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9648dda3cb
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feat(cpu): implement like 1 THUMB instruction
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2022-01-14 07:26:27 -04:00 |
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0cf052838d
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chore(cpu): lay groundwork for THUMB instruction decoding and execution
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2022-01-14 05:23:16 -04:00 |
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ae37b1218b
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chore(cpu): refactor ARM functions to make room for THUMB
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2022-01-14 04:26:09 -04:00 |
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37bd6758fb
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fix(cpu): fix imm value calculation in MSR
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2022-01-14 04:08:04 -04:00 |
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7f6ab626d9
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fix(cpu): resolve off-by-one error when executing LDM
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2022-01-14 03:43:03 -04:00 |
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77dba68a0b
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feat(cpu): implement branch and exchange
If I want to continue with armwrestler, I'll have to implement
THUMB instructions now
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2022-01-12 07:20:24 -04:00 |
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7adc7c8802
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fix(cpu): make Data Processing instructions r15-aware
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2022-01-12 07:20:24 -04:00 |
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229f7c3388
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fix(cpu): make LDRH and STRH aware of r15
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2022-01-12 07:20:21 -04:00 |
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5812b9713c
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fix(cpu): account for r15 in LDR and STR instructions
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2022-01-12 06:16:59 -04:00 |
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98c5803208
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fix(cpu): flip two branches in PSR Transfer execution
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2022-01-12 06:16:34 -04:00 |
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74abd3df4d
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feat(cpu): implement MSR and MRS
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2022-01-12 04:48:57 -04:00 |
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7531af7f2b
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feat(cpu): stub PSR Transfer instructions
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2022-01-12 03:40:51 -04:00 |
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072a66cfdb
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fix(cpu): write results of ORR to destination register
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2022-01-10 10:56:41 -04:00 |
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ed3bdd90fb
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feat(cpu): implement TEQ
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2022-01-10 08:09:02 -04:00 |
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e9c1c94cae
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feat(cpu): Implement ORR
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2022-01-10 08:06:00 -04:00 |
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22b95b2a74
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feat(cpu): refactor LDM/STM
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2022-01-10 06:51:32 -04:00 |
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7d79a0bee2
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feat(cpu): implement LDM/STM
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2022-01-10 06:27:36 -04:00 |
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0d8c5e6882
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fix(cpu): fix off-by-word bug in BL
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2022-01-10 06:26:02 -04:00 |
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0d4c850218
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chore: remove premature inlines
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2022-01-10 01:24:14 -04:00 |
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568c374131
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chore: code cleanup
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2022-01-07 20:00:42 -04:00 |
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910745f442
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chore(bus): refactor bus.zig
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2022-01-07 19:49:58 -04:00 |
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f8c6af3247
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chore: refactor instruction exec code
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2022-01-07 19:44:48 -04:00 |
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5037b8f0cc
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feat: implement S (when rd != 15) for several data processing instructions
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2022-01-05 15:45:52 -05:00 |
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28a70d0112
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feat: implement dedicated Barrel Shifter SHL and SHR
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2022-01-05 13:58:11 -05:00 |
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7473ffedc7
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chore: stub TST
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2022-01-04 04:08:02 -06:00 |
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28bb410dfd
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fix(cpu): improve LDR/STR write-back logic
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2022-01-04 03:55:41 -06:00 |
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ed9c1413b1
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fix(cpu): properly implement SUB/CMP CSPSR carry bit condition
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2022-01-04 03:08:08 -06:00 |
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8cabcd8901
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fix(cpu): resolve reversed if statement + write back on W = 0
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2022-01-04 01:57:37 -06:00 |
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44d52d8137
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feat(cpu): properly implement STR STRH and STRB
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2022-01-03 17:48:43 -06:00 |
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1c42d1795a
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feat(bus): add Io Struct
Also, add more information to all panic messages
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2022-01-02 14:40:49 -06:00 |
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de9045fba3
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chore: use bitfield library
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2022-01-02 13:01:11 -06:00 |
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65c3dd722c
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feat(bus): implement Gameboy Advance MMIO
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2022-01-02 02:36:06 -06:00 |
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c40a1af534
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chore: conform to zig style guides
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2022-01-01 21:08:47 -06:00 |
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92a06e49c3
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chore(cpu): iron out some false assumptions
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2022-01-01 03:41:50 -06:00 |
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c660ca8922
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feat: implement LDR STR
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2021-12-29 17:16:32 -06:00 |
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7cc3f40a85
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chore: run zig fmt
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2021-12-29 15:13:50 -06:00 |
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5b3b81e4dc
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Initial Commit
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2021-12-29 15:09:00 -06:00 |
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