chore: code cleanup

src/Bus.zig

@@ -1,10 +1,10 @@
 const std = @import("std");
 
-const Scheduler = @import("scheduler.zig").Scheduler;
-const Io = @import("bus/io.zig").Io;
 const Bios = @import("bus/Bios.zig");
 const GamePak = @import("bus/GamePak.zig");
+const Io = @import("bus/io.zig").Io;
 const Ppu = @import("ppu.zig").Ppu;
+const Scheduler = @import("scheduler.zig").Scheduler;
 
 const Allocator = std.mem.Allocator;
 

src/bus/io.zig

@@ -1,8 +1,7 @@
 const std = @import("std");
-const bitfield = @import("bitfield");
 
-const Bitfield = bitfield.Bitfield;
-const Bit = bitfield.Bit;
+const Bit = @import("bitfield").Bit;
+const Bitfield = @import("bitfield").Bitfield;
 
 pub const Io = struct {
     const Self = @This();

src/cpu.zig

@@ -1,14 +1,12 @@
 const std = @import("std");
 const util = @import("util.zig");
-const bitfield = @import("bitfield");
 
 const BarrelShifter = @import("cpu/barrel_shifter.zig");
 const Bus = @import("Bus.zig");
+const Bit = @import("bitfield").Bit;
+const Bitfield = @import("bitfield").Bitfield;
 const Scheduler = @import("scheduler.zig").Scheduler;
 
-const Bitfield = bitfield.Bitfield;
-const Bit = bitfield.Bit;
-
 const dataProcessing = @import("cpu/data_processing.zig").dataProcessing;
 const singleDataTransfer = @import("cpu/single_data_transfer.zig").singleDataTransfer;
 const halfAndSignedDataTransfer = @import("cpu/half_signed_data_transfer.zig").halfAndSignedDataTransfer;

src/cpu/barrel_shifter.zig

@@ -1,8 +1,7 @@
 const std = @import("std");
 
-const arm = @import("../cpu.zig");
-const Arm7tdmi = arm.Arm7tdmi;
-const CPSR = arm.CPSR;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const CPSR = @import("../cpu.zig").CPSR;
 
 pub inline fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     var shift_amt: u8 = undefined;

src/cpu/branch.zig

@@ -1,10 +1,8 @@
-const arm = @import("../cpu.zig");
 const util = @import("../util.zig");
 
 const Bus = @import("../Bus.zig");
-
-const Arm7tdmi = arm.Arm7tdmi;
-const InstrFn = arm.InstrFn;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../cpu.zig").InstrFn;
 
 pub fn branch(comptime L: bool) InstrFn {
     return struct {

src/cpu/data_processing.zig

@@ -1,10 +1,9 @@
 const std = @import("std");
-const arm = @import("../cpu.zig");
 
 const BarrelShifter = @import("barrel_shifter.zig");
 const Bus = @import("../Bus.zig");
-const Arm7tdmi = arm.Arm7tdmi;
-const InstrFn = arm.InstrFn;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../cpu.zig").InstrFn;
 
 pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
     return struct {

src/cpu/half_signed_data_transfer.zig

@@ -1,10 +1,9 @@
 const std = @import("std");
-const arm = @import("../cpu.zig");
 const util = @import("../util.zig");
 
 const Bus = @import("../Bus.zig");
-const Arm7tdmi = arm.Arm7tdmi;
-const InstrFn = arm.InstrFn;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../cpu.zig").InstrFn;
 
 pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
     return struct {

src/cpu/single_data_transfer.zig

@@ -1,12 +1,11 @@
 const std = @import("std");
 const util = @import("../util.zig");
-const arm = @import("../cpu.zig");
 
 const BarrelShifter = @import("barrel_shifter.zig");
 const Bus = @import("../Bus.zig");
-const Arm7tdmi = arm.Arm7tdmi;
-const InstrFn = arm.InstrFn;
-const CPSR = arm.CPSR;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const CPSR = @import("../cpu.zig").CPSR;
+const InstrFn = @import("../cpu.zig").InstrFn;
 
 pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
     return struct {

src/main.zig

@@ -1,9 +1,9 @@
 const std = @import("std");
 const emu = @import("emu.zig");
 
-const Scheduler = @import("scheduler.zig").Scheduler;
 const Bus = @import("Bus.zig");
 const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
+const Scheduler = @import("scheduler.zig").Scheduler;
 
 pub fn main() anyerror!void {
     var gpa = std.heap.GeneralPurposeAllocator(.{}){};

src/ppu.zig

@@ -1,8 +1,9 @@
 const std = @import("std");
 
-const Allocator = std.mem.Allocator;
-const Scheduler = @import("scheduler.zig").Scheduler;
 const EventKind = @import("scheduler.zig").EventKind;
+const Scheduler = @import("scheduler.zig").Scheduler;
+
+const Allocator = std.mem.Allocator;
 
 pub const Ppu = struct {
     vram: Vram,

src/scheduler.zig

@@ -2,6 +2,7 @@ const std = @import("std");
 
 const Bus = @import("Bus.zig");
 const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
+
 const Order = std.math.Order;
 const PriorityQueue = std.PriorityQueue;
 const Allocator = std.mem.Allocator;

src/util.zig

@@ -1,13 +1,12 @@
 const std = @import("std");
-const assert = std.debug.assert;
 
 pub fn signExtend(comptime T: type, comptime bits: usize, value: anytype) T {
     const ValT = comptime @TypeOf(value);
-    comptime assert(isInteger(ValT));
-    comptime assert(isSigned(ValT));
+    comptime std.debug.assert(isInteger(ValT));
+    comptime std.debug.assert(isSigned(ValT));
 
     const value_bits = @typeInfo(ValT).Int.bits;
-    comptime assert(value_bits >= bits);
+    comptime std.debug.assert(value_bits >= bits);
 
     const bit_diff = value_bits - bits;