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fix(cpu): make Data Processing instructions r15-aware

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-01-12 06:54:22 -04:00
parent 229f7c3388
commit 7adc7c8802
2 changed files with 31 additions and 20 deletions
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22
src/cpu/barrel_shifter.zig
View File

@ -12,21 +12,27 @@ pub fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
}
const rm = cpu.r[opcode & 0xF];
var value: u32 = undefined;
if (rm == 0xF) {
value = cpu.fakePC() + 4; // 12 ahead
} else {
value = cpu.r[opcode & 0xF];
}
if (S) {
return switch (@truncate(u2, opcode >> 5)) {
0b00 => logical_left(&cpu.cpsr, rm, shift_amt),
0b01 => logical_right(&cpu.cpsr, rm, shift_amt),
0b10 => arithmetic_right(&cpu.cpsr, rm, shift_amt),
0b11 => rotate_right(&cpu.cpsr, rm, shift_amt),
0b00 => logical_left(&cpu.cpsr, value, shift_amt),
0b01 => logical_right(&cpu.cpsr, value, shift_amt),
0b10 => arithmetic_right(&cpu.cpsr, value, shift_amt),
0b11 => rotate_right(&cpu.cpsr, value, shift_amt),
};
} else {
var dummy = CPSR{ .raw = 0x0000_0000 };
return switch (@truncate(u2, opcode >> 5)) {
0b00 => logical_left(&dummy, rm, shift_amt),
0b01 => logical_right(&dummy, rm, shift_amt),
0b10 => arithmetic_right(&dummy, rm, shift_amt),
0b11 => rotate_right(&dummy, rm, shift_amt),
0b00 => logical_left(&dummy, value, shift_amt),
0b01 => logical_right(&dummy, value, shift_amt),
0b10 => arithmetic_right(&dummy, value, shift_amt),
0b11 => rotate_right(&dummy, value, shift_amt),
};
}
}

29
src/cpu/data_processing.zig
View File

@ -9,24 +9,29 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
return struct {
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
const rd = opcode >> 12 & 0xF;
const op1 = opcode >> 16 & 0xF;
const rn = opcode >> 16 & 0xF;
if (S and rd == 0xF) std.debug.panic("[CPU] Data Processing Instruction w/ S set and Rd == 15", .{});
var op1: u32 = undefined;
if (rn == 0xF) {
op1 = cpu.fakePC();
} else {
op1 = cpu.r[rn];
}
var op2: u32 = undefined;
if (I) {
op2 = std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1);
} else {
if (S and rd == 0xF) {
std.debug.panic("[CPU] Data Processing Instruction w/ S set and Rd == 15", .{});
} else {
op2 = BarrelShifter.exec(S, cpu, opcode);
}
op2 = BarrelShifter.exec(S, cpu, opcode);
}
switch (instrKind) {
0x4 => {
// ADD
var result: u32 = undefined;
const didOverflow = @addWithOverflow(u32, cpu.r[op1], op2, &result);
const didOverflow = @addWithOverflow(u32, op1, op2, &result);
cpu.r[rd] = result;
if (S and rd != 0xF) {
@ -38,7 +43,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
},
0x8 => {
// TST
const result = cpu.r[op1] & op2;
const result = op1 & op2;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
@ -47,7 +52,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
},
0x9 => {
// TEQ
const result = cpu.r[op1] ^ op2;
const result = op1 ^ op2;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
@ -66,16 +71,16 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
},
0xA => {
// CMP
const result = cpu.r[op1] -% op2;
const result = op1 -% op2;
cpu.cpsr.n.write(result >> 31 & 1 == 1);
cpu.cpsr.z.write(result == 0);
cpu.cpsr.c.write(op2 <= cpu.r[op1]);
cpu.cpsr.c.write(op2 <= op1);
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
},
0xC => {
// ORR
const result = cpu.r[op1] | op2;
const result = op1 | op2;
cpu.r[rd] = result;
if (S and rd != 0xF) {