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fix(cpu): improve LDR/STR write-back logic

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-01-04 03:55:41 -06:00
parent 5ea888f68c
commit 28bb410dfd
2 changed files with 7 additions and 8 deletions
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13
src/cpu/half_signed_data_transfer.zig
View File

@ -34,18 +34,17 @@ pub fn comptimeHalfSignedDataTransfer(comptime P: bool, comptime U: bool, compti
},
0b01 => {
// LDRH
const halfword = bus.read16(address);
cpu.r[rd] = @as(u32, halfword);
cpu.r[rd] = bus.read16(address);
},
0b10 => {
// LDRSB
const byte = bus.read8(address);
cpu.r[rd] = util.u32SignExtend(8, @as(u32, byte));
cpu.r[rd] = util.u32SignExtend(8, @as(u32, bus.read8(address)));
std.debug.panic("TODO: Affect the CPSR", .{});
},
0b11 => {
// LDRSH
const halfword = bus.read16(address);
cpu.r[rd] = util.u32SignExtend(16, @as(u32, halfword));
cpu.r[rd] = util.u32SignExtend(16, @as(u32, bus.read16(address)));
std.debug.panic("TODO: Affect the CPSR", .{});
},
}
} else {
@ -58,7 +57,7 @@ pub fn comptimeHalfSignedDataTransfer(comptime P: bool, comptime U: bool, compti
}
address = modified_base;
if (W and P) cpu.r[rn] = address;
if (W and P or !P) cpu.r[rn] = address;
}
}.halfSignedDataTransfer;
}

2
src/cpu/single_data_transfer.zig
View File

@ -40,7 +40,7 @@ pub fn comptimeSingleDataTransfer(comptime I: bool, comptime P: bool, comptime U
}
address = modified_base;
if (W and P or !W) cpu.r[rn] = address;
if (W and P or !P) cpu.r[rn] = address;
// TODO: W-bit forces non-privledged mode for the transfer
}