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211 Commits

Author SHA1 Message Date
Rekai Nyangadzayi Musuka f9013cf9db Merge branch 'main' of ssh://musuka.dev:2222/paoda/zba 2022-02-10 23:02:35 -04:00
Rekai Nyangadzayi Musuka eaac49cebb chore: update README 2022-02-10 21:21:34 -04:00
Rekai Nyangadzayi Musuka ee27053db3 chore: remove TODOs and some useless imports 2022-02-06 19:07:23 -04:00
Rekai Nyangadzayi Musuka 7441dd151c fix: improper condition check and initialization of register 2022-02-06 18:41:16 -04:00
Rekai Nyangadzayi Musuka bbd4447734 fix(cpu): force align thumb and arm block data transfers 2022-02-06 17:08:12 -04:00
Rekai Nyangadzayi Musuka 225c0f7d55 feat: pass arm.gba 2022-02-06 05:06:25 -04:00
Rekai Nyangadzayi Musuka fcde905ae1 chore: reimplement ARM LDM/STM 2022-02-06 04:34:45 -04:00
Rekai Nyangadzayi Musuka 798987eba0 chore: improve arm ldm/stm 2022-02-05 23:29:34 -04:00
Rekai Nyangadzayi Musuka adfd501fc4 fix(cpu): force-align SWP reads and writes 2022-02-05 23:18:23 -04:00
Rekai Nyangadzayi Musuka 9581e3b3cb fix: force-align ARM STRH reads 2022-02-05 23:09:13 -04:00
Rekai Nyangadzayi Musuka 1b9ab1f1d7 fix: implement the same LDRSH logic as THUMB LDRSH 2022-02-05 23:09:02 -04:00
Rekai Nyangadzayi Musuka c52dc5adb1 fix: PC is 12 ahead when it is rd in str and strb 2022-02-05 21:42:04 -04:00
Rekai Nyangadzayi Musuka 7bfb87a859 fix: listen to my past self 
By deleting this line I go from test 234 to test 355 in arm.gba
 2022-02-05 21:35:26 -04:00
Rekai Nyangadzayi Musuka aec189ac6a chore: update SDL.zig 2022-02-05 21:07:15 -04:00
Rekai Nyangadzayi Musuka 0aece06107 chore: dont use std.mem.bytesToValue 
the stdlib accounts for endianness, which isn't something we want.
 2022-02-05 21:05:08 -04:00
Rekai Nyangadzayi Musuka 2842345111 chore: remove unnecessary @as calls 2022-02-05 21:01:39 -04:00
Rekai Nyangadzayi Musuka aa6f3c7a92 feat: pass thumb.gba 2022-02-05 20:39:15 -04:00
Rekai Nyangadzayi Musuka 3ae24d6977 chore: account for empty rlist in THUMB LDM/STM 2022-02-05 18:03:39 -04:00
Rekai Nyangadzayi Musuka 0a22730479 fix(cpu): handle edge case in LDRSH 2022-02-05 17:12:25 -04:00
Rekai Nyangadzayi Musuka 166bc6fc6d chore: specify which compiler this project is built with 2022-02-05 16:28:06 -04:00
Rekai Nyangadzayi Musuka bf4207ba8c chore: reorganize util.zig 2022-02-05 15:55:12 -04:00
Rekai Nyangadzayi Musuka 78080b4682 fix: zero initialize all allocated memory 2022-02-05 15:54:53 -04:00
Rekai Nyangadzayi Musuka 9159270e87 chore: don't commit *.sh files 2022-02-05 15:53:30 -04:00
Rekai Nyangadzayi Musuka 428eff1468 Revert "fix: allow for 32-bit reads to KEYINPUT" 
This reverts commit 3a51707280.
 2022-02-05 14:52:49 -04:00
Rekai Nyangadzayi Musuka 5ec8d4b0a5 fix: resolve decoding mixup in THUMB format 8 instructions 2022-02-05 14:50:34 -04:00
Rekai Nyangadzayi Musuka 3a51707280 fix: allow for 32-bit reads to KEYINPUT 2022-02-05 13:47:05 -04:00
Rekai Nyangadzayi Musuka b4d20fb264 chore: refactor ARMv4 decoding 2022-02-05 13:46:55 -04:00
Rekai Nyangadzayi Musuka 746158043d chore: add more debug information to CPU panic method 2022-02-05 13:46:24 -04:00
Rekai Nyangadzayi Musuka 25300c8a9f chore: give more descriptive panic messages when changing mode fails 2022-02-04 16:54:57 -04:00
Rekai Nyangadzayi Musuka 27d0ba8c7e chore: clean up THUMB instruction decoding 2022-02-04 15:57:46 -04:00
Rekai Nyangadzayi Musuka 2f74b61f2e feat: parse cartridge header 2022-02-04 05:54:06 -04:00
Rekai Nyangadzayi Musuka b233981a34 feat: rename ARM and THUMB SWI functions 2022-02-04 04:34:47 -04:00
Rekai Nyangadzayi Musuka 1b8db0c427 chore: group THUMB and select ARM instructions together (same file) 2022-02-04 04:18:20 -04:00
Rekai Nyangadzayi Musuka 3e4f9eddb2 feat: integrate zig-clap with ZBA 2022-02-04 03:12:35 -04:00
Rekai Nyangadzayi Musuka 6ab4610a81 fix(cpu): properly decode format 7 and 8 2022-02-03 01:29:18 -04:00
Rekai Nyangadzayi Musuka 91384a7c68 fix(cpu): resolve edge cases in THUMB Format 5 2022-02-03 00:55:57 -04:00
Rekai Nyangadzayi Musuka c6bb4bf8e1 fix(cpu): allow for select values to overflow 
FuzzARM found these operations which panicked, when they should
have overflowed. These are now fixed

n = 8000
 2022-02-02 22:49:33 -04:00
Rekai Nyangadzayi Musuka 800ed6f1a7 feat(cpu): implement format 13 
While bugs do exist, at this point all THUMB and ARMv4 instructions
have been implemented! Yay!
 2022-02-02 22:31:21 -04:00
Rekai Nyangadzayi Musuka 027e4fb57b feat(cpu): implement THUMB format 17 2022-02-02 22:31:08 -04:00
Rekai Nyangadzayi Musuka 1378c809e6 feat(cpu): implement THUMB format11 2022-02-02 22:30:46 -04:00
Rekai Nyangadzayi Musuka 33399e9517 chore: update to latest zig nightly 2022-02-02 21:26:12 -04:00
Rekai Nyangadzayi Musuka 99492a6782 chore: progress towards passing ldr/str thumb in armwrestler 2022-02-02 21:14:46 -04:00
Rekai Nyangadzayi Musuka 8b574efe85 fix(cpu): properly negate in NEG 2022-02-02 20:12:20 -04:00
Rekai Nyangadzayi Musuka 9fd03d2a92 fix(cpu): reimplement THUMB offset shifts 2022-02-02 20:12:07 -04:00
Rekai Nyangadzayi Musuka 9affe01da8 fix(cpu): op == 0b00 decodes to add in format 5 2022-02-02 18:58:06 -04:00
Rekai Nyangadzayi Musuka 784bc81a4a fix(cpu): account for overflow in THUMB alu MUL 2022-02-02 18:57:33 -04:00
Rekai Nyangadzayi Musuka 045c98de1f chore: use if-else when decoding THUMB instructions 2022-02-02 18:48:47 -04:00
Rekai Nyangadzayi Musuka c2901ee0d8 fix(cpu): account for rn in rlist in block data transfer 2022-02-02 17:35:33 -04:00
Rekai Nyangadzayi Musuka d95efa5b12 feat: implement LDM/STM behaviour when S is set 2022-02-02 16:12:47 -04:00
Rekai Nyangadzayi Musuka 237beb9caa feat(cpu): Pass all LDR/STR ARMwrestler tests 2022-02-02 14:07:18 -04:00