 Rekai Nyangadzayi Musuka
|
ae37b1218b
|
chore(cpu): refactor ARM functions to make room for THUMB
|
2022-01-14 04:26:09 -04:00 |
|
Rekai Nyangadzayi Musuka
|
070322064d
|
fix(cpu): fix conditions for GT cond
|
2022-01-14 04:19:54 -04:00 |
|
Rekai Nyangadzayi Musuka
|
37bd6758fb
|
fix(cpu): fix imm value calculation in MSR
|
2022-01-14 04:08:04 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7f6ab626d9
|
fix(cpu): resolve off-by-one error when executing LDM
|
2022-01-14 03:43:03 -04:00 |
|
Rekai Nyangadzayi Musuka
|
77dba68a0b
|
feat(cpu): implement branch and exchange
If I want to continue with armwrestler, I'll have to implement
THUMB instructions now
|
2022-01-12 07:20:24 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7adc7c8802
|
fix(cpu): make Data Processing instructions r15-aware
|
2022-01-12 07:20:24 -04:00 |
|
Rekai Nyangadzayi Musuka
|
229f7c3388
|
fix(cpu): make LDRH and STRH aware of r15
|
2022-01-12 07:20:21 -04:00 |
|
Rekai Nyangadzayi Musuka
|
5812b9713c
|
fix(cpu): account for r15 in LDR and STR instructions
|
2022-01-12 06:16:59 -04:00 |
|
Rekai Nyangadzayi Musuka
|
98c5803208
|
fix(cpu): flip two branches in PSR Transfer execution
|
2022-01-12 06:16:34 -04:00 |
|
Rekai Nyangadzayi Musuka
|
74abd3df4d
|
feat(cpu): implement MSR and MRS
|
2022-01-12 04:48:57 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7531af7f2b
|
feat(cpu): stub PSR Transfer instructions
|
2022-01-12 03:40:51 -04:00 |
|
Rekai Nyangadzayi Musuka
|
1c173eb4b8
|
chore(io): implement IE and IME
|
2022-01-12 02:19:26 -04:00 |
|
Rekai Nyangadzayi Musuka
|
769c67b9d4
|
chore: remove some magic constants
|
2022-01-12 00:46:20 -04:00 |
|
Rekai Nyangadzayi Musuka
|
3596caf106
|
Merge branch 'main' of ssh://musuka.dev:2222/paoda/zba
|
2022-01-11 02:36:37 -04:00 |
|
Rekai Nyangadzayi Musuka
|
3be084cb82
|
chore: ignores for building on windows
|
2022-01-11 01:42:26 -04:00 |
|
Rekai Nyangadzayi Musuka
|
c1be53bcb2
|
fix(bus): remove accidental recursion
|
2022-01-10 21:25:45 -04:00 |
|
Rekai Nyangadzayi Musuka
|
072a66cfdb
|
fix(cpu): write results of ORR to destination register
|
2022-01-10 10:56:41 -04:00 |
|
Rekai Nyangadzayi Musuka
|
ed3bdd90fb
|
feat(cpu): implement TEQ
|
2022-01-10 08:09:02 -04:00 |
|
Rekai Nyangadzayi Musuka
|
e9c1c94cae
|
feat(cpu): Implement ORR
|
2022-01-10 08:06:00 -04:00 |
|
Rekai Nyangadzayi Musuka
|
0f08ad05be
|
feat(bus): implement IWRAM and EWRAM
|
2022-01-10 07:59:21 -04:00 |
|
Rekai Nyangadzayi Musuka
|
fd5006b29d
|
fix(ppu): properly access Mode 4 palette
|
2022-01-10 07:23:54 -04:00 |
|
Rekai Nyangadzayi Musuka
|
22b95b2a74
|
feat(cpu): refactor LDM/STM
|
2022-01-10 06:51:32 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7d79a0bee2
|
feat(cpu): implement LDM/STM
|
2022-01-10 06:27:36 -04:00 |
|
Rekai Nyangadzayi Musuka
|
6c0651ca08
|
chore(io): DISPSTAT bits 3 and 4 better match GBATEK documentation
|
2022-01-10 06:26:42 -04:00 |
|
Rekai Nyangadzayi Musuka
|
0d8c5e6882
|
fix(cpu): fix off-by-word bug in BL
|
2022-01-10 06:26:02 -04:00 |
|
Rekai Nyangadzayi Musuka
|
89a8fe403b
|
feat(bus): have VCOUNT be addressable on the bus
|
2022-01-10 03:35:28 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7c5d2d2389
|
feat(ppu): implement Mode 4
Implementation is not tested. Pending on LDM and STM so that I can
run beeg.gba
|
2022-01-10 03:35:24 -04:00 |
|
Rekai Nyangadzayi Musuka
|
2467b94dbd
|
chore(io): rename some io bitfield fields
|
2022-01-10 02:13:25 -04:00 |
|
Rekai Nyangadzayi Musuka
|
0d4c850218
|
chore: remove premature inlines
|
2022-01-10 01:24:14 -04:00 |
|
Rekai Nyangadzayi Musuka
|
bbe2ecfa53
|
chore: add FPS counter
|
2022-01-10 01:22:55 -04:00 |
|
Rekai Nyangadzayi Musuka
|
c54145ce3c
|
chore: improve code clarity
|
2022-01-09 23:34:33 -04:00 |
|
Rekai Nyangadzayi Musuka
|
ead6d1ce49
|
feat(ppu): improve timings + implement BG mode 3 bitmap
|
2022-01-09 22:16:34 -04:00 |
|
Rekai Nyangadzayi Musuka
|
581285a434
|
fix: allocate framebuf on heap
|
2022-01-08 20:30:57 -04:00 |
|
Rekai Nyangadzayi Musuka
|
0d203543ca
|
chore: add code for heap alloc of white texture
|
2022-01-08 18:52:11 -04:00 |
|
Rekai Nyangadzayi Musuka
|
eb6c00f0ac
|
chore(gui): switch from RGBA8888 to BGR5555 to match BG Mode 3
|
2022-01-08 04:54:39 -04:00 |
|
Rekai Nyangadzayi Musuka
|
da7f21f47e
|
feat: draw white texture using SDL2
|
2022-01-07 22:46:17 -04:00 |
|
Rekai Nyangadzayi Musuka
|
8fb666624f
|
fix(ppu): deallocate palette RAM on cleanup
|
2022-01-07 22:27:08 -04:00 |
|
Rekai Nyangadzayi Musuka
|
568c374131
|
chore: code cleanup
|
2022-01-07 20:00:42 -04:00 |
|
Rekai Nyangadzayi Musuka
|
910745f442
|
chore(bus): refactor bus.zig
|
2022-01-07 19:49:58 -04:00 |
|
Rekai Nyangadzayi Musuka
|
f8c6af3247
|
chore: refactor instruction exec code
|
2022-01-07 19:44:48 -04:00 |
|
Rekai Nyangadzayi Musuka
|
a407671de2
|
chore(io): alias @This() to Self in io.zig
|
2022-01-07 19:34:54 -04:00 |
|
Rekai Nyangadzayi Musuka
|
e9ec124e33
|
chore: refactor bios.zig and pak.zig
|
2022-01-07 19:33:49 -04:00 |
|
Rekai Nyangadzayi Musuka
|
9f64804763
|
fix: by convention deinit() should not take pointers to self
|
2022-01-07 19:16:23 -04:00 |
|
Rekai Nyangadzayi Musuka
|
c6123d8a6d
|
feat: implement PPU Timings in Scheduler
|
2022-01-05 21:18:33 -04:00 |
|
Rekai Nyangadzayi Musuka
|
f709458638
|
feat(sched): add HBlank and VBlank events to the scheduler
|
2022-01-05 17:34:59 -05:00 |
|
Rekai Nyangadzayi Musuka
|
5037b8f0cc
|
feat: implement S (when rd != 15) for several data processing instructions
|
2022-01-05 15:45:52 -05:00 |
|
Rekai Nyangadzayi Musuka
|
28a70d0112
|
feat: implement dedicated Barrel Shifter SHL and SHR
|
2022-01-05 13:58:11 -05:00 |
|
Rekai Nyangadzayi Musuka
|
7473ffedc7
|
chore: stub TST
|
2022-01-04 04:08:02 -06:00 |
|
Rekai Nyangadzayi Musuka
|
172f3e8efe
|
chore: comment-out logging by default
|
2022-01-04 03:58:11 -06:00 |
|
Rekai Nyangadzayi Musuka
|
28bb410dfd
|
fix(cpu): improve LDR/STR write-back logic
|
2022-01-04 03:55:41 -06:00 |