 Rekai Nyangadzayi Musuka
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dc6931639f
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fix(cpu): don't ignore 11th bit of THUMB BL offset
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2022-01-29 23:53:40 -04:00 |
|
Rekai Nyangadzayi Musuka
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e18f10126e
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feat(cpu): implement thumb push / pop and stub format 13 thumb instrs
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2022-01-29 23:22:10 -04:00 |
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Rekai Nyangadzayi Musuka
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0598ba402d
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feat(cpu): implement THUMB format 9 loads / stores
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2022-01-29 22:34:40 -04:00 |
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Rekai Nyangadzayi Musuka
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b8a9aaee86
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fix(cpu): resolve issues with unexpected PC value in THUMB
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2022-01-29 22:07:36 -04:00 |
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Rekai Nyangadzayi Musuka
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00058f6094
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feat(cpu): implement THUMB ldmia stmia
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2022-01-29 21:10:14 -04:00 |
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Rekai Nyangadzayi Musuka
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2dde47318c
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chore: implement THUMB format 4 instructions
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2022-01-29 20:42:13 -04:00 |
|
Rekai Nyangadzayi Musuka
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ae4023e51c
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chore: dedup code in THUMB instructions
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2022-01-29 20:05:27 -04:00 |
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Rekai Nyangadzayi Musuka
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bce067557f
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chore: refactor and genericize ARM data processing calculations
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2022-01-29 19:40:58 -04:00 |
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Rekai Nyangadzayi Musuka
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e0acabf050
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chore: relocate barrel_shifter zig file
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2022-01-29 18:52:16 -04:00 |
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Rekai Nyangadzayi Musuka
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599e068c7e
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feat(cpu): implement format2 THUMB instructions
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2022-01-29 18:46:27 -04:00 |
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Rekai Nyangadzayi Musuka
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4ca65caef0
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feat(cpu): implement format19 THUMB instructions
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2022-01-29 18:25:50 -04:00 |
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Rekai Nyangadzayi Musuka
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44dbdba48c
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feat(cpu): implement format16 THUMB instructions
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2022-01-29 17:44:04 -04:00 |
|
Rekai Nyangadzayi Musuka
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d85e0c8d05
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feat(cpu): implement format 1 THUMB instructions
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2022-01-29 17:29:30 -04:00 |
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Rekai Nyangadzayi Musuka
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cfbd292edc
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feat(cpu): implement format 6 THUMB instructions
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2022-01-29 01:18:41 -04:00 |
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Rekai Nyangadzayi Musuka
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fbc5b309b0
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chore: binary logging + file logging + DP chanes + fastBoot changes
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2022-01-25 18:18:52 -04:00 |
|
Rekai Nyangadzayi Musuka
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997dc1314c
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feat(cpu): implement SWI
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2022-01-25 10:34:21 -04:00 |
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Rekai Nyangadzayi Musuka
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6257418405
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fix(cpu): interim solution to weird program counter behaviour on illegal tst instruction
|
2022-01-25 09:23:32 -04:00 |
|
Rekai Nyangadzayi Musuka
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985fefb9f6
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chore(cpu): implement behaviour for undefined test instruction
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2022-01-25 08:05:42 -04:00 |
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Rekai Nyangadzayi Musuka
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95dd3e3df8
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fix(cpu): fix PC offset when barrel shifter and bit 4 of DP is set
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2022-01-24 17:52:01 -04:00 |
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Rekai Nyangadzayi Musuka
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702ff288d8
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fix(cpu): implement S set + rd == 15 case for data processing
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2022-01-19 07:46:49 -04:00 |
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Rekai Nyangadzayi Musuka
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bf36a23722
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feat(cpu): implement banked registers
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2022-01-19 07:29:49 -04:00 |
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Rekai Nyangadzayi Musuka
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fc5a3460dd
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fix(cpu): improve MRS and MSR instructions
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2022-01-18 20:17:00 -04:00 |
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Rekai Nyangadzayi Musuka
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6177927049
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feat(cpu): implement CMN
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2022-01-18 15:09:25 -04:00 |
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Rekai Nyangadzayi Musuka
|
903b75c7c4
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fix(barrel_shifter): fix PC being 1 word ahead in barrel shifter
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2022-01-18 15:08:29 -04:00 |
|
Rekai Nyangadzayi Musuka
|
8d786cbe25
|
feat(cpu): Implement RSC
|
2022-01-18 14:46:57 -04:00 |
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Rekai Nyangadzayi Musuka
|
212bc9e11d
|
feat(cpu): implement RSB
|
2022-01-18 14:36:03 -04:00 |
|
Rekai Nyangadzayi Musuka
|
63a57ac954
|
feat(cpu): implement BIC
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2022-01-18 14:28:47 -04:00 |
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Rekai Nyangadzayi Musuka
|
85dae5e1d7
|
feat(cpu): implement EOR
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2022-01-18 14:27:07 -04:00 |
|
Rekai Nyangadzayi Musuka
|
6189bf0315
|
feat(cpu): implement ADD
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2022-01-18 14:25:29 -04:00 |
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Rekai Nyangadzayi Musuka
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2f3213f693
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feat(cpu): implement fix for ADC and implement SBC
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2022-01-18 14:20:01 -04:00 |
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Rekai Nyangadzayi Musuka
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a62cd9aa40
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chore(barrel_shifter): remove panic from ASR
|
2022-01-18 14:19:58 -04:00 |
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Rekai Nyangadzayi Musuka
|
25c57a4cc7
|
fix(barrel_shifter): should not modify cpsr when amount == 0
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2022-01-18 13:30:41 -04:00 |
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Rekai Nyangadzayi Musuka
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a7a44c4463
|
chore(cpu): refactor the barrel shifter once again
|
2022-01-17 15:55:55 -04:00 |
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Rekai Nyangadzayi Musuka
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d4d2fedfbe
|
feat(cpu): implement ADC
ADC interacting w/ the Barrel Shifter is not working though
|
2022-01-17 14:29:34 -04:00 |
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Rekai Nyangadzayi Musuka
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483e149b32
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feat(cpu): implement RRX for Barrel Shifter
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2022-01-17 14:19:40 -04:00 |
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Rekai Nyangadzayi Musuka
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85ffdf44f5
|
feat(cpu): implement SUB in THUMB format 3
|
2022-01-17 11:36:02 -04:00 |
|
Rekai Nyangadzayi Musuka
|
9098a55ae3
|
feat(cpu): implement ARM SUB in data processing
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2022-01-17 11:35:41 -04:00 |
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Rekai Nyangadzayi Musuka
|
c0d956ea95
|
feat(cpu): implement MVN
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2022-01-17 11:30:59 -04:00 |
|
Rekai Nyangadzayi Musuka
|
1025500407
|
chore(cpu): refactor barrel shifter
|
2022-01-17 11:17:04 -04:00 |
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Rekai Nyangadzayi Musuka
|
d05a924420
|
fix(cpu): use barrel shifter in data processing immediates
|
2022-01-17 11:02:34 -04:00 |
|
Rekai Nyangadzayi Musuka
|
2a416fb2c6
|
feat(cpu): implement format 12 thumb instructions
|
2022-01-17 10:07:50 -04:00 |
|
Rekai Nyangadzayi Musuka
|
ea5f0ce552
|
feat(cpu): implement some already decoded format 3 instructions
|
2022-01-17 09:29:11 -04:00 |
|
Rekai Nyangadzayi Musuka
|
e55d2dc323
|
feat(cpu): implement THUMB format 5 instructions
|
2022-01-17 09:28:46 -04:00 |
|
Rekai Nyangadzayi Musuka
|
1915d98bdd
|
feat(cpu): implement like 1 THUMB instruction
|
2022-01-16 12:46:59 -04:00 |
|
Rekai Nyangadzayi Musuka
|
0cf052838d
|
chore(cpu): lay groundwork for THUMB instruction decoding and execution
|
2022-01-14 05:23:16 -04:00 |
|
Rekai Nyangadzayi Musuka
|
ae37b1218b
|
chore(cpu): refactor ARM functions to make room for THUMB
|
2022-01-14 04:26:09 -04:00 |
|
Rekai Nyangadzayi Musuka
|
37bd6758fb
|
fix(cpu): fix imm value calculation in MSR
|
2022-01-14 04:08:04 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7f6ab626d9
|
fix(cpu): resolve off-by-one error when executing LDM
|
2022-01-14 03:43:03 -04:00 |
|
Rekai Nyangadzayi Musuka
|
77dba68a0b
|
feat(cpu): implement branch and exchange
If I want to continue with armwrestler, I'll have to implement
THUMB instructions now
|
2022-01-12 07:20:24 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7adc7c8802
|
fix(cpu): make Data Processing instructions r15-aware
|
2022-01-12 07:20:24 -04:00 |
|
Rekai Nyangadzayi Musuka
|
229f7c3388
|
fix(cpu): make LDRH and STRH aware of r15
|
2022-01-12 07:20:21 -04:00 |
|
Rekai Nyangadzayi Musuka
|
5812b9713c
|
fix(cpu): account for r15 in LDR and STR instructions
|
2022-01-12 06:16:59 -04:00 |
|
Rekai Nyangadzayi Musuka
|
98c5803208
|
fix(cpu): flip two branches in PSR Transfer execution
|
2022-01-12 06:16:34 -04:00 |
|
Rekai Nyangadzayi Musuka
|
74abd3df4d
|
feat(cpu): implement MSR and MRS
|
2022-01-12 04:48:57 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7531af7f2b
|
feat(cpu): stub PSR Transfer instructions
|
2022-01-12 03:40:51 -04:00 |
|
Rekai Nyangadzayi Musuka
|
072a66cfdb
|
fix(cpu): write results of ORR to destination register
|
2022-01-10 10:56:41 -04:00 |
|
Rekai Nyangadzayi Musuka
|
ed3bdd90fb
|
feat(cpu): implement TEQ
|
2022-01-10 08:09:02 -04:00 |
|
Rekai Nyangadzayi Musuka
|
e9c1c94cae
|
feat(cpu): Implement ORR
|
2022-01-10 08:06:00 -04:00 |
|
Rekai Nyangadzayi Musuka
|
22b95b2a74
|
feat(cpu): refactor LDM/STM
|
2022-01-10 06:51:32 -04:00 |
|
Rekai Nyangadzayi Musuka
|
7d79a0bee2
|
feat(cpu): implement LDM/STM
|
2022-01-10 06:27:36 -04:00 |
|
Rekai Nyangadzayi Musuka
|
0d8c5e6882
|
fix(cpu): fix off-by-word bug in BL
|
2022-01-10 06:26:02 -04:00 |
|
Rekai Nyangadzayi Musuka
|
0d4c850218
|
chore: remove premature inlines
|
2022-01-10 01:24:14 -04:00 |
|
Rekai Nyangadzayi Musuka
|
568c374131
|
chore: code cleanup
|
2022-01-07 20:00:42 -04:00 |
|
Rekai Nyangadzayi Musuka
|
910745f442
|
chore(bus): refactor bus.zig
|
2022-01-07 19:49:58 -04:00 |
|
Rekai Nyangadzayi Musuka
|
f8c6af3247
|
chore: refactor instruction exec code
|
2022-01-07 19:44:48 -04:00 |
|
Rekai Nyangadzayi Musuka
|
5037b8f0cc
|
feat: implement S (when rd != 15) for several data processing instructions
|
2022-01-05 15:45:52 -05:00 |
|
Rekai Nyangadzayi Musuka
|
28a70d0112
|
feat: implement dedicated Barrel Shifter SHL and SHR
|
2022-01-05 13:58:11 -05:00 |
|
Rekai Nyangadzayi Musuka
|
7473ffedc7
|
chore: stub TST
|
2022-01-04 04:08:02 -06:00 |
|
Rekai Nyangadzayi Musuka
|
28bb410dfd
|
fix(cpu): improve LDR/STR write-back logic
|
2022-01-04 03:55:41 -06:00 |
|
Rekai Nyangadzayi Musuka
|
ed9c1413b1
|
fix(cpu): properly implement SUB/CMP CSPSR carry bit condition
|
2022-01-04 03:08:08 -06:00 |
|
Rekai Nyangadzayi Musuka
|
8cabcd8901
|
fix(cpu): resolve reversed if statement + write back on W = 0
|
2022-01-04 01:57:37 -06:00 |
|
Rekai Nyangadzayi Musuka
|
44d52d8137
|
feat(cpu): properly implement STR STRH and STRB
|
2022-01-03 17:48:43 -06:00 |
|
Rekai Nyangadzayi Musuka
|
1c42d1795a
|
feat(bus): add Io Struct
Also, add more information to all panic messages
|
2022-01-02 14:40:49 -06:00 |
|
Rekai Nyangadzayi Musuka
|
de9045fba3
|
chore: use bitfield library
|
2022-01-02 13:01:11 -06:00 |
|
Rekai Nyangadzayi Musuka
|
65c3dd722c
|
feat(bus): implement Gameboy Advance MMIO
|
2022-01-02 02:36:06 -06:00 |
|
Rekai Nyangadzayi Musuka
|
c40a1af534
|
chore: conform to zig style guides
|
2022-01-01 21:08:47 -06:00 |
|
Rekai Nyangadzayi Musuka
|
92a06e49c3
|
chore(cpu): iron out some false assumptions
|
2022-01-01 03:41:50 -06:00 |
|
Rekai Nyangadzayi Musuka
|
c660ca8922
|
feat: implement LDR STR
|
2021-12-29 17:16:32 -06:00 |
|
Rekai Nyangadzayi Musuka
|
7cc3f40a85
|
chore: run zig fmt
|
2021-12-29 15:13:50 -06:00 |
|
Rekai Nyangadzayi Musuka
|
5b3b81e4dc
|
Initial Commit
|
2021-12-29 15:09:00 -06:00 |