feat(cpu): implement THUMB format 5 instructions
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@ -18,6 +18,7 @@ const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
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// THUMB Instruction Groups
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const format3 = @import("cpu/thumb/format3.zig").format3;
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const format5 = @import("cpu/thumb/format5.zig").format5;
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pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
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pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
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@ -160,6 +161,14 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
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lut[i] = format3(op, rd);
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}
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if (i >> 4 & 0x3F == 0b010001) {
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const op = i >> 2 & 0x3;
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const h1 = i >> 1 & 1;
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const h2 = i & 1;
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lut[i] = format5(op, h1, h2);
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}
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}
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return lut;
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@ -0,0 +1,35 @@
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const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const src = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
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const dst = @as(u4, h1) << 3 | (opcode & 0x7);
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switch (op) {
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0b01 => {
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// CMP
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const left = cpu.r[dst];
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const right = cpu.r[src];
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const result = left -% right;
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cpu.cpsr.n.write(result >> 31 & 1 == 1);
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cpu.cpsr.z.write(result == 0);
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cpu.cpsr.c.write(right <= left);
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cpu.cpsr.v.write(((left ^ result) & (~right ^ result)) >> 31 & 1 == 1);
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},
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0b10 => cpu.r[dst] = cpu.r[src], // MOV
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0b11 => {
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// BX
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cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
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cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
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},
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else => std.debug.panic("[CPU] Op #{} is invalid for THUMB Format 5", .{op}),
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}
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}
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}.inner;
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}
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