0010029783
fix: LDR(S)H behaviour differs between ARMv4/ARMv5TE
2024-03-11 10:52:28 -05:00
6f0e271360
fix: update to 0.12.0-dev.2063+804cee3b9
2024-02-08 23:09:04 -06:00
bdc4bfc642
dbg: add dbgRead and dbgWrite fns to cpu struct
2024-01-13 16:10:05 -06:00
580e7baca9
fix: make Bank.spsrIndex public
2023-12-27 18:52:28 -06:00
aad3bdc9ea
feat: pass nds arm7wrestler
...
- impl behaviour of running v5te instrs on v4t cpu
- impl undefined instruction exception handler
- panic on what I think are still unimplemented v5te opcodes
2023-12-27 00:13:06 -06:00
dcff3fd588
fix(v5te): account for high vectors in swi
2023-10-09 19:28:04 -05:00
8d2a3f1b67
feat(v5te): let cp15 affect more tcm behaviours
...
cp15 can now enable/disable ITCM/DTCM. cp15 can also now enable/disable load mode.
TODO: load mode doesn't effect SWP/SWPB for some reason?
2023-09-29 23:34:46 -05:00
1bd96304ba
fix: off-by-one when handling TCM addresses
2023-09-29 02:35:21 -05:00
481271ba2a
fix(v4t/v5te): resolve critical error in ldm/stm obscure behaviour
2023-09-26 20:46:30 -05:00
2c5d474c56
fix(v5te): fix off by one in DTCM handler
2023-09-20 00:29:49 -05:00
4d3814db36
fix(v5te): set T on select load instrs when rd == 15
2023-09-20 00:29:47 -05:00
502647806c
feat(v5te): stub THUMB BKPT
2023-09-20 00:29:44 -05:00
3c5d4acc5f
feat(v5te): implement THUMB BLX(1), BLX(2), and ARM BLX
2023-09-20 00:29:42 -05:00
37b3fe3d10
fix(v5te): properly implement SMLAL<x><y>
2023-09-20 00:29:38 -05:00
106820b444
fix(v5te): properly implement qadd/qsub qdadd/qdsub
2023-09-19 21:24:31 -05:00
a3eefa6432
chore: panic TODO on Unconditional address space
2023-09-15 14:50:29 -05:00
30cf951d2a
feat: integrate cp15 and TCM code
2023-09-15 14:20:24 -05:00
71541c312c
chore: semi-pass more rockwrestler tests
2023-09-15 14:20:21 -05:00
514e4d6014
feat: implement Coprocessor Interface
2023-09-15 14:20:17 -05:00
5d70e4bd1d
chore(v4t,v5te): don't give SWP/SWPB its own separate handler
2023-09-09 03:39:21 -05:00
253cbbcdff
feat(v5te): impl BLX, QDADD/QDSUB, SMLAL<x><y>, SMLAW<y>, SMULW<y>, SMUL<x><y>
2023-09-09 03:04:44 -05:00
c94912887e
feat(v5te): implement SMLA<x><y>
2023-09-07 20:00:19 -05:00
819eace2a7
feat: implement QADD/QSUB
2023-09-07 03:39:51 -05:00
177f9b55a9
fix(v5te): rework MSR/MRS handling to account for v5TE extension space
2023-09-07 01:26:51 -05:00
6dde25bd0f
fix(arm): group multiply instructions together
...
- implement clz in ARMv5TE
2023-09-07 01:26:51 -05:00
44b59512c0
feat(v5te): implement clz
2023-09-07 01:26:51 -05:00
ea3db88bec
feat(v5te): stub LDRD / STRD
2023-09-07 01:26:51 -05:00
67bae5dcb4
fix: ensure order of operations to prevent regression in arm.gba
2023-09-06 20:04:00 -05:00
e6863e7a9b
fix(armv5te): implement obscure behaviour on invalid LDM writeback
...
All I have to do is implement ARMv5TE specific instructions, and then
we're finished with ARMWRESTLER!
2023-09-06 01:29:08 -05:00
591352a65b
fix: Arm32 should represent generic, not pointer to generic
2023-09-05 21:38:22 -05:00
ada2a08516
feat(v5te): implement basic DTCM + ITCM
2023-07-26 00:14:32 -05:00
ba22b856ec
chore: drop *Bus argument from the InstrFn LUT
2023-07-25 22:00:17 -05:00
f31c4bdb65
feat: stub coprocessor instructions
2023-07-25 22:00:17 -05:00
96a3a45d9b
feat: add v5te arm and thumb namespaces
...
also, drop the comptime parameter from arm and thumb namespaces
2023-07-25 22:00:17 -05:00
2af9c351bc
feat: allow lib use as git-submodule
2023-07-25 22:00:17 -05:00
6c81608c59
fix: remove redundant casts from zig fmt
2023-07-11 00:39:14 -05:00
a831ab22fe
chore: update dependencies
2023-07-10 22:16:24 -05:00
f8c2479ed9
chore: update to latest builtin syntax
2023-07-10 22:00:59 -05:00
90d5c19e01
feat: implement debug i/o in Bus Interface
2023-06-29 23:27:24 -05:00
3c8a87c14d
chore: expose arm namespace
2023-06-25 18:54:57 -05:00
fa54f194a1
feat: expose module for zig build system
2023-06-25 18:54:57 -05:00
d2db52e495
feat: implement ARM7TDMI (and stub ARM946E-S)
2023-06-25 18:54:57 -05:00
c8e78c42ec
feat: initial commit
2023-06-25 01:04:02 -05:00
