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chore: update to latest builtin syntax

This commit is contained in:
Rekai Nyangadzayi Musuka 2023-07-10 22:00:59 -05:00
parent 90d5c19e01
commit f8c2479ed9
15 changed files with 69 additions and 73 deletions
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10
src/arm.zig
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@ -174,7 +174,7 @@ pub fn Arm32(comptime arch: Architecture) type {
}
pub fn setCpsr(self: *Self, value: u32) void {
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@as(u5, @truncate(value & 0x1F)));
self.cpsr.raw = value;
}
@ -257,7 +257,7 @@ pub fn Arm32(comptime arch: Architecture) type {
},
}
self.cpsr.mode.write(@enumToInt(next));
self.cpsr.mode.write(@intFromEnum(next));
}
pub fn step(self: *Self) void {
@ -267,12 +267,12 @@ pub fn Arm32(comptime arch: Architecture) type {
}
if (self.cpsr.t.read()) {
const opcode = @truncate(u16, self.pipe.step(self, u16) orelse return);
const opcode = @as(u16, @truncate(self.pipe.step(self, u16) orelse return));
thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
} else {
const opcode = self.pipe.step(self, u32) orelse return;
if (self.cpsr.check(@truncate(u4, opcode >> 28))) {
if (self.cpsr.check(@as(u4, @truncate(opcode >> 28)))) {
arm.lut[arm.idx(opcode)](self, self.bus, opcode);
}
}
@ -391,7 +391,7 @@ pub const PSR = extern union {
}
pub inline fn check(self: @This(), cond: u4) bool {
const flags = @truncate(u4, self.raw >> 28);
const flags = @as(u4, @truncate(self.raw >> 28));
return condition_lut[cond] & (@as(u16, 1) << flags) != 0;
}

4
src/arm/cpu/arm/block_data_transfer.zig
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@ -5,7 +5,7 @@ pub fn blockDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: b
return struct {
fn inner(cpu: Arm32, bus: Bus, opcode: u32) void {
const rn = @truncate(u4, opcode >> 16 & 0xF);
const rn = @as(u4, @truncate(opcode >> 16 & 0xF));
const rlist = opcode & 0xFFFF;
const r15 = rlist >> 15 & 1 == 1;
@ -15,7 +15,7 @@ pub fn blockDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: b
var write_to_base = true;
while (i < 16) : (i += 1) {
const r = @truncate(u4, 15 - i);
const r = @as(u4, @truncate(15 - i));
if (rlist >> r & 1 == 1) {
first = r;
count += 1;

8
src/arm/cpu/arm/data_processing.zig
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@ -8,16 +8,16 @@ pub fn dataProcessing(comptime InstrFn: type, comptime I: bool, comptime S: bool
return struct {
fn inner(cpu: Arm32, _: Bus, opcode: u32) void {
const rd = @truncate(u4, opcode >> 12 & 0xF);
const rd = @as(u4, @truncate(opcode >> 12 & 0xF));
const rn = opcode >> 16 & 0xF;
const old_carry = @boolToInt(cpu.cpsr.c.read());
const old_carry = @intFromBool(cpu.cpsr.c.read());
// If certain conditions are met, PC is 12 ahead instead of 8
// TODO: Why these conditions?
if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
const op1 = cpu.r[rn];
const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
const amount = @as(u8, @truncate((opcode >> 8 & 0xF) << 1));
const op2 = if (I) ror(S, &cpu.cpsr, opcode & 0xFF, amount) else exec(S, cpu, opcode);
// Undo special condition from above
@ -164,7 +164,7 @@ pub fn dataProcessing(comptime InstrFn: type, comptime I: bool, comptime S: bool
pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
// TODO: Make your own version (thanks peach.bot)
const subtrahend = @as(u64, right) -% old_carry +% 1;
const ret = @truncate(u32, left -% subtrahend);
const ret = @as(u32, @truncate(left -% subtrahend));
return ret;
}

6
src/arm/cpu/arm/half_signed_data_transfer.zig
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@ -21,7 +21,7 @@ pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, compt
var result: u32 = undefined;
if (L) {
switch (@truncate(u2, opcode >> 5)) {
switch (@as(u2, @truncate(opcode >> 5))) {
0b01 => {
// LDRH
const value = bus.read(u16, address);
@ -34,14 +34,14 @@ pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, compt
0b11 => {
// LDRSH
const value = bus.read(u16, address);
result = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value);
result = if (address & 1 == 1) sext(u32, u8, @as(u8, @truncate(value >> 8))) else sext(u32, u16, value);
},
0b00 => unreachable, // SWP
}
} else {
if (opcode >> 5 & 0x01 == 0x01) {
// STRH
bus.write(u16, address, @truncate(u16, cpu.r[rd]));
bus.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
} else unreachable; // SWP
}

14
src/arm/cpu/arm/multiply.zig
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@ -11,7 +11,7 @@ pub fn multiply(comptime InstrFn: type, comptime A: bool, comptime S: bool) Inst
const rm = opcode & 0xF;
const temp: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]) + if (A) cpu.r[rn] else 0;
const result = @truncate(u32, temp);
const result = @as(u32, @truncate(temp));
cpu.r[rd] = result;
if (S) {
@ -35,18 +35,18 @@ pub fn multiplyLong(comptime InstrFn: type, comptime U: bool, comptime A: bool,
if (U) {
// Signed (WHY IS IT U THEN?)
var result: i64 = @as(i64, @bitCast(i32, cpu.r[rm])) * @as(i64, @bitCast(i32, cpu.r[rs]));
if (A) result +%= @bitCast(i64, @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]));
var result: i64 = @as(i64, @as(i32, @bitCast(cpu.r[rm]))) * @as(i64, @as(i32, @bitCast(cpu.r[rs])));
if (A) result +%= @as(i64, @bitCast(@as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo])));
cpu.r[rd_hi] = @bitCast(u32, @truncate(i32, result >> 32));
cpu.r[rd_lo] = @bitCast(u32, @truncate(i32, result));
cpu.r[rd_hi] = @as(u32, @bitCast(@as(i32, @truncate(result >> 32))));
cpu.r[rd_lo] = @as(u32, @bitCast(@as(i32, @truncate(result))));
} else {
// Unsigned
var result: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]);
if (A) result +%= @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]);
cpu.r[rd_hi] = @truncate(u32, result >> 32);
cpu.r[rd_lo] = @truncate(u32, result);
cpu.r[rd_hi] = @as(u32, @truncate(result >> 32));
cpu.r[rd_lo] = @as(u32, @truncate(result));
}
if (S) {

4
src/arm/cpu/arm/psr_transfer.zig
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@ -22,7 +22,7 @@ pub fn psrTransfer(comptime InstrFn: type, comptime I: bool, comptime R: bool, c
},
0b10 => {
// MSR
const field_mask = @truncate(u4, opcode >> 16 & 0xF);
const field_mask = @as(u4, @truncate(opcode >> 16 & 0xF));
const rm_idx = opcode & 0xF;
const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) * 2) else cpu.r[rm_idx];
@ -46,7 +46,7 @@ pub fn psrTransfer(comptime InstrFn: type, comptime I: bool, comptime R: bool, c
fn fieldMask(psr: *const PSR, field_mask: u4, right: u32) u32 {
// This bitwise ORs bits 3 and 0 of the field mask into a u2
// We do this because we only care about bits 7:0 and 31:28 of the CPSR
const bits = @truncate(u2, (field_mask >> 2 & 0x2) | (field_mask & 1));
const bits = @as(u2, @truncate((field_mask >> 2 & 0x2) | (field_mask & 1)));
const mask: u32 = switch (bits) {
0b00 => 0x0000_0000,

2
src/arm/cpu/arm/single_data_swap.zig
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@ -16,7 +16,7 @@ pub fn singleDataSwap(comptime InstrFn: type, comptime B: bool) InstrFn {
if (B) {
// SWPB
const value = bus.read(u8, address);
bus.write(u8, address, @truncate(u8, cpu.r[rm]));
bus.write(u8, address, @as(u8, @truncate(cpu.r[rm])));
cpu.r[rd] = value;
} else {
// SWP

2
src/arm/cpu/arm/single_data_transfer.zig
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@ -31,7 +31,7 @@ pub fn singleDataTransfer(comptime InstrFn: type, comptime I: bool, comptime P:
if (B) {
// STRB
const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
bus.write(u8, address, @truncate(u8, value));
bus.write(u8, address, @as(u8, @truncate(value)));
} else {
// STR
const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);

26
src/arm/cpu/barrel_shifter.zig
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@ -16,9 +16,9 @@ pub fn exec(comptime S: bool, cpu: anytype, opcode: u32) u32 {
fn register(comptime S: bool, cpu: anytype, opcode: u32) u32 {
const rs_idx = opcode >> 8 & 0xF;
const rm = cpu.r[opcode & 0xF];
const rs = @truncate(u8, cpu.r[rs_idx]);
const rs = @as(u8, @truncate(cpu.r[rs_idx]));
return switch (@truncate(u2, opcode >> 5)) {
return switch (@as(u2, @truncate(opcode >> 5))) {
0b00 => lsl(S, &cpu.cpsr, rm, rs),
0b01 => lsr(S, &cpu.cpsr, rm, rs),
0b10 => asr(S, &cpu.cpsr, rm, rs),
@ -27,12 +27,12 @@ fn register(comptime S: bool, cpu: anytype, opcode: u32) u32 {
}
pub fn immediate(comptime S: bool, cpu: anytype, opcode: u32) u32 {
const amount = @truncate(u8, opcode >> 7 & 0x1F);
const amount = @as(u8, @truncate(opcode >> 7 & 0x1F));
const rm = cpu.r[opcode & 0xF];
var result: u32 = undefined;
if (amount == 0) {
switch (@truncate(u2, opcode >> 5)) {
switch (@as(u2, @truncate(opcode >> 5))) {
0b00 => {
// LSL #0
result = rm;
@ -44,19 +44,19 @@ pub fn immediate(comptime S: bool, cpu: anytype, opcode: u32) u32 {
},
0b10 => {
// ASR #0 aka ASR #32
result = @bitCast(u32, @bitCast(i32, rm) >> 31);
result = @as(u32, @bitCast(@as(i32, @bitCast(rm)) >> 31));
if (S) cpu.cpsr.c.write(result >> 31 & 1 == 1);
},
0b11 => {
// ROR #0 aka RRX
const carry: u32 = @boolToInt(cpu.cpsr.c.read());
const carry: u32 = @intFromBool(cpu.cpsr.c.read());
if (S) cpu.cpsr.c.write(rm & 1 == 1);
result = (carry << 31) | (rm >> 1);
},
}
} else {
switch (@truncate(u2, opcode >> 5)) {
switch (@as(u2, @truncate(opcode >> 5))) {
0b00 => result = lsl(S, &cpu.cpsr, rm, amount),
0b01 => result = lsr(S, &cpu.cpsr, rm, amount),
0b10 => result = asr(S, &cpu.cpsr, rm, amount),
@ -68,7 +68,7 @@ pub fn immediate(comptime S: bool, cpu: anytype, opcode: u32) u32 {
}
pub fn lsl(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
const amount = @truncate(u5, total_amount);
const amount = @as(u5, @truncate(total_amount));
const bit_count: u8 = @typeInfo(u32).Int.bits;
var result: u32 = 0x0000_0000;
@ -77,7 +77,7 @@ pub fn lsl(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
result = rm << amount;
if (S and total_amount != 0) {
const carry_bit = @truncate(u5, bit_count - amount);
const carry_bit = @as(u5, @truncate(bit_count - amount));
cpsr.c.write(rm >> carry_bit & 1 == 1);
}
} else {
@ -95,7 +95,7 @@ pub fn lsl(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
}
pub fn lsr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 {
const amount = @truncate(u5, total_amount);
const amount = @as(u5, @truncate(total_amount));
const bit_count: u8 = @typeInfo(u32).Int.bits;
var result: u32 = 0x0000_0000;
@ -119,16 +119,16 @@ pub fn lsr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 {
}
pub fn asr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
const amount = @truncate(u5, total_amount);
const amount = @as(u5, @truncate(total_amount));
const bit_count: u8 = @typeInfo(u32).Int.bits;
var result: u32 = 0x0000_0000;
if (total_amount < bit_count) {
result = @bitCast(u32, @bitCast(i32, rm) >> amount);
result = @as(u32, @bitCast(@as(i32, @bitCast(rm)) >> amount));
if (S and total_amount != 0) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
} else {
// ASR #32 and ASR #>32 have the same result
result = @bitCast(u32, @bitCast(i32, rm) >> 31);
result = @as(u32, @bitCast(@as(i32, @bitCast(rm)) >> 31));
if (S) cpsr.c.write(result >> 31 & 1 == 1);
}

12
src/arm/cpu/thumb/alu.zig
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@ -15,7 +15,7 @@ pub fn fmt4(comptime InstrFn: type, comptime op: u4) InstrFn {
fn inner(cpu: Arm32, _: Bus, opcode: u16) void {
const rs = opcode >> 3 & 0x7;
const rd = opcode & 0x7;
const carry = @boolToInt(cpu.cpsr.c.read());
const carry = @intFromBool(cpu.cpsr.c.read());
const op1 = cpu.r[rd];
const op2 = cpu.r[rs];
@ -26,12 +26,12 @@ pub fn fmt4(comptime InstrFn: type, comptime op: u4) InstrFn {
switch (op) {
0x0 => result = op1 & op2, // AND
0x1 => result = op1 ^ op2, // EOR
0x2 => result = lsl(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSL
0x3 => result = lsr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSR
0x4 => result = asr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ASR
0x2 => result = lsl(true, &cpu.cpsr, op1, @as(u8, @truncate(op2))), // LSL
0x3 => result = lsr(true, &cpu.cpsr, op1, @as(u8, @truncate(op2))), // LSR
0x4 => result = asr(true, &cpu.cpsr, op1, @as(u8, @truncate(op2))), // ASR
0x5 => result = adc(&overflow, op1, op2, carry), // ADC
0x6 => result = sbc(op1, op2, carry), // SBC
0x7 => result = ror(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ROR
0x7 => result = ror(true, &cpu.cpsr, op1, @as(u8, @truncate(op2))), // ROR
0x8 => result = op1 & op2, // TST
0x9 => result = 0 -% op2, // NEG
0xA => result = op1 -% op2, // CMP
@ -42,7 +42,7 @@ pub fn fmt4(comptime InstrFn: type, comptime op: u4) InstrFn {
overflow = tmp[1];
},
0xC => result = op1 | op2, // ORR
0xD => result = @truncate(u32, @as(u64, op2) * @as(u64, op1)),
0xD => result = @as(u32, @truncate(@as(u64, op2) * @as(u64, op1))),
0xE => result = op1 & ~op2,
0xF => result = ~op2,
}

2
src/arm/cpu/thumb/block_data_transfer.zig
View File

@ -5,7 +5,7 @@ pub fn fmt14(comptime InstrFn: type, comptime L: bool, comptime R: bool) InstrFn
return struct {
fn inner(cpu: Arm32, bus: Bus, opcode: u16) void {
const count = @boolToInt(R) + countRlist(opcode);
const count = @intFromBool(R) + countRlist(opcode);
const start = cpu.r[13] - if (!L) count * 4 else 0;
var end = cpu.r[13];

4
src/arm/cpu/thumb/data_processing.zig
View File

@ -36,7 +36,7 @@ pub fn fmt1(comptime InstrFn: type, comptime op: u2, comptime offset: u5) InstrF
// ASR
if (offset == 0) {
cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
break :blk @as(u32, @bitCast(@as(i32, @bitCast(cpu.r[rs])) >> 31));
} else {
break :blk asr(true, &cpu.cpsr, cpu.r[rs], offset);
}
@ -115,7 +115,7 @@ pub fn fmt2(comptime InstrFn: type, comptime I: bool, is_sub: bool, rn: u3) Inst
return struct {
fn inner(cpu: Arm32, _: Bus, opcode: u16) void {
const rs = opcode >> 3 & 0x7;
const rd = @truncate(u3, opcode);
const rd = @as(u3, @truncate(opcode));
const op1 = cpu.r[rs];
const op2: u32 = if (I) rn else cpu.r[rn];

10
src/arm/cpu/thumb/data_transfer.zig
View File

@ -33,7 +33,7 @@ pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn
switch (op) {
0b00 => {
// STRH
bus.write(u16, address, @truncate(u16, cpu.r[rd]));
bus.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
},
0b01 => {
// LDSB
@ -47,7 +47,7 @@ pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn
0b11 => {
// LDRSH
const value = bus.read(u16, address);
cpu.r[rd] = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value);
cpu.r[rd] = if (address & 1 == 1) sext(u32, u8, @as(u8, @truncate(value >> 8))) else sext(u32, u16, value);
},
}
} else {
@ -59,7 +59,7 @@ pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn
},
0b01 => {
// STRB
bus.write(u8, address, @truncate(u8, cpu.r[rd]));
bus.write(u8, address, @as(u8, @truncate(cpu.r[rd])));
},
0b10 => {
// LDR
@ -99,7 +99,7 @@ pub fn fmt9(comptime InstrFn: type, comptime B: bool, comptime L: bool, comptime
if (B) {
// STRB
const address = cpu.r[rb] + offset;
bus.write(u8, address, @truncate(u8, cpu.r[rd]));
bus.write(u8, address, @as(u8, @truncate(cpu.r[rd])));
} else {
// STR
const address = cpu.r[rb] + (@as(u32, offset) << 2);
@ -126,7 +126,7 @@ pub fn fmt10(comptime InstrFn: type, comptime L: bool, comptime offset: u5) Inst
cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
} else {
// STRH
bus.write(u16, address, @truncate(u16, cpu.r[rd]));
bus.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
}
}
}.inner;

4
src/arm/v4t.zig
View File

@ -20,7 +20,7 @@ pub fn arm(comptime Arm32: type) type {
/// Determine index into ARM InstrFn LUT
pub fn idx(opcode: u32) u12 {
return @truncate(u12, opcode >> 20 & 0xFF) << 4 | @truncate(u12, opcode >> 4 & 0xF);
return @as(u12, @truncate(opcode >> 20 & 0xFF)) << 4 | @as(u12, @truncate(opcode >> 4 & 0xF));
}
// Undefined ARM Instruction handler
@ -117,7 +117,7 @@ pub fn thumb(comptime Arm32: type) type {
/// Determine index into THUMB InstrFn LUT
pub fn idx(opcode: u16) u10 {
return @truncate(u10, opcode >> 6);
return @as(u10, @truncate(opcode >> 6));
}
/// Undefined THUMB Instruction Handler

34
src/lib.zig
View File

@ -64,71 +64,69 @@ pub const Bus = struct {
std.debug.assert(info.Pointer.size == .One); // Single-Item Pointer
std.debug.assert(@typeInfo(info.Pointer.child) == .Struct); // Pointer Child is a `struct`
const alignment = info.Pointer.alignment;
const impl = struct {
fn read8(ptr: *anyopaque, address: u32) u8 {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
return self.read(u8, address);
}
fn read16(ptr: *anyopaque, address: u32) u16 {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
return self.read(u16, address);
}
fn read32(ptr: *anyopaque, address: u32) u32 {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
return self.read(u32, address);
}
fn write8(ptr: *anyopaque, address: u32, value: u8) void {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
self.write(u8, address, value);
}
fn write16(ptr: *anyopaque, address: u32, value: u16) void {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
self.write(u16, address, value);
}
fn write32(ptr: *anyopaque, address: u32, value: u32) void {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
self.write(u32, address, value);
}
fn dbgRead8(ptr: *anyopaque, address: u32) u8 {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
return self.dbgRead(u8, address);
}
fn dbgRead16(ptr: *anyopaque, address: u32) u16 {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
return self.dbgRead(u16, address);
}
fn dbgRead32(ptr: *anyopaque, address: u32) u32 {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
return self.dbgRead(u32, address);
}
fn dbgWrite8(ptr: *anyopaque, address: u32, value: u8) void {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
self.dbgWrite(u8, address, value);
}
fn dbgWrite16(ptr: *anyopaque, address: u32, value: u16) void {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
self.dbgWrite(u16, address, value);
}
fn dbgWrite32(ptr: *anyopaque, address: u32, value: u32) void {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
self.dbgWrite(u32, address, value);
}
fn reset(ptr: *anyopaque) void {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
self.reset();
}
};
@ -213,16 +211,14 @@ pub const Scheduler = struct {
std.debug.assert(info.Pointer.size == .One); // Single-Item Pointer
std.debug.assert(@typeInfo(info.Pointer.child) == .Struct); // Pointer Child is a `struct`
const alignment = info.Pointer.alignment;
const impl = struct {
fn now(ptr: *anyopaque) u64 {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
return self.now();
}
fn reset(ptr: *anyopaque) void {
const self = @ptrCast(P, @alignCast(alignment, ptr));
const self: P = @ptrCast(@alignCast(ptr));
self.reset();
}
};