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dbg: add dbgRead and dbgWrite fns to cpu struct

This commit is contained in:
Rekai Nyangadzayi Musuka 2024-01-13 16:08:33 -06:00
parent 580e7baca9
commit bdc4bfc642
1 changed files with 18 additions and 0 deletions
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18
src/arm.zig
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@ -217,6 +217,24 @@ pub fn Arm32(comptime isa: Architecture) type {
}
};
pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
if (is_v5te) {
if (self.itcm.read(T, address)) |val| return val;
if (self.dtcm.read(T, address)) |val| return val;
}
return self.bus.dbgRead(T, address);
}
pub fn dbgWrite(self: *Self, comptime T: type, address: u32, value: T) void {
if (is_v5te) {
if (self.itcm.write(T, address, value)) return;
if (self.dtcm.write(T, address, value)) return;
}
return self.bus.dbgWrite(T, address, value);
}
// CPU needs it's own read/write fns due to ICTM and DCTM present in v5te
// I considered implementing Bus.cpu_read and Bus.cpu_write but ended up considering that a bit too leaky
pub fn read(self: *Self, comptime T: type, address: u32) T {