feat: implement Coprocessor Interface
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parent
5d70e4bd1d
commit
514e4d6014
90
src/arm.zig
90
src/arm.zig
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@ -4,6 +4,7 @@ const Architecture = enum { v4t, v5te };
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const Interpreter = @import("lib.zig").Interpreter;
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const Bus = @import("lib.zig").Bus;
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const Scheduler = @import("lib.zig").Scheduler;
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const Coprocessor = @import("lib.zig").Coprocessor;
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const Bitfield = @import("bitfield").Bitfield;
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const Bit = @import("bitfield").Bit;
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@ -46,6 +47,7 @@ pub fn Arm32(comptime isa: Architecture) type {
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// The following will be `void` on.v4t but exist on v5te
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itcm: if (is_v5te) Itcm else void,
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dtcm: if (is_v5te) Dtcm else void,
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cp15: if (is_v5te) Coprocessor else void,
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const arm = switch (isa) {
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.v4t => @import("arm/v4t.zig").arm,
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@ -154,17 +156,64 @@ pub fn Arm32(comptime isa: Architecture) type {
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}
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};
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pub fn init(scheduler: Scheduler, bus: Bus) Self {
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return .{
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.sched = scheduler,
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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// FIXME: Is this a hack or idiomatic?
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// See https://github.com/ziglang/zig/blob/1a0e6bcdb140c844384d62b78a7f4247753f9ffd/lib/std/atomic/Atomic.zig#L156-L176
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pub usingnamespace if (is_v5te) struct {
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// FIXME: this is pretty NDS9 specific lol
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pub fn init(scheduler: Scheduler, bus: Bus, cp15: Coprocessor) Self {
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return .{
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.sched = scheduler,
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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.dtcm = if (is_v5te) .{} else {},
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.itcm = if (is_v5te) .{} else {},
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};
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}
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.cp15 = cp15,
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.dtcm = .{},
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.itcm = .{},
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};
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}
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// FIXME: Resetting disables logging (if enabled)
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pub fn reset(self: *Self) void {
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self.* = .{
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.sched = self.sched,
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.bus = self.bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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.dtcm = .{},
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.itcm = .{},
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.cp15 = self.cp15,
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};
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}
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} else struct {
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pub fn init(scheduler: Scheduler, bus: Bus) Self {
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return .{
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.sched = scheduler,
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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.cp15 = {},
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.dtcm = {},
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.itcm = {},
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};
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}
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// FIXME: Resetting disables logging (if enabled)
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pub fn reset(self: *Self) void {
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self.* = .{
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.sched = self.sched,
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.bus = self.bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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.dtcm = {},
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.itcm = {},
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.cp15 = {},
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};
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}
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};
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// CPU needs it's own read/write fns due to ICTM and DCTM present in v5te
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// I considered implementing Bus.cpu_read and Bus.cpu_write but ended up considering that a bit too leaky
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@ -179,10 +228,10 @@ pub fn Arm32(comptime isa: Architecture) type {
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// FIXME: verify correctness + can this be faster?
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if (itcm_base < address and address < itcm_base + itcm_size)
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return readInt(T, self.itcm.buf[address & 0x0000_7FFF ..][0..@sizeOf(T)]);
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return readInt(T, self.itcm.buf[address..][0..@sizeOf(T)]);
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if (dtcm_base < address and address < dtcm_base + dtcm_size)
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return readInt(T, self.itcm.buf[address & 0x0000_3FFF ..][0..@sizeOf(T)]);
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return readInt(T, self.dtcm.buf[address..][0..@sizeOf(T)]);
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}
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return self.bus.read(T, address);
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@ -199,28 +248,15 @@ pub fn Arm32(comptime isa: Architecture) type {
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// FIXME: verify correctness + can this be faster?
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if (itcm_base < address and address < itcm_base + itcm_size)
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return writeInt(T, self.itcm.buf[address & 0x0000_7FFF ..][0..@sizeOf(T)], value);
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return writeInt(T, self.itcm.buf[address..][0..@sizeOf(T)], value);
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if (dtcm_base < address and address < dtcm_base + dtcm_size)
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return writeInt(T, self.itcm.buf[address & 0x0000_3FFF ..][0..@sizeOf(T)], value);
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return writeInt(T, self.dtcm.buf[address..][0..@sizeOf(T)], value);
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}
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return self.bus.write(T, address, value);
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}
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// FIXME: Resetting disables logging (if enabled)
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pub fn reset(self: *Self) void {
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self.* = .{
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.sched = self.sched,
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.bus = self.bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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.dtcm = if (is_v5te) .{} else {},
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.itcm = if (is_v5te) .{} else {},
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};
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}
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pub inline fn hasSPSR(self: *const Self) bool {
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const mode = Mode.getChecked(self, self.cpsr.mode.read());
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return switch (mode) {
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241
src/lib.zig
241
src/lib.zig
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@ -32,6 +32,38 @@ pub const Interpreter = union(enum) {
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}
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};
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test "create ARMv4T interface" {
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var bus_impl = ExampleBus{};
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var scheduler_impl = ExampleScheduler{};
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const bus_interface = Bus.init(&bus_impl);
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const scheduler_interface = Scheduler.init(&scheduler_impl);
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var arm7tdmi = Arm7tdmi.init(scheduler_interface, bus_interface);
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var icpu = arm7tdmi.interface();
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icpu.reset();
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icpu.step();
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// TODO: call icpu.panic()
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}
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test "create ARMv5TE interface" {
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var bus_impl = ExampleBus{};
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var scheduler_impl = ExampleScheduler{};
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var cop_impl = ExampleCoprocessor{};
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const bus_interface = Bus.init(&bus_impl);
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const scheduler_interface = Scheduler.init(&scheduler_impl);
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const coprocessor_interface = Coprocessor.init(&cop_impl);
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var arm946es = Arm946es.init(scheduler_interface, bus_interface, coprocessor_interface);
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var icpu = arm946es.interface();
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icpu.reset();
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icpu.step();
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// TODO: call icpu.panic();
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}
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pub const Bus = struct {
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ptr: *anyopaque,
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vtable: *const Vtable,
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@ -196,6 +228,118 @@ pub const Bus = struct {
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}
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};
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test "create Bus" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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_ = iface;
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}
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test "call Bus reads" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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_ = iface.read(u32, 0x0000_0000);
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_ = iface.read(u16, 0x0000_0000);
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_ = iface.read(u8, 0x0000_0000);
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_ = iface.dbgRead(u32, 0x0000_0000);
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_ = iface.dbgRead(u16, 0x0000_0000);
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_ = iface.dbgRead(u8, 0x0000_0000);
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}
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test "call Bus writes" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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_ = iface.write(u32, 0x0000_0000, 0x0000_0000);
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_ = iface.write(u16, 0x0000_0000, 0x0000);
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_ = iface.write(u8, 0x0000_0000, 0x00);
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_ = iface.dbgWrite(u32, 0x0000_0000, 0x0000_0000);
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_ = iface.dbgWrite(u16, 0x0000_0000, 0x0000);
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_ = iface.dbgWrite(u8, 0x0000_0000, 0x00);
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}
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pub const Coprocessor = struct {
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ptr: *anyopaque,
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// VTable
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readFn: *const fn (ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3) u32,
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writeFn: *const fn (ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void,
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resetFn: *const fn (ptr: *anyopaque) void,
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pub fn init(obj: anytype) @This() {
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const P = @TypeOf(obj);
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const info = @typeInfo(P);
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std.debug.assert(info == .Pointer); // `anytype` is a Pointer
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std.debug.assert(info.Pointer.size == .One); // Single-Item Pointer
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std.debug.assert(@typeInfo(info.Pointer.child) == .Struct); // Pointer Child is a `struct`
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const impl = struct {
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fn read(ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3) u32 {
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const self: P = @ptrCast(@alignCast(ptr));
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return self.read(op1, cn, cm, op2);
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}
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fn write(ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
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const self: P = @ptrCast(@alignCast(ptr));
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return self.write(op1, cn, cm, op2, value);
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}
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fn reset(ptr: *anyopaque) void {
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const self: P = @ptrCast(@alignCast(ptr));
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return self.reset();
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}
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};
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return .{
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.ptr = obj,
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.readFn = impl.read,
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.writeFn = impl.write,
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.resetFn = impl.reset,
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};
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}
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pub fn read(self: @This(), op1: u3, cn: u4, cm: u4, op2: u3) u32 {
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return self.readFn(self.ptr, op1, cn, cm, op2);
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}
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pub fn write(self: @This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
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return self.writeFn(self.ptr, op1, cn, cm, op2, value);
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}
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pub fn reset(self: @This()) void {
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return self.resetFn(self.ptr);
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}
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};
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test "create Coprocessor" {
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var cop_impl = ExampleCoprocessor{};
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_ = Coprocessor.init(&cop_impl);
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}
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test "Coprocessor.read" {
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var cop_impl = ExampleCoprocessor{};
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const iface = Coprocessor.init(&cop_impl);
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try testing.expectEqual(@as(u32, 0xDEADBEEF), iface.read(0, 0, 0, 0));
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}
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test "Coprocessor.write" {
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var cop_impl = ExampleCoprocessor{};
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const iface = Coprocessor.init(&cop_impl);
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iface.write(0, 0, 0, 0, 0xDEADBEEF);
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}
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test "Coprocessor.reset" {
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var cop_impl = ExampleCoprocessor{};
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const iface = Coprocessor.init(&cop_impl);
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iface.reset();
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}
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pub const Scheduler = struct {
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ptr: *anyopaque,
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@ -235,6 +379,27 @@ pub const Scheduler = struct {
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}
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};
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test "create Scheduler" {
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var scheduler_impl = ExampleScheduler{};
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const iface = Scheduler.init(&scheduler_impl);
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_ = iface;
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}
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test "Scheduler.now()" {
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var scheduler_impl = ExampleScheduler{};
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const iface = Scheduler.init(&scheduler_impl);
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try testing.expectEqual(@as(u64, 0), iface.now());
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}
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test "Scheduler.reset()" {
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var scheduler_impl = ExampleScheduler{ .tick = std.math.maxInt(u64) };
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const iface = Scheduler.init(&scheduler_impl);
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iface.reset();
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try testing.expectEqual(@as(u64, 0), scheduler_impl.tick);
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}
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// ---
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// TESTING
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// ---
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@ -282,61 +447,27 @@ const ExampleScheduler = struct {
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}
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};
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test "create IBus" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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_ = iface;
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}
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const ExampleCoprocessor = struct {
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pub fn read(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3) u32 {
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_ = op2;
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_ = cm;
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_ = cn;
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_ = op1;
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_ = self;
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test "call IBus reads" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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return 0xDEADBEEF;
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}
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_ = iface.read(u32, 0x0000_0000);
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_ = iface.read(u16, 0x0000_0000);
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_ = iface.read(u8, 0x0000_0000);
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pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
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_ = value;
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_ = op2;
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_ = cm;
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_ = cn;
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_ = op1;
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_ = self;
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}
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_ = iface.dbgRead(u32, 0x0000_0000);
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_ = iface.dbgRead(u16, 0x0000_0000);
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_ = iface.dbgRead(u8, 0x0000_0000);
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}
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test "call IBus writes" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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_ = iface.write(u32, 0x0000_0000, 0x0000_0000);
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_ = iface.write(u16, 0x0000_0000, 0x0000);
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_ = iface.write(u8, 0x0000_0000, 0x00);
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_ = iface.dbgWrite(u32, 0x0000_0000, 0x0000_0000);
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_ = iface.dbgWrite(u16, 0x0000_0000, 0x0000);
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_ = iface.dbgWrite(u8, 0x0000_0000, 0x00);
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}
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test "create ARMv4T interface" {
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var bus_impl = ExampleBus{};
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var scheduler_impl = ExampleScheduler{};
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const bus_interface = Bus.init(&bus_impl);
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const scheduler_interface = Scheduler.init(&scheduler_impl);
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var arm7tdmi = Arm7tdmi.init(scheduler_interface, bus_interface);
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var icpu = arm7tdmi.interface();
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icpu.reset();
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icpu.step();
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// TODO: call icpu.panic()
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}
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test "create ARMv5TE interface" {
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var bus_impl = ExampleBus{};
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var scheduler_impl = ExampleScheduler{};
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const bus_interface = Bus.init(&bus_impl);
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const scheduler_interface = Scheduler.init(&scheduler_impl);
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var arm946es = Arm946es.init(scheduler_interface, bus_interface);
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_ = arm946es.interface();
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}
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pub fn reset(self: *@This()) void {
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self.* = .{};
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}
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};
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