feat: implement debug i/o in Bus Interface
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parent
3c8a87c14d
commit
90d5c19e01
109
src/lib.zig
109
src/lib.zig
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@ -45,6 +45,14 @@ pub const Bus = struct {
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write16: *const fn (ptr: *anyopaque, address: u32, value: u16) void,
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write32: *const fn (ptr: *anyopaque, address: u32, value: u32) void,
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dbg_read8: *const fn (ptr: *anyopaque, address: u32) u8,
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dbg_read16: *const fn (ptr: *anyopaque, address: u32) u16,
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dbg_read32: *const fn (ptr: *anyopaque, address: u32) u32,
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dbg_write8: *const fn (ptr: *anyopaque, address: u32, value: u8) void,
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dbg_write16: *const fn (ptr: *anyopaque, address: u32, value: u16) void,
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dbg_write32: *const fn (ptr: *anyopaque, address: u32, value: u32) void,
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reset: *const fn (ptr: *anyopaque) void,
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};
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@ -89,6 +97,36 @@ pub const Bus = struct {
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self.write(u32, address, value);
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}
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fn dbgRead8(ptr: *anyopaque, address: u32) u8 {
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const self = @ptrCast(P, @alignCast(alignment, ptr));
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return self.dbgRead(u8, address);
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}
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fn dbgRead16(ptr: *anyopaque, address: u32) u16 {
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const self = @ptrCast(P, @alignCast(alignment, ptr));
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return self.dbgRead(u16, address);
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}
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fn dbgRead32(ptr: *anyopaque, address: u32) u32 {
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const self = @ptrCast(P, @alignCast(alignment, ptr));
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return self.dbgRead(u32, address);
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}
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fn dbgWrite8(ptr: *anyopaque, address: u32, value: u8) void {
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const self = @ptrCast(P, @alignCast(alignment, ptr));
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self.dbgWrite(u8, address, value);
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}
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fn dbgWrite16(ptr: *anyopaque, address: u32, value: u16) void {
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const self = @ptrCast(P, @alignCast(alignment, ptr));
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self.dbgWrite(u16, address, value);
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}
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fn dbgWrite32(ptr: *anyopaque, address: u32, value: u32) void {
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const self = @ptrCast(P, @alignCast(alignment, ptr));
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self.dbgWrite(u32, address, value);
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}
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fn reset(ptr: *anyopaque) void {
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const self = @ptrCast(P, @alignCast(alignment, ptr));
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self.reset();
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@ -106,6 +144,14 @@ pub const Bus = struct {
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.write16 = impl.write16,
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.write32 = impl.write32,
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.dbg_read8 = impl.dbgRead8,
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.dbg_read16 = impl.dbgRead16,
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.dbg_read32 = impl.dbgRead32,
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.dbg_write8 = impl.dbgWrite8,
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.dbg_write16 = impl.dbgWrite16,
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.dbg_write32 = impl.dbgWrite32,
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.reset = impl.reset,
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},
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};
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@ -130,16 +176,21 @@ pub const Bus = struct {
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}
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pub fn dbgRead(self: @This(), comptime T: type, address: u32) T {
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_ = address;
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_ = self;
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@panic("TODO: Implement Debug Reads via Bus Interface");
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return switch (T) {
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u32 => self.vtable.dbg_read32(self.ptr, address),
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u16 => self.vtable.dbg_read16(self.ptr, address),
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u8 => self.vtable.dbg_read8(self.ptr, address),
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else => @compileError("TODO: Fill this in"),
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};
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}
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pub fn dbgWrite(self: @This(), comptime T: type, address: u32, value: T) void {
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_ = self;
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_ = value;
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_ = address;
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@panic("TODO: Implement Debug Writes via Bus Interface");
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switch (T) {
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u32 => self.vtable.dbg_write32(self.ptr, address, value),
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u16 => self.vtable.dbg_write16(self.ptr, address, value),
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u8 => self.vtable.dbg_write8(self.ptr, address, value),
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else => @compileError("TODO: Fill this in"),
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}
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}
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pub fn reset(self: @This()) void {
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@ -206,6 +257,17 @@ const ExampleBus = struct {
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_ = value;
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_ = address;
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}
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pub fn dbgRead(self: *@This(), comptime T: type, address: u32) T {
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_ = self;
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_ = address;
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return 0;
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}
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pub fn dbgWrite(self: *@This(), comptime T: type, address: u32, value: T) void {
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_ = self;
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_ = value;
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_ = address;
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}
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pub fn reset(self: *@This()) void {
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self._ = 0;
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@ -224,6 +286,38 @@ const ExampleScheduler = struct {
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}
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};
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test "create IBus" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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_ = iface;
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}
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test "call IBus reads" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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_ = iface.read(u32, 0x0000_0000);
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_ = iface.read(u16, 0x0000_0000);
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_ = iface.read(u8, 0x0000_0000);
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_ = iface.dbgRead(u32, 0x0000_0000);
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_ = iface.dbgRead(u16, 0x0000_0000);
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_ = iface.dbgRead(u8, 0x0000_0000);
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}
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test "call IBus writes" {
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var bus_impl = ExampleBus{};
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const iface = Bus.init(&bus_impl);
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_ = iface.write(u32, 0x0000_0000, 0x0000_0000);
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_ = iface.write(u16, 0x0000_0000, 0x0000);
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_ = iface.write(u8, 0x0000_0000, 0x00);
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_ = iface.dbgWrite(u32, 0x0000_0000, 0x0000_0000);
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_ = iface.dbgWrite(u16, 0x0000_0000, 0x0000);
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_ = iface.dbgWrite(u8, 0x0000_0000, 0x00);
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}
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test "create ARMv4T interface" {
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var bus_impl = ExampleBus{};
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var scheduler_impl = ExampleScheduler{};
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@ -242,6 +336,7 @@ test "create ARMv4T interface" {
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icpu.reset();
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icpu.step();
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// TODO: call icpu.panic()
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}
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test "create ARMv5TE interface" {
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