feat: pass nds arm7wrestler
- impl behaviour of running v5te instrs on v4t cpu - impl undefined instruction exception handler - panic on what I think are still unimplemented v5te opcodes
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23
src/arm.zig
23
src/arm.zig
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@ -409,6 +409,29 @@ pub fn Arm32(comptime isa: Architecture) type {
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std.debug.panic(format, args);
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}
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// TODO: Rename
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pub fn undefinedInstructionTrap(self: *Self) void {
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// Copy Values from Current Mode
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const ret_addr = self.r[15] - @as(u32, if (self.cpsr.t.read()) 2 else 4);
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const cpsr = self.cpsr.raw;
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// Switch Mode
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self.changeMode(.Undefined);
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self.cpsr.t.write(false); // Force ARM Mode
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self.cpsr.i.write(true); // Disable normal interrupts
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self.r[14] = ret_addr; // Resume Execution
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self.spsr.raw = cpsr; // Previous mode CPSR
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self.r[15] = switch (Self.arch) {
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.v4t => 0x0000_0004,
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.v5te => blk: {
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const ctrl = self.cp15.read(0, 1, 0, 0);
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break :blk if (ctrl >> 13 & 1 == 1) 0xFFFF_0004 else 0x0000_0004;
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},
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};
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self.pipe.reload(self);
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}
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pub fn interface(self: *Self) Interpreter {
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return switch (isa) {
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.v4t => .{ .v4t = self },
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@ -51,14 +51,13 @@ pub fn dataTransfer(
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// TODO: Increment address + 4 (and perform op) until coprocessor says stop
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if (L) {
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log.debug("TODO: ldc{s} p{}, c{}, 0x{X:0>8}", .{ [_]u8{if (N) 'l' else ' '}, cp_num, crd, start_address });
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cpu.panic("TODO: ldc{s} p{}, c{}, 0x{X:0>8}", .{ [_]u8{if (N) 'l' else ' '}, cp_num, crd, start_address });
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} else {
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log.debug("TODO: stc{s} p{}, c{}, 0x{X:0>8}", .{ [_]u8{if (N) 'l' else ' '}, cp_num, crd, start_address });
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cpu.panic("TODO: stc{s} p{}, c{}, 0x{X:0>8}", .{ [_]u8{if (N) 'l' else ' '}, cp_num, crd, start_address });
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}
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}
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fn copExt(cpu: *Arm32, opcode: u32) void {
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_ = cpu;
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const cp_num = opcode >> 8 & 0xF;
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const rd = opcode >> 12 & 0xF;
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const rn = opcode >> 16 & 0xF;
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@ -71,10 +70,10 @@ pub fn dataTransfer(
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if (L) {
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// MRRC
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log.debug("TODO: mrrc p{}, {}, r{}, r{}, c{}", .{ cp_num, cp_opcode, rd, rn, crm });
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cpu.panic("TODO: mrrc p{}, {}, r{}, r{}, c{}", .{ cp_num, cp_opcode, rd, rn, crm });
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} else {
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// MCRR
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log.debug("TODO: mcrr p{}, {}, r{}, r{}, c{}", .{ cp_num, cp_opcode, rd, rn, crm });
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cpu.panic("TODO: mcrr p{}, {}, r{}, r{}, c{}", .{ cp_num, cp_opcode, rd, rn, crm });
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}
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}
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}.inner;
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@ -90,7 +89,11 @@ pub fn registerTransfer(comptime InstrFn: type, comptime opcode1: u3, comptime L
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const cp_num = opcode >> 8 & 0xF;
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const crm: u4 = @intCast(opcode & 0xF);
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std.debug.assert(cp_num == 0xF); // There's no other coprocessor on NDS9;
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switch (cp_num) {
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14 => return,
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15 => if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap(),
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else => cpu.panic("MRC: unexpected coprocessor #: {}", .{cp_num}),
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}
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if (L) {
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// MRC
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@ -148,9 +151,7 @@ pub fn dataProcessing(comptime InstrFn: type, comptime opcode1: u4, comptime opc
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return struct {
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fn inner(cpu: *Arm32, opcode: u32) void {
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_ = cpu;
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log.err("TODO: handle 0x{X:0>8} which is a coprocessor data processing instr", .{opcode});
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cpu.panic("TODO: handle 0x{X:0>8} which is a coprocessor data processing instr", .{opcode});
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}
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}.inner;
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}
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@ -1,6 +1,9 @@
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const std = @import("std");
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const sext = @import("zba-util").sext;
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const rotr = @import("zba-util").rotr;
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const log = std.log.scoped(.half_and_signed_data_transfer);
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pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
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const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
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@ -66,9 +69,9 @@ pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, compt
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// FIXME: I shouldn't have to use @as(u16, ...) here
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cpu.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
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},
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0b10 => {
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0b10 => blk: {
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// LDRD
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if (Arm32.arch != .v5te) cpu.panic("LDRD: unsupported on arm{s}", .{@tagName(Arm32.arch)});
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if (Arm32.arch == .v4t) break :blk;
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if (rd & 0 != 0) cpu.panic("LDRD: UNDEFINED behaviour when Rd is not even", .{});
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if (rd == 0xE) cpu.panic("LDRD: UNPREDICTABLE behaviour when rd == 14", .{});
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if (address & 0x7 != 0b000) cpu.panic("LDRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
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@ -30,6 +30,7 @@ pub fn control(comptime InstrFn: type, comptime I: bool, comptime op: u6) InstrF
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},
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0b01_0001 => cpu.panic("TODO: implement v5TE BX", .{}),
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0b11_0001 => { // CLZ
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if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap();
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const rd = opcode >> 12 & 0xF;
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const rm = opcode & 0xF;
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@ -50,6 +51,7 @@ pub fn control(comptime InstrFn: type, comptime I: bool, comptime op: u6) InstrF
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cpu.pipe.reload(cpu);
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},
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0b00_0101, 0b01_0101, 0b10_0101, 0b11_0101 => { // QADD / QDADD / QSUB / QDSUB
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if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap();
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const U = op >> 4 & 1 == 1;
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const D = op >> 5 & 1 == 1;
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@ -84,6 +86,7 @@ pub fn control(comptime InstrFn: type, comptime I: bool, comptime op: u6) InstrF
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},
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0b01_0111 => cpu.panic("TODO: handle BKPT", .{}),
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0b00_1000, 0b00_1010, 0b00_1100, 0b00_1110 => { // SMLA<x><y>
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if (Arm32.arch == .v4t) return; // no-op
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const X = op >> 1 & 1;
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const Y = op >> 2 & 1;
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@ -20,6 +20,8 @@ pub const arm = struct {
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/// Arithmetic Instruction Extension Space
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const multiplyExt = @import("cpu/arm/multiply.zig").multiply;
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const cop = @import("cpu/arm/coprocessor.zig");
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/// Determine index into ARM InstrFn LUT
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pub fn idx(opcode: u32) u12 {
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// FIXME: omit these?
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@ -87,8 +89,29 @@ pub const arm = struct {
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const L = i >> 8 & 1 == 1;
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break :blk branch(InstrFn, L);
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},
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0b10 => und, // COP Data Transfer
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0b11 => if (i >> 8 & 1 == 1) swi(InstrFn) else und, // COP Data Operation + Register Transfer
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0b10 => blk: {
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const N = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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break :blk cop.dataTransfer(InstrFn, P, U, N, W, L);
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},
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0b11 => blk: {
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if (i >> 8 & 1 == 1) break :blk swi(InstrFn);
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const data_opcode1 = i >> 4 & 0xF; // bits 20 -> 23
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const reg_opcode1 = i >> 5 & 0x7; // bits 21 -> 23
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const opcode2 = i >> 1 & 0x7; // bits 5 -> 7
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const L = i >> 4 & 1 == 1; // bit 20
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// Bit 4 (index pos of 0) distinguishes between these classes of instructions
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break :blk switch (i & 1 == 1) {
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true => cop.registerTransfer(InstrFn, reg_opcode1, L, opcode2),
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false => cop.dataProcessing(InstrFn, data_opcode1, opcode2),
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};
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},
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},
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};
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}
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