ci: ensure that submodules are updated recursively

Reviewed-on: #6

.github/workflows/main.yml

@@ -14,7 +14,8 @@ jobs:
   build:
     strategy:
       matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
+        # os: [ubuntu-latest, windows-latest, macos-latest]
+        os: [ubuntu-latest, windows-latest]
     runs-on: ${{matrix.os}}
     steps:
       - uses: goto-bus-stop/setup-zig@v2
@@ -37,9 +38,9 @@ jobs:
             brew install sdl2
       - uses: actions/checkout@v3
         with:
-          submodules: true
+          submodules: recursive
       - name: build 
-        run: zig build -Drelease-safe
+        run: zig build -Doptimize=ReleaseSafe -Dcpu=baseline
       - name: upload
         uses: actions/upload-artifact@v3
         with:
@@ -50,7 +51,7 @@ jobs:
     steps: 
       - uses: actions/checkout@v3
         with:
-          submodules: true
+          submodules: recursive
       - uses: goto-bus-stop/setup-zig@v2
         with:
           version: master

.gitmodules

@@ -13,3 +13,6 @@
 [submodule "lib/zig-toml"]
 	path = lib/zig-toml
 	url = https://github.com/aeronavery/zig-toml
+[submodule "lib/zba-gdbstub"]
+	path = lib/zba-gdbstub
+	url = https://git.musuka.dev/paoda/zba-gdbstub

.vscode/extensions.json

@@ -1,8 +0,0 @@
-{
-    "recommendations": [
-        "augusterame.zls-vscode",
-        "usernamehw.errorlens",
-        "vadimcn.vscode-lldb",
-        "dan-c-underwood.arm"
-    ]
-}

README.md

@@ -10,10 +10,10 @@ This is a simple (read: incomplete) for-fun long-term project. I hope to get "mo
 
 ### TODO
 
-- [ ] Affine Sprites
+- [x] Affine Sprites
 - [ ] Windowing (see [this branch](https://git.musuka.dev/paoda/zba/src/branch/window))
 - [ ] Audio Resampler (Having issues with SDL2's)
-- [ ] Immediate Mode GUI
+- [x] Immediate Mode GUI (see [this branch](https://git.musuka.dev/paoda/zba/src/branch/imgui))
 - [ ] Refactoring for easy-ish perf boosts
 
 ## Usage
@@ -77,7 +77,7 @@ arm7wrestler GBA Fixed | [destoer](https://github.com/destoer)
 
 ## Compiling
 
-Most recently built on Zig [0.11.0-dev.368+1829b6eab](https://github.com/ziglang/zig/tree/1829b6eab)
+Most recently built on Zig [v0.11.0-dev.1580+a5b34a61a](https://github.com/ziglang/zig/tree/a5b34a61a)
 
 ### Dependencies
 
@@ -91,17 +91,17 @@ zig-datetime | <https://github.com/frmdstryr/zig-datetime>
 `bitfields.zig` | [https://github.com/FlorenceOS/Florence](https://github.com/FlorenceOS/Florence/blob/aaa5a9e568/lib/util/bitfields.zig)
 `gl.zig` | <https://github.com/MasterQ32/zig-opengl>
 
-Use `git submodule update --init` from the project root to pull the git submodules `SDL.zig`, `zig-clap`, `known-folders`, `zig-toml` and `zig-datetime`
+Use `git submodule update --init` from the project root to pull the git relevant git submodules
 
 Be sure to provide SDL2 using:
 
 - Linux: Your distro's package manager
-- MacOS: ¯\\\_(ツ)_/¯
+- macOS: ¯\\\_(ツ)_/¯ (try [this formula](https://formulae.brew.sh/formula/sdl2)?)
 - Windows: [`vcpkg`](https://github.com/Microsoft/vcpkg) (install `sdl2:x64-windows`)
 
 `SDL.zig` will provide a helpful compile error if the zig compiler is unable to find SDL2.
 
-Once you've got all the dependencies, execute `zig build -Drelease-fast`. The executable is located at `zig-out/bin/`.
+Once you've got all the dependencies, execute `zig build -Doptimize=ReleaseSafe`. The executable is located at `zig-out/bin/`.
 
 ## Controls
 

build.zig

@@ -1,54 +1,55 @@
 const std = @import("std");
 const builtin = @import("builtin");
+
 const Sdk = @import("lib/SDL.zig/Sdk.zig");
+const Gdbstub = @import("lib/zba-gdbstub/build.zig");
 
 pub fn build(b: *std.build.Builder) void {
     // Minimum Zig Version
-    const min_ver = std.SemanticVersion.parse("0.11.0-dev.323+30eb2a175") catch return; // https://github.com/ziglang/zig/commit/30eb2a175
+    const min_ver = std.SemanticVersion.parse("0.11.0-dev.1580+a5b34a61a") catch return; // https://github.com/ziglang/zig/commit/a5b34a61a
     if (builtin.zig_version.order(min_ver).compare(.lt)) {
         std.log.err("{s}", .{b.fmt("Zig v{} does not meet the minimum version requirement. (Zig v{})", .{ builtin.zig_version, min_ver })});
         std.os.exit(1);
     }
 
-    // Standard target options allows the person running `zig build` to choose
-    // what target to build for. Here we do not override the defaults, which
-    // means any target is allowed, and the default is native. Other options
-    // for restricting supported target set are available.
     const target = b.standardTargetOptions(.{});
+    const optimize = b.standardOptimizeOption(.{});
 
-    // Standard release options allow the person running `zig build` to select
+    const exe = b.addExecutable(.{
-    // between Debug, ReleaseSafe, ReleaseFast, and ReleaseSmall.
+        .name = "zba",
-    const mode = b.standardReleaseOptions();
+        .root_source_file = .{ .path = "src/main.zig" },
+        .target = target,
+        .optimize = optimize,
+    });
 
-    const exe = b.addExecutable("zba", "src/main.zig");
     exe.setMainPkgPath("."); // Necessary so that src/main.zig can embed example.toml
-    exe.setTarget(target);
 
     // Known Folders (%APPDATA%, XDG, etc.)
-    exe.addPackagePath("known_folders", "lib/known-folders/known-folders.zig");
+    exe.addAnonymousModule("known_folders", .{ .source_file = .{ .path = "lib/known-folders/known-folders.zig" } });
 
     // DateTime Library
-    exe.addPackagePath("datetime", "lib/zig-datetime/src/main.zig");
+    exe.addAnonymousModule("datetime", .{ .source_file = .{ .path = "lib/zig-datetime/src/main.zig" } });
 
     // Bitfield type from FlorenceOS: https://github.com/FlorenceOS/
-    // exe.addPackage(.{ .name = "bitfield", .path = .{ .path = "lib/util/bitfield.zig" } });
+    exe.addAnonymousModule("bitfield", .{ .source_file = .{ .path = "lib/util/bitfield.zig" } });
-    exe.addPackagePath("bitfield", "lib/util/bitfield.zig");
 
     // Argument Parsing Library
-    exe.addPackagePath("clap", "lib/zig-clap/clap.zig");
+    exe.addAnonymousModule("clap", .{ .source_file = .{ .path = "lib/zig-clap/clap.zig" } });
 
     // TOML Library
-    exe.addPackagePath("toml", "lib/zig-toml/src/toml.zig");
+    exe.addAnonymousModule("toml", .{ .source_file = .{ .path = "lib/zig-toml/src/toml.zig" } });
 
     // OpenGL 3.3 Bindings
-    exe.addPackagePath("gl", "lib/gl.zig");
+    exe.addAnonymousModule("gl", .{ .source_file = .{ .path = "lib/gl.zig" } });
+
+    // gdbstub
+    Gdbstub.link(exe);
 
     // Zig SDL Bindings: https://github.com/MasterQ32/SDL.zig
-    const sdk = Sdk.init(b);
+    const sdk = Sdk.init(b, null);
     sdk.link(exe, .dynamic);
-    exe.addPackage(sdk.getNativePackage("sdl2"));
+    exe.addModule("sdl2", sdk.getNativeModule());
 
-    exe.setBuildMode(mode);
     exe.install();
 
     const run_cmd = exe.run();
@@ -60,9 +61,11 @@ pub fn build(b: *std.build.Builder) void {
     const run_step = b.step("run", "Run the app");
     run_step.dependOn(&run_cmd.step);
 
-    const exe_tests = b.addTest("src/main.zig");
+    const exe_tests = b.addTest(.{
-    exe_tests.setTarget(target);
+        .root_source_file = .{ .path = "src/main.zig" },
-    exe_tests.setBuildMode(mode);
+        .target = target,
+        .optimize = optimize,
+    });
 
     const test_step = b.step("test", "Run unit tests");
     test_step.dependOn(&exe_tests.step);

src/core/Bus.zig

@@ -60,9 +60,8 @@ allocator: Allocator,
 pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
     const tables = try allocator.alloc(?*anyopaque, 3 * table_len); // Allocate all tables
 
-    const read_table: *[table_len]?*const anyopaque = tables[0..table_len];
+    const read_table = tables[0..table_len];
-    const left_write: *[table_len]?*anyopaque = tables[table_len .. 2 * table_len];
+    const write_tables = .{ tables[table_len .. 2 * table_len], tables[2 * table_len .. 3 * table_len] };
-    const right_write: *[table_len]?*anyopaque = tables[2 * table_len .. 3 * table_len];
 
     self.* = .{
         .pak = try GamePak.init(allocator, cpu, paths.rom, paths.save),
@@ -78,18 +77,15 @@ pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi
         .sched = sched,
 
         .read_table = read_table,
-        .write_tables = .{ left_write, right_write },
+        .write_tables = write_tables,
         .allocator = allocator,
     };
 
-    // read_table, write_tables, and *Self are not restricted to the lifetime
+    self.fillReadTable(read_table);
-    // of this init function so we can initialize our tables here
-    fillReadTable(self, read_table);
 
-    // Internal Display Memory behavious unusually on 8-bit reads
+    // Internal Display Memory behaves differently on 8-bit reads
-    // so we have two different tables depending on whether there's an 8-bit read or not
+    self.fillWriteTable(u32, write_tables[0]);
-    fillWriteTable(u32, self, left_write);
+    self.fillWriteTable(u8, write_tables[1]);
-    fillWriteTable(u8, self, right_write);
 }
 
 pub fn deinit(self: *Self) void {
@@ -106,50 +102,50 @@ pub fn deinit(self: *Self) void {
     self.* = undefined;
 }
 
-fn fillReadTable(bus: *Self, table: *[table_len]?*const anyopaque) void {
+fn fillReadTable(self: *Self, table: *[table_len]?*const anyopaque) void {
-    const vramMirror = @import("ppu.zig").Vram.mirror;
+    const vramMirror = @import("ppu/Vram.zig").mirror;
 
-    for (table) |*ptr, i| {
+    for (table, 0..) |*ptr, i| {
-        const addr = page_size * i;
+        const addr = @intCast(u32, page_size * i);
 
         ptr.* = switch (addr) {
             // General Internal Memory
             0x0000_0000...0x0000_3FFF => null, // BIOS has it's own checks
-            0x0200_0000...0x02FF_FFFF => &bus.ewram.buf[addr & 0x3FFFF],
+            0x0200_0000...0x02FF_FFFF => &self.ewram.buf[addr & 0x3FFFF],
-            0x0300_0000...0x03FF_FFFF => &bus.iwram.buf[addr & 0x7FFF],
+            0x0300_0000...0x03FF_FFFF => &self.iwram.buf[addr & 0x7FFF],
             0x0400_0000...0x0400_03FF => null, // I/O
 
             // Internal Display Memory
-            0x0500_0000...0x05FF_FFFF => &bus.ppu.palette.buf[addr & 0x3FF],
+            0x0500_0000...0x05FF_FFFF => &self.ppu.palette.buf[addr & 0x3FF],
-            0x0600_0000...0x06FF_FFFF => &bus.ppu.vram.buf[vramMirror(addr)],
+            0x0600_0000...0x06FF_FFFF => &self.ppu.vram.buf[vramMirror(addr)],
-            0x0700_0000...0x07FF_FFFF => &bus.ppu.oam.buf[addr & 0x3FF],
+            0x0700_0000...0x07FF_FFFF => &self.ppu.oam.buf[addr & 0x3FF],
 
             // External Memory (Game Pak)
-            0x0800_0000...0x0DFF_FFFF => fillTableExternalMemory(bus, addr),
+            0x0800_0000...0x0DFF_FFFF => self.fillReadTableExternal(addr),
             0x0E00_0000...0x0FFF_FFFF => null, // SRAM
             else => null,
         };
     }
 }
 
-fn fillWriteTable(comptime T: type, bus: *Self, table: *[table_len]?*const anyopaque) void {
+fn fillWriteTable(self: *Self, comptime T: type, table: *[table_len]?*const anyopaque) void {
     comptime std.debug.assert(T == u32 or T == u16 or T == u8);
-    const vramMirror = @import("ppu.zig").Vram.mirror;
+    const vramMirror = @import("ppu/Vram.zig").mirror;
 
-    for (table) |*ptr, i| {
+    for (table, 0..) |*ptr, i| {
-        const addr = page_size * i;
+        const addr = @intCast(u32, page_size * i);
 
         ptr.* = switch (addr) {
             // General Internal Memory
             0x0000_0000...0x0000_3FFF => null, // BIOS has it's own checks
-            0x0200_0000...0x02FF_FFFF => &bus.ewram.buf[addr & 0x3FFFF],
+            0x0200_0000...0x02FF_FFFF => &self.ewram.buf[addr & 0x3FFFF],
-            0x0300_0000...0x03FF_FFFF => &bus.iwram.buf[addr & 0x7FFF],
+            0x0300_0000...0x03FF_FFFF => &self.iwram.buf[addr & 0x7FFF],
             0x0400_0000...0x0400_03FF => null, // I/O
 
             // Internal Display Memory
-            0x0500_0000...0x05FF_FFFF => if (T != u8) &bus.ppu.palette.buf[addr & 0x3FF] else null,
+            0x0500_0000...0x05FF_FFFF => if (T != u8) &self.ppu.palette.buf[addr & 0x3FF] else null,
-            0x0600_0000...0x06FF_FFFF => if (T != u8) &bus.ppu.vram.buf[vramMirror(addr)] else null,
+            0x0600_0000...0x06FF_FFFF => if (T != u8) &self.ppu.vram.buf[vramMirror(addr)] else null,
-            0x0700_0000...0x07FF_FFFF => if (T != u8) &bus.ppu.oam.buf[addr & 0x3FF] else null,
+            0x0700_0000...0x07FF_FFFF => if (T != u8) &self.ppu.oam.buf[addr & 0x3FF] else null,
 
             // External Memory (Game Pak)
             0x0800_0000...0x0DFF_FFFF => null, // ROM
@@ -159,24 +155,29 @@ fn fillWriteTable(comptime T: type, bus: *Self, table: *[table_len]?*const anyop
     }
 }
 
-fn fillTableExternalMemory(bus: *Self, addr: usize) ?*anyopaque {
+fn fillReadTableExternal(self: *Self, addr: u32) ?*anyopaque {
     // see `GamePak.zig` for more information about what conditions need to be true
     // so that a simple pointer dereference isn't possible
 
+    std.debug.assert(addr & @as(u32, page_size - 1) == 0); // addr is guaranteed to be page-aligned
+
     const start_addr = addr;
-    const end_addr = addr + page_size;
+    const end_addr = start_addr + page_size;
 
-    const gpio_data = start_addr <= 0x0800_00C4 and 0x0800_00C4 < end_addr;
+    {
-    const gpio_direction = start_addr <= 0x0800_00C6 and 0x0800_00C6 < end_addr;
+        const data = start_addr <= 0x0800_00C4 and 0x0800_00C4 < end_addr; // GPIO Data
-    const gpio_control = start_addr <= 0x0800_00C8 and 0x0800_00C8 < end_addr;
+        const direction = start_addr <= 0x0800_00C6 and 0x0800_00C6 < end_addr; // GPIO Direction
+        const control = start_addr <= 0x0800_00C8 and 0x0800_00C8 < end_addr; // GPIO Control
 
-    if (bus.pak.gpio.device.kind != .None and (gpio_data or gpio_direction or gpio_control)) {
+        const has_gpio = data or direction or control;
-        // We found a GPIO device, and this page a GPIO register. We want to handle this in slowmem
+        const gpio_kind = self.pak.gpio.device.kind;
-        return null;
+
+        // There is a GPIO Device, and the current page contains at least one memory-mapped GPIO register
+        if (gpio_kind != .None and has_gpio) return null;
     }
 
-    if (bus.pak.backup.kind == .Eeprom) {
+    if (self.pak.backup.kind == .Eeprom) {
-        if (bus.pak.buf.len > 0x100_000) {
+        if (self.pak.buf.len > 0x100_000) {
             // We are using a "large" EEPROM which means that if the below check is true
             // this page has an address that's reserved for the EEPROM and therefore must
             // be handled in slowmem
@@ -192,49 +193,9 @@ fn fillTableExternalMemory(bus: *Self, addr: usize) ?*anyopaque {
     // Finally, the GamePak has some unique behaviour for reads past the end of the ROM,
     // so those will be handled by slowmem as well
     const masked_addr = addr & 0x1FF_FFFF;
-    if (masked_addr >= bus.pak.buf.len) return null;
+    if (masked_addr >= self.pak.buf.len) return null;
 
-    return &bus.pak.buf[masked_addr];
+    return &self.pak.buf[masked_addr];
-}
-
-// TODO: Take advantage of fastmem here too?
-pub fn dbgRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
-    const page = @truncate(u8, unaligned_address >> 24);
-    const address = forceAlign(T, unaligned_address);
-
-    return switch (page) {
-        // General Internal Memory
-        0x00 => blk: {
-            if (address < Bios.size)
-                break :blk self.bios.dbgRead(T, self.cpu.r[15], address);
-
-            break :blk self.openBus(T, address);
-        },
-        0x02 => self.ewram.read(T, address),
-        0x03 => self.iwram.read(T, address),
-        0x04 => self.readIo(T, address),
-
-        // Internal Display Memory
-        0x05 => self.ppu.palette.read(T, address),
-        0x06 => self.ppu.vram.read(T, address),
-        0x07 => self.ppu.oam.read(T, address),
-
-        // External Memory (Game Pak)
-        0x08...0x0D => self.pak.dbgRead(T, address),
-        0x0E...0x0F => blk: {
-            const value = self.pak.backup.read(unaligned_address);
-
-            const multiplier = switch (T) {
-                u32 => 0x01010101,
-                u16 => 0x0101,
-                u8 => 1,
-                else => @compileError("Backup: Unsupported read width"),
-            };
-
-            break :blk @as(T, value) * multiplier;
-        },
-        else => self.openBus(T, address),
-    };
 }
 
 fn readIo(self: *const Self, comptime T: type, address: u32) T {
@@ -316,8 +277,7 @@ pub fn read(self: *Self, comptime T: type, unaligned_address: u32) T {
     if (self.read_table[page]) |some_ptr| {
         // We have a pointer to a page, cast the pointer to it's underlying type
         const Ptr = [*]const T;
-        const alignment = @alignOf(std.meta.Child(Ptr));
+        const ptr = @ptrCast(Ptr, @alignCast(@alignOf(std.meta.Child(Ptr)), some_ptr));
-        const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
 
         // Note: We don't check array length, since we force align the
         // lower bits of the address as the GBA would
@@ -327,6 +287,27 @@ pub fn read(self: *Self, comptime T: type, unaligned_address: u32) T {
     return self.slowRead(T, unaligned_address);
 }
 
+pub fn dbgRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
+    const bits = @typeInfo(std.math.IntFittingRange(0, page_size - 1)).Int.bits;
+    const page = unaligned_address >> bits;
+    const offset = unaligned_address & (page_size - 1);
+
+    // We're doing some serious out-of-bounds open-bus reads
+    if (page >= table_len) return self.openBus(T, unaligned_address);
+
+    if (self.read_table[page]) |some_ptr| {
+        // We have a pointer to a page, cast the pointer to it's underlying type
+        const Ptr = [*]const T;
+        const ptr = @ptrCast(Ptr, @alignCast(@alignOf(std.meta.Child(Ptr)), some_ptr));
+
+        // Note: We don't check array length, since we force align the
+        // lower bits of the address as the GBA would
+        return ptr[forceAlign(T, offset) / @sizeOf(T)];
+    }
+
+    return self.dbgSlowRead(T, unaligned_address);
+}
+
 fn slowRead(self: *Self, comptime T: type, unaligned_address: u32) T {
     @setCold(true);
 
@@ -337,7 +318,7 @@ fn slowRead(self: *Self, comptime T: type, unaligned_address: u32) T {
         // General Internal Memory
         0x00 => blk: {
             if (address < Bios.size)
-                break :blk self.bios.read(T, self.cpu.r[15], address);
+                break :blk self.bios.read(T, self.cpu.r[15], unaligned_address);
 
             break :blk self.openBus(T, address);
         },
@@ -352,22 +333,52 @@ fn slowRead(self: *Self, comptime T: type, unaligned_address: u32) T {
 
         // External Memory (Game Pak)
         0x08...0x0D => self.pak.read(T, address),
-        0x0E...0x0F => blk: {
+        0x0E...0x0F => self.readBackup(T, unaligned_address),
-            const value = self.pak.backup.read(unaligned_address);
-
-            const multiplier = switch (T) {
-                u32 => 0x01010101,
-                u16 => 0x0101,
-                u8 => 1,
-                else => @compileError("Backup: Unsupported read width"),
-            };
-
-            break :blk @as(T, value) * multiplier;
-        },
         else => self.openBus(T, address),
     };
 }
 
+fn dbgSlowRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
+    const page = @truncate(u8, unaligned_address >> 24);
+    const address = forceAlign(T, unaligned_address);
+
+    return switch (page) {
+        // General Internal Memory
+        0x00 => blk: {
+            if (address < Bios.size)
+                break :blk self.bios.dbgRead(T, self.cpu.r[15], unaligned_address);
+
+            break :blk self.openBus(T, address);
+        },
+        0x02 => unreachable, // handled by fastmem
+        0x03 => unreachable, // handled by fastmem
+        0x04 => self.readIo(T, address),
+
+        // Internal Display Memory
+        0x05 => unreachable, // handled by fastmem
+        0x06 => unreachable, // handled by fastmem
+        0x07 => unreachable, // handled by fastmem
+
+        // External Memory (Game Pak)
+        0x08...0x0D => self.pak.dbgRead(T, address),
+        0x0E...0x0F => self.readBackup(T, unaligned_address),
+        else => self.openBus(T, address),
+    };
+}
+
+fn readBackup(self: *const Self, comptime T: type, unaligned_address: u32) T {
+    const value = self.pak.backup.read(unaligned_address);
+
+    const multiplier = switch (T) {
+        u32 => 0x01010101,
+        u16 => 0x0101,
+        u8 => 1,
+        else => @compileError("Backup: Unsupported read width"),
+    };
+
+    return @as(T, value) * multiplier;
+}
+
 pub fn write(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
     const bits = @typeInfo(std.math.IntFittingRange(0, page_size - 1)).Int.bits;
     const page = unaligned_address >> bits;
@@ -382,8 +393,7 @@ pub fn write(self: *Self, comptime T: type, unaligned_address: u32, value: T) vo
     if (self.write_tables[@boolToInt(T == u8)][page]) |some_ptr| {
         // We have a pointer to a page, cast the pointer to it's underlying type
         const Ptr = [*]T;
-        const alignment = @alignOf(std.meta.Child(Ptr));
+        const ptr = @ptrCast(Ptr, @alignCast(@alignOf(std.meta.Child(Ptr)), some_ptr));
-        const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
 
         // Note: We don't check array length, since we force align the
         // lower bits of the address as the GBA would
@@ -396,8 +406,34 @@ pub fn write(self: *Self, comptime T: type, unaligned_address: u32, value: T) vo
     }
 }
 
-pub fn slowWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
+/// Mostly Identical to `Bus.write`, slowmeme is handled by `Bus.dbgSlowWrite`
-    // @setCold(true);
+pub fn dbgWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
+    const bits = @typeInfo(std.math.IntFittingRange(0, page_size - 1)).Int.bits;
+    const page = unaligned_address >> bits;
+    const offset = unaligned_address & (page_size - 1);
+
+    // We're doing some serious out-of-bounds open-bus writes, they do nothing though
+    if (page >= table_len) return;
+
+    if (self.write_tables[@boolToInt(T == u8)][page]) |some_ptr| {
+        // We have a pointer to a page, cast the pointer to it's underlying type
+        const Ptr = [*]T;
+        const ptr = @ptrCast(Ptr, @alignCast(@alignOf(std.meta.Child(Ptr)), some_ptr));
+
+        // Note: We don't check array length, since we force align the
+        // lower bits of the address as the GBA would
+        ptr[forceAlign(T, offset) / @sizeOf(T)] = value;
+    } else {
+        // we can return early if this is an 8-bit OAM write
+        if (T == u8 and @truncate(u8, unaligned_address >> 24) == 0x07) return;
+
+        self.dbgSlowWrite(T, unaligned_address, value);
+    }
+}
+
+fn slowWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
+    @setCold(true);
+
     const page = @truncate(u8, unaligned_address >> 24);
     const address = forceAlign(T, unaligned_address);
 
@@ -420,16 +456,41 @@ pub fn slowWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T
     }
 }
 
+fn dbgSlowWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
+    @setCold(true);
+
+    const page = @truncate(u8, unaligned_address >> 24);
+    const address = forceAlign(T, unaligned_address);
+
+    switch (page) {
+        // General Internal Memory
+        0x00 => self.bios.write(T, address, value),
+        0x02 => unreachable, // completely handled by fastmem
+        0x03 => unreachable, // completely handled by fastmem
+        0x04 => return, // FIXME: Let debug writes mess with I/O
+
+        // Internal Display Memory
+        0x05 => self.ppu.palette.write(T, address, value),
+        0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, address, value),
+        0x07 => unreachable, // completely handled by fastmem
+
+        // External Memory (Game Pak)
+        0x08...0x0D => return, // FIXME: Debug Write to Backup/GPIO w/out messing with state
+        0x0E...0x0F => return, // FIXME: Debug Write to Backup w/out messing with state
+        else => {},
+    }
+}
+
 inline fn rotateBy(comptime T: type, address: u32) u32 {
     return switch (T) {
         u32 => address & 3,
         u16 => address & 1,
         u8 => 0,
-        else => @compileError("Backup: Unsupported write width"),
+        else => @compileError("Unsupported write width"),
     };
 }
 
-inline fn forceAlign(comptime T: type, address: u32) u32 {
+pub inline fn forceAlign(comptime T: type, address: u32) u32 {
     return switch (T) {
         u32 => address & ~@as(u32, 3),
         u16 => address & ~@as(u32, 1),

src/core/bus/Bios.zig

@@ -3,6 +3,9 @@ const std = @import("std");
 const Allocator = std.mem.Allocator;
 const log = std.log.scoped(.Bios);
 
+const rotr = @import("../../util.zig").rotr;
+const forceAlign = @import("../Bus.zig").forceAlign;
+
 /// Size of the BIOS in bytes
 pub const size = 0x4000;
 const Self = @This();
@@ -10,21 +13,37 @@ const Self = @This();
 buf: ?[]u8,
 allocator: Allocator,
 
-addr_latch: u32,
+addr_latch: u32 = 0,
 
-pub fn read(self: *Self, comptime T: type, r15: u32, addr: u32) T {
+// https://github.com/ITotalJustice/notorious_beeg/issues/106
+pub fn read(self: *Self, comptime T: type, r15: u32, address: u32) T {
     if (r15 < Self.size) {
+        const addr = forceAlign(T, address);
+
         self.addr_latch = addr;
         return self._read(T, addr);
     }
 
-    log.debug("Rejected read since r15=0x{X:0>8}", .{r15});
+    log.warn("Open Bus! Read from 0x{X:0>8}, but PC was 0x{X:0>8}", .{ address, r15 });
-    return @truncate(T, self._read(T, self.addr_latch));
+    const value = self._read(u32, self.addr_latch);
+
+    return @truncate(T, rotr(u32, value, 8 * rotateBy(T, address)));
 }
 
-pub fn dbgRead(self: *const Self, comptime T: type, r15: u32, addr: u32) T {
+fn rotateBy(comptime T: type, address: u32) u32 {
-    if (r15 < Self.size) return self._read(T, addr);
+    return switch (T) {
-    return @truncate(T, self._read(T, self.addr_latch + 8));
+        u8 => address & 3,
+        u16 => address & 2,
+        u32 => 0,
+        else => @compileError("bios: unsupported read width"),
+    };
+}
+
+pub fn dbgRead(self: *const Self, comptime T: type, r15: u32, address: u32) T {
+    if (r15 < Self.size) return self._read(T, forceAlign(T, address));
+
+    const value = self._read(u32, self.addr_latch);
+    return @truncate(T, rotr(u32, value, 8 * rotateBy(T, address)));
 }
 
 /// Read without the GBA safety checks
@@ -43,18 +62,19 @@ pub fn write(_: *Self, comptime T: type, addr: u32, value: T) void {
 }
 
 pub fn init(allocator: Allocator, maybe_path: ?[]const u8) !Self {
-    const buf: ?[]u8 = if (maybe_path) |path| blk: {
+    if (maybe_path == null) return .{ .buf = null, .allocator = allocator };
-        const file = try std.fs.cwd().openFile(path, .{});
+    const path = maybe_path.?;
-        defer file.close();
 
-        break :blk try file.readToEndAlloc(allocator, try file.getEndPos());
+    const buf = try allocator.alloc(u8, Self.size);
-    } else null;
+    errdefer allocator.free(buf);
 
-    return Self{
+    const file = try std.fs.cwd().openFile(path, .{});
-        .buf = buf,
+    defer file.close();
-        .allocator = allocator,
+
-        .addr_latch = 0,
+    const file_len = try file.readAll(buf);
-    };
+    if (file_len != Self.size) log.err("Expected BIOS to be {}B, was {}B", .{ Self.size, file_len });
+
+    return Self{ .buf = buf, .allocator = allocator };
 }
 
 pub fn deinit(self: *Self) void {

src/core/bus/GamePak.zig

@@ -213,6 +213,7 @@ fn guessDevice(buf: []const u8) Gpio.Device.Kind {
     // Try to Guess if ROM uses RTC
     const needle = "RTC_V"; // I was told SIIRTC_V, though Pokemen Firered (USA) is a false negative
 
+    // TODO: Use new for loop syntax?
     var i: usize = 0;
     while ((i + needle.len) < buf.len) : (i += 1) {
         if (std.mem.eql(u8, needle, buf[i..(i + needle.len)])) return .Rtc;

src/core/bus/backup.zig

@@ -137,6 +137,7 @@ pub const Backup = struct {
         for (backup_kinds) |needle| {
             const needle_len = needle.str.len;
 
+            // TODO: Use new for loop syntax?
             var i: usize = 0;
             while ((i + needle_len) < rom.len) : (i += 1) {
                 if (std.mem.eql(u8, needle.str, rom[i..][0..needle_len])) return needle.kind;

src/core/bus/dma.zig

@@ -338,11 +338,8 @@ fn DmaController(comptime id: u2) type {
     };
 }
 
-pub fn pollDmaOnBlank(bus: *Bus, comptime kind: DmaKind) void {
+pub fn onBlanking(bus: *Bus, comptime kind: DmaKind) void {
-    comptime var i: usize = 0;
+    inline for (0..4) |i| bus.dma[i].poll(kind);
-    inline while (i < 4) : (i += 1) {
-        bus.dma[i].poll(kind);
-    }
 }
 
 const Adjustment = enum(u2) {

src/core/bus/gpio.zig

@@ -293,13 +293,13 @@ pub const Clock = struct {
         self.cpu.sched.push(.RealTimeClock, (1 << 24) -| late); // Reschedule
 
         const now = DateTime.now();
-        self.year = bcd(u8, @intCast(u8, now.date.year - 2000));
+        self.year = bcd(@intCast(u8, now.date.year - 2000));
-        self.month = bcd(u5, now.date.month);
+        self.month = @truncate(u5, bcd(now.date.month));
-        self.day = bcd(u6, now.date.day);
+        self.day = @truncate(u6, bcd(now.date.day));
-        self.weekday = bcd(u3, (now.date.weekday() + 1) % 7); // API is Monday = 0, Sunday = 6. We want Sunday = 0, Saturday = 6
+        self.weekday = @truncate(u3, bcd((now.date.weekday() + 1) % 7)); // API is Monday = 0, Sunday = 6. We want Sunday = 0, Saturday = 6
-        self.hour = bcd(u6, now.time.hour);
+        self.hour = @truncate(u6, bcd(now.time.hour));
-        self.minute = bcd(u7, now.time.minute);
+        self.minute = @truncate(u7, bcd(now.time.minute));
-        self.second = bcd(u7, now.time.second);
+        self.second = @truncate(u7, bcd(now.time.second));
     }
 
     fn step(self: *Self, value: Data) u4 {
@@ -449,16 +449,8 @@ pub const Clock = struct {
     }
 };
 
-fn bcd(comptime T: type, value: u8) T {
+/// Converts an 8-bit unsigned integer to its BCD representation.
-    var input = value;
+/// Note: Algorithm only works for values between 0 and 99 inclusive.
-    var ret: u8 = 0;
+fn bcd(value: u8) u8 {
-    var shift: u3 = 0;
+    return ((value / 10) << 4) + (value % 10);
-
-    while (input > 0) {
-        ret |= (input % 10) << (shift << 2);
-        shift += 1;
-        input /= 10;
-    }
-
-    return @truncate(T, ret);
 }

src/core/bus/io.zig

@@ -449,6 +449,8 @@ pub const BldY = extern union {
     raw: u16,
 };
 
+const u8WriteKind = enum { Hi, Lo };
+
 /// Write-only
 pub const WinH = extern union {
     x2: Bitfield(u16, 0, 8),
@@ -458,6 +460,8 @@ pub const WinH = extern union {
 
 /// Write-only
 pub const WinV = extern union {
+    const Self = @This();
+
     y2: Bitfield(u16, 0, 8),
     y1: Bitfield(u16, 8, 8),
     raw: u16,
@@ -466,20 +470,20 @@ pub const WinV = extern union {
 pub const WinIn = extern union {
     w0_bg: Bitfield(u16, 0, 4),
     w0_obj: Bit(u16, 4),
-    w0_colour: Bit(u16, 5),
+    w0_bld: Bit(u16, 5),
     w1_bg: Bitfield(u16, 8, 4),
     w1_obj: Bit(u16, 12),
-    w1_colour: Bit(u16, 13),
+    w1_bld: Bit(u16, 13),
     raw: u16,
 };
 
 pub const WinOut = extern union {
     out_bg: Bitfield(u16, 0, 4),
     out_obj: Bit(u16, 4),
-    out_colour: Bit(u16, 5),
+    out_bld: Bit(u16, 5),
     obj_bg: Bitfield(u16, 8, 4),
     obj_obj: Bit(u16, 12),
-    obj_colour: Bit(u16, 13),
+    obj_bld: Bit(u16, 13),
     raw: u16,
 };
 

src/core/cpu.zig

@@ -39,13 +39,12 @@ pub const arm = struct {
     }
 
     fn populate() [0x1000]InstrFn {
-        return comptime {
+        comptime {
             @setEvalBranchQuota(0xE000);
-            var ret = [_]InstrFn{und} ** 0x1000;
+            var table = [_]InstrFn{und} ** 0x1000;
 
-            var i: usize = 0;
+            for (&table, 0..) |*handler, i| {
-            while (i < ret.len) : (i += 1) {
+                handler.* = switch (@as(u2, i >> 10)) {
-                ret[i] = switch (@as(u2, i >> 10)) {
                     0b00 => if (i == 0x121) blk: {
                         break :blk branchExchange;
                     } else if (i & 0xFCF == 0x009) blk: {
@@ -107,8 +106,8 @@ pub const arm = struct {
                 };
             }
 
-            return ret;
+            return table;
-        };
+        }
     }
 };
 
@@ -136,13 +135,12 @@ pub const thumb = struct {
     }
 
     fn populate() [0x400]InstrFn {
-        return comptime {
+        comptime {
             @setEvalBranchQuota(5025); // This is exact
-            var ret = [_]InstrFn{und} ** 0x400;
+            var table = [_]InstrFn{und} ** 0x400;
 
-            var i: usize = 0;
+            for (&table, 0..) |*handler, i| {
-            while (i < ret.len) : (i += 1) {
+                handler.* = switch (@as(u3, i >> 7 & 0x7)) {
-                ret[i] = switch (@as(u3, i >> 7 & 0x7)) {
                     0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
                         const I = i >> 4 & 1 == 1;
                         const is_sub = i >> 3 & 1 == 1;
@@ -230,8 +228,8 @@ pub const thumb = struct {
                 };
             }
 
-            return ret;
+            return table;
-        };
+        }
     }
 };
 
@@ -385,8 +383,7 @@ pub const Arm7tdmi = struct {
         const now = getModeChecked(self, self.cpsr.mode.read());
 
         // Bank R8 -> r12
-        var i: usize = 0;
+        for (0..5) |i| {
-        while (i < 5) : (i += 1) {
             self.bank.fiq[Bank.fiqIdx(i, now)] = self.r[8 + i];
         }
 
@@ -404,8 +401,7 @@ pub const Arm7tdmi = struct {
         }
 
         // Grab R8 -> R12
-        i = 0;
+        for (0..5) |i| {
-        while (i < 5) : (i += 1) {
             self.r[8 + i] = self.bank.fiq[Bank.fiqIdx(i, next)];
         }
 
@@ -470,8 +466,7 @@ pub const Arm7tdmi = struct {
     }
 
     pub fn stepDmaTransfer(self: *Self) bool {
-        comptime var i: usize = 0;
+        inline for (0..4) |i| {
-        inline while (i < 4) : (i += 1) {
             if (self.bus.dma[i].in_progress) {
                 self.bus.dma[i].step(self);
                 return true;

src/core/cpu/arm/data_processing.zig

@@ -24,7 +24,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
 
             var result: u32 = undefined;
-            var overflow: bool = undefined;
+            var overflow: u1 = undefined;
 
             // Perform Data Processing Logic
             switch (kind) {
@@ -62,7 +62,9 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
                     if (rd == 0xF)
                         return undefinedTestBehaviour(cpu);
 
-                    overflow = @addWithOverflow(u32, op1, op2, &result);
+                    const tmp = @addWithOverflow(op1, op2);
+                    result = tmp[0];
+                    overflow = tmp[1];
                 },
                 0xC => result = op1 | op2, // ORR
                 0xD => result = op2, // MOV
@@ -110,7 +112,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
                     // ADD, ADC Flags
                     cpu.cpsr.n.write(result >> 31 & 1 == 1);
                     cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(overflow);
+                    cpu.cpsr.c.write(overflow == 0b1);
                     cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
                 },
                 0x6, 0x7 => if (S and rd != 0xF) {
@@ -141,7 +143,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
                         cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
                     } else if (kind == 0xB) {
                         // CMN specific
-                        cpu.cpsr.c.write(overflow);
+                        cpu.cpsr.c.write(overflow == 0b1);
                         cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
                     } else {
                         // TST, TEQ specific
@@ -162,19 +164,19 @@ pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
     return ret;
 }
 
-pub fn add(overflow: *bool, left: u32, right: u32) u32 {
+pub fn add(overflow: *u1, left: u32, right: u32) u32 {
-    var ret: u32 = undefined;
+    const ret = @addWithOverflow(left, right);
-    overflow.* = @addWithOverflow(u32, left, right, &ret);
+    overflow.* = ret[1];
-    return ret;
+
+    return ret[0];
 }
 
-pub fn adc(overflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
+pub fn adc(overflow: *u1, left: u32, right: u32, old_carry: u1) u32 {
-    var ret: u32 = undefined;
+    const tmp = @addWithOverflow(left, right);
-    const first = @addWithOverflow(u32, left, right, &ret);
+    const ret = @addWithOverflow(tmp[0], old_carry);
-    const second = @addWithOverflow(u32, ret, old_carry, &ret);
+    overflow.* = tmp[1] | ret[1];
 
-    overflow.* = first or second;
+    return ret[0];
-    return ret;
 }
 
 fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {

src/core/cpu/arm/single_data_transfer.zig

@@ -11,9 +11,7 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
 
-            // rn is r15 and L is not set, the PC is 12 ahead
+            const base = cpu.r[rn];
-            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
-
             const offset = if (I) shifter.immediate(false, cpu, opcode) else opcode & 0xFFF;
 
             const modified_base = if (U) base +% offset else base -% offset;

src/core/cpu/thumb/alu.zig

@@ -21,7 +21,8 @@ pub fn fmt4(comptime op: u4) InstrFn {
             const op2 = cpu.r[rs];
 
             var result: u32 = undefined;
-            var overflow: bool = undefined;
+            var overflow: u1 = undefined;
+
             switch (op) {
                 0x0 => result = op1 & op2, // AND
                 0x1 => result = op1 ^ op2, // EOR
@@ -34,7 +35,12 @@ pub fn fmt4(comptime op: u4) InstrFn {
                 0x8 => result = op1 & op2, // TST
                 0x9 => result = 0 -% op2, // NEG
                 0xA => result = op1 -% op2, // CMP
-                0xB => overflow = @addWithOverflow(u32, op1, op2, &result), // CMN
+                0xB => {
+                    // CMN
+                    const tmp = @addWithOverflow(op1, op2);
+                    result = tmp[0];
+                    overflow = tmp[1];
+                },
                 0xC => result = op1 | op2, // ORR
                 0xD => result = @truncate(u32, @as(u64, op2) * @as(u64, op1)),
                 0xE => result = op1 & ~op2,
@@ -71,7 +77,7 @@ pub fn fmt4(comptime op: u4) InstrFn {
                     // ADC, CMN
                     cpu.cpsr.n.write(result >> 31 & 1 == 1);
                     cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(overflow);
+                    cpu.cpsr.c.write(overflow == 0b1);
                     cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
                 },
                 0x6 => {

src/core/cpu/thumb/block_data_transfer.zig

@@ -92,8 +92,7 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
 inline fn countRlist(opcode: u16) u32 {
     var count: u32 = 0;
 
-    comptime var i: u4 = 0;
+    inline for (0..8) |i| {
-    inline while (i < 8) : (i += 1) {
         if (opcode >> (7 - i) & 1 == 1) count += 1;
     }
 

src/core/cpu/thumb/data_processing.zig

@@ -64,7 +64,7 @@ pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
             const op2 = cpu.r[rs];
 
             var result: u32 = undefined;
-            var overflow: bool = undefined;
+            var overflow: u1 = undefined;
             switch (op) {
                 0b00 => result = add(&overflow, op1, op2), // ADD
                 0b01 => result = op1 -% op2, // CMP
@@ -126,13 +126,13 @@ pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
                 cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
             } else {
                 // ADD
-                var overflow: bool = undefined;
+                var overflow: u1 = undefined;
                 const result = add(&overflow, op1, op2);
                 cpu.r[rd] = result;
 
                 cpu.cpsr.n.write(result >> 31 & 1 == 1);
                 cpu.cpsr.z.write(result == 0);
-                cpu.cpsr.c.write(overflow);
+                cpu.cpsr.c.write(overflow == 0b1);
                 cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
             }
         }
@@ -145,7 +145,7 @@ pub fn fmt3(comptime op: u2, comptime rd: u3) InstrFn {
             const op1 = cpu.r[rd];
             const op2: u32 = opcode & 0xFF; // Offset
 
-            var overflow: bool = undefined;
+            var overflow: u1 = undefined;
             const result: u32 = switch (op) {
                 0b00 => op2, // MOV
                 0b01 => op1 -% op2, // CMP
@@ -169,7 +169,7 @@ pub fn fmt3(comptime op: u2, comptime rd: u3) InstrFn {
                 },
                 0b10 => {
                     // ADD
-                    cpu.cpsr.c.write(overflow);
+                    cpu.cpsr.c.write(overflow == 0b1);
                     cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
                 },
             }

src/core/emu.zig

@@ -94,7 +94,7 @@ pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi) void {
         if (!cpu.stepDmaTransfer()) {
             if (cpu.isHalted()) {
                 // Fast-forward to next Event
-                sched.tick = sched.queue.peek().?.tick;
+                sched.tick = sched.nextTimestamp();
             } else {
                 cpu.step();
             }
@@ -146,9 +146,8 @@ fn sleep(timer: *Timer, wake_time: u64) ?u64 {
 
     const step = 2 * std.time.ns_per_ms; // Granularity of 2ms
     const times = sleep_for / step;
-    var i: usize = 0;
 
-    while (i < times) : (i += 1) {
+    for (0..times) |_| {
         std.time.sleep(step);
 
         // Upon wakeup, check to see if this particular sleep was longer than expected
@@ -163,3 +162,59 @@ fn sleep(timer: *Timer, wake_time: u64) ?u64 {
 fn spinLoop(timer: *Timer, wake_time: u64) void {
     while (true) if (timer.read() > wake_time) break;
 }
+
+pub const EmuThing = struct {
+    const Self = @This();
+    const Interface = @import("gdbstub").Emulator;
+    const Allocator = std.mem.Allocator;
+
+    cpu: *Arm7tdmi,
+    scheduler: *Scheduler,
+
+    pub fn init(cpu: *Arm7tdmi, scheduler: *Scheduler) Self {
+        return .{ .cpu = cpu, .scheduler = scheduler };
+    }
+
+    pub fn interface(self: *Self, allocator: Allocator) Interface {
+        return Interface.init(allocator, self);
+    }
+
+    pub fn read(self: *const Self, addr: u32) u8 {
+        return self.cpu.bus.dbgRead(u8, addr);
+    }
+
+    pub fn write(self: *Self, addr: u32, value: u8) void {
+        self.cpu.bus.dbgWrite(u8, addr, value);
+    }
+
+    pub fn registers(self: *const Self) *[16]u32 {
+        return &self.cpu.r;
+    }
+
+    pub fn cpsr(self: *const Self) u32 {
+        return self.cpu.cpsr.raw;
+    }
+
+    pub fn step(self: *Self) void {
+        const cpu = self.cpu;
+        const sched = self.scheduler;
+
+        // Is true when we have executed one (1) instruction
+        var did_step: bool = false;
+
+        // TODO: How can I make it easier to keep this in lock-step with runFrame?
+        while (!did_step) {
+            if (!cpu.stepDmaTransfer()) {
+                if (cpu.isHalted()) {
+                    // Fast-forward to next Event
+                    sched.tick = sched.queue.peek().?.tick;
+                } else {
+                    cpu.step();
+                    did_step = true;
+                }
+            }
+
+            if (sched.tick >= sched.nextTimestamp()) sched.handleEvent(cpu);
+        }
+    }
+};

src/core/ppu/Oam.zig

@@ -0,0 +1,40 @@
+const std = @import("std");
+
+const Allocator = std.mem.Allocator;
+
+const buf_len = 0x400;
+const Self = @This();
+
+buf: []u8,
+allocator: Allocator,
+
+pub fn read(self: *const Self, comptime T: type, address: usize) T {
+    const addr = address & 0x3FF;
+
+    return switch (T) {
+        u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
+        else => @compileError("OAM: Unsupported read width"),
+    };
+}
+
+pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
+    const addr = address & 0x3FF;
+
+    switch (T) {
+        u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
+        u8 => return, // 8-bit writes are explicitly ignored
+        else => @compileError("OAM: Unsupported write width"),
+    }
+}
+
+pub fn init(allocator: Allocator) !Self {
+    const buf = try allocator.alloc(u8, buf_len);
+    std.mem.set(u8, buf, 0);
+
+    return Self{ .buf = buf, .allocator = allocator };
+}
+
+pub fn deinit(self: *Self) void {
+    self.allocator.free(self.buf);
+    self.* = undefined;
+}

src/core/ppu/Palette.zig

@@ -0,0 +1,47 @@
+const std = @import("std");
+
+const Allocator = std.mem.Allocator;
+
+const buf_len = 0x400;
+const Self = @This();
+
+buf: []u8,
+allocator: Allocator,
+
+pub fn read(self: *const Self, comptime T: type, address: usize) T {
+    const addr = address & 0x3FF;
+
+    return switch (T) {
+        u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
+        else => @compileError("PALRAM: Unsupported read width"),
+    };
+}
+
+pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
+    const addr = address & 0x3FF;
+
+    switch (T) {
+        u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
+        u8 => {
+            const align_addr = addr & ~@as(u32, 1); // Aligned to Halfword boundary
+            std.mem.writeIntSliceLittle(u16, self.buf[align_addr..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
+        },
+        else => @compileError("PALRAM: Unsupported write width"),
+    }
+}
+
+pub fn init(allocator: Allocator) !Self {
+    const buf = try allocator.alloc(u8, buf_len);
+    std.mem.set(u8, buf, 0);
+
+    return Self{ .buf = buf, .allocator = allocator };
+}
+
+pub fn deinit(self: *Self) void {
+    self.allocator.free(self.buf);
+    self.* = undefined;
+}
+
+pub inline fn backdrop(self: *const Self) u16 {
+    return std.mem.readIntNative(u16, self.buf[0..2]);
+}

src/core/ppu/Vram.zig

@@ -0,0 +1,60 @@
+const std = @import("std");
+const io = @import("../bus/io.zig");
+
+const Allocator = std.mem.Allocator;
+
+const buf_len = 0x18000;
+const Self = @This();
+
+buf: []u8,
+allocator: Allocator,
+
+pub fn read(self: *const Self, comptime T: type, address: usize) T {
+    const addr = Self.mirror(address);
+
+    return switch (T) {
+        u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
+        else => @compileError("VRAM: Unsupported read width"),
+    };
+}
+
+pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address: usize, value: T) void {
+    const mode: u3 = dispcnt.bg_mode.read();
+    const idx = Self.mirror(address);
+
+    switch (T) {
+        u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[idx..][0..@sizeOf(T)], value),
+        u8 => {
+            // Ignore write if it falls within the boundaries of OBJ VRAM
+            switch (mode) {
+                0, 1, 2 => if (0x0001_0000 <= idx) return,
+                else => if (0x0001_4000 <= idx) return,
+            }
+
+            const align_idx = idx & ~@as(u32, 1); // Aligned to a halfword boundary
+            std.mem.writeIntSliceLittle(u16, self.buf[align_idx..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
+        },
+        else => @compileError("VRAM: Unsupported write width"),
+    }
+}
+
+pub fn init(allocator: Allocator) !Self {
+    const buf = try allocator.alloc(u8, buf_len);
+    std.mem.set(u8, buf, 0);
+
+    return Self{ .buf = buf, .allocator = allocator };
+}
+
+pub fn deinit(self: *Self) void {
+    self.allocator.free(self.buf);
+    self.* = undefined;
+}
+
+pub fn mirror(address: usize) usize {
+    // Mirrored in steps of 128K (64K + 32K + 32K) (abcc)
+    const addr = address & 0x1FFFF;
+
+    // If the address is within 96K we don't do anything,
+    // otherwise we want to mirror the last 32K (addresses between 64K and 96K)
+    return if (addr < buf_len) addr else 0x10000 + (addr & 0x7FFF);
+}

src/core/scheduler.zig

@@ -31,61 +31,55 @@ pub const Scheduler = struct {
     }
 
     pub fn handleEvent(self: *Self, cpu: *Arm7tdmi) void {
-        if (self.queue.removeOrNull()) |event| {
+        const event = self.queue.remove();
-            const late = self.tick - event.tick;
+        const late = self.tick - event.tick;
 
-            switch (event.kind) {
+        switch (event.kind) {
-                .HeatDeath => {
+            .HeatDeath => {
-                    log.err("u64 overflow. This *actually* should never happen.", .{});
+                log.err("u64 overflow. This *actually* should never happen.", .{});
-                    unreachable;
+                unreachable;
-                },
+            },
-                .Draw => {
+            .Draw => {
-                    // The end of a VDraw
+                // The end of a VDraw
-                    cpu.bus.ppu.drawScanline();
+                cpu.bus.ppu.drawScanline();
-                    cpu.bus.ppu.onHdrawEnd(cpu, late);
+                cpu.bus.ppu.onHdrawEnd(cpu, late);
-                },
+            },
-                .TimerOverflow => |id| {
+            .TimerOverflow => |id| {
-                    switch (id) {
+                switch (id) {
-                        inline 0...3 => |idx| cpu.bus.tim[idx].onTimerExpire(cpu, late),
+                    inline 0...3 => |idx| cpu.bus.tim[idx].onTimerExpire(cpu, late),
-                    }
+                }
-                },
+            },
-                .ApuChannel => |id| {
+            .ApuChannel => |id| {
-                    switch (id) {
+                switch (id) {
-                        0 => cpu.bus.apu.ch1.onToneSweepEvent(late),
+                    0 => cpu.bus.apu.ch1.onToneSweepEvent(late),
-                        1 => cpu.bus.apu.ch2.onToneEvent(late),
+                    1 => cpu.bus.apu.ch2.onToneEvent(late),
-                        2 => cpu.bus.apu.ch3.onWaveEvent(late),
+                    2 => cpu.bus.apu.ch3.onWaveEvent(late),
-                        3 => cpu.bus.apu.ch4.onNoiseEvent(late),
+                    3 => cpu.bus.apu.ch4.onNoiseEvent(late),
-                    }
+                }
-                },
+            },
-                .RealTimeClock => {
+            .RealTimeClock => {
-                    const device = &cpu.bus.pak.gpio.device;
+                const device = &cpu.bus.pak.gpio.device;
-                    if (device.kind != .Rtc or device.ptr == null) return;
+                if (device.kind != .Rtc or device.ptr == null) return;
 
-                    const clock = @ptrCast(*Clock, @alignCast(@alignOf(*Clock), device.ptr.?));
+                const clock = @ptrCast(*Clock, @alignCast(@alignOf(*Clock), device.ptr.?));
-                    clock.onClockUpdate(late);
+                clock.onClockUpdate(late);
-                },
+            },
-                .FrameSequencer => cpu.bus.apu.onSequencerTick(late),
+            .FrameSequencer => cpu.bus.apu.onSequencerTick(late),
-                .SampleAudio => cpu.bus.apu.sampleAudio(late),
+            .SampleAudio => cpu.bus.apu.sampleAudio(late),
-                .HBlank => cpu.bus.ppu.onHblankEnd(cpu, late), // The end of a HBlank
+            .HBlank => cpu.bus.ppu.onHblankEnd(cpu, late), // The end of a HBlank
-                .VBlank => cpu.bus.ppu.onHdrawEnd(cpu, late), // The end of a VBlank
+            .VBlank => cpu.bus.ppu.onHdrawEnd(cpu, late), // The end of a VBlank
-            }
         }
     }
 
     /// Removes the **first** scheduled event of type `needle`
     pub fn removeScheduledEvent(self: *Self, needle: EventKind) void {
-        var it = self.queue.iterator();
+        for (self.queue.items, 0..) |event, i| {
-
-        var i: usize = 0;
-        while (it.next()) |event| : (i += 1) {
             if (std.meta.eql(event.kind, needle)) {
 
-                // This invalidates the iterator
+                // invalidates the slice we're iterating over
                 _ = self.queue.removeIndex(i);
 
-                // Since removing something from the PQ invalidates the iterator,
+                log.debug("Removed {?}@{}", .{ event.kind, event.tick });
-                // this implementation can safely only remove the first instance of
-                // a Scheduled Event. Exit Early
                 break;
             }
         }

src/main.zig

@@ -4,14 +4,17 @@ const known_folders = @import("known_folders");
 const clap = @import("clap");
 
 const config = @import("config.zig");
+const emu = @import("core/emu.zig");
 
 const Gui = @import("platform.zig").Gui;
 const Bus = @import("core/Bus.zig");
 const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
 const Scheduler = @import("core/scheduler.zig").Scheduler;
 const FilePaths = @import("util.zig").FilePaths;
-
+const FpsTracker = @import("util.zig").FpsTracker;
 const Allocator = std.mem.Allocator;
+const Atomic = std.atomic.Atomic;
+
 const log = std.log.scoped(.Cli);
 const width = @import("core/ppu.zig").width;
 const height = @import("core/ppu.zig").height;
@@ -22,6 +25,7 @@ const params = clap.parseParamsComptime(
     \\-h, --help            Display this help and exit.
     \\-s, --skip            Skip BIOS.
     \\-b, --bios <str>      Optional path to a GBA BIOS ROM.
+    \\ --gdb                Run ZBA from the context of a GDB Server
     \\<str>                 Path to the GBA GamePak ROM.
     \\
 );
@@ -87,13 +91,49 @@ pub fn main() void {
         cpu.fastBoot();
     }
 
+    var quit = Atomic(bool).init(false);
     var gui = Gui.init(&bus.pak.title, &bus.apu, width, height) catch |e| exitln("failed to init gui: {}", .{e});
     defer gui.deinit();
 
-    gui.run(&cpu, &scheduler) catch |e| exitln("failed to run gui thread: {}", .{e});
+    if (result.args.gdb) {
+        const Server = @import("gdbstub").Server;
+        const EmuThing = @import("core/emu.zig").EmuThing;
+
+        var wrapper = EmuThing.init(&cpu, &scheduler);
+        var emulator = wrapper.interface(allocator);
+        defer emulator.deinit();
+
+        log.info("Ready to connect", .{});
+
+        var server = Server.init(emulator) catch |e| exitln("failed to init gdb server: {}", .{e});
+        defer server.deinit(allocator);
+
+        log.info("Starting GDB Server Thread", .{});
+
+        const thread = std.Thread.spawn(.{}, Server.run, .{ &server, allocator, &quit }) catch |e| exitln("gdb server thread crashed: {}", .{e});
+        defer thread.join();
+
+        gui.run(.{
+            .cpu = &cpu,
+            .scheduler = &scheduler,
+            .quit = &quit,
+        }) catch |e| exitln("main thread panicked: {}", .{e});
+    } else {
+        var tracker = FpsTracker.init();
+
+        const thread = std.Thread.spawn(.{}, emu.run, .{ &quit, &scheduler, &cpu, &tracker }) catch |e| exitln("emu thread panicked: {}", .{e});
+        defer thread.join();
+
+        gui.run(.{
+            .cpu = &cpu,
+            .scheduler = &scheduler,
+            .tracker = &tracker,
+            .quit = &quit,
+        }) catch |e| exitln("main thread panicked: {}", .{e});
+    }
 }
 
-pub fn handleArguments(allocator: Allocator, data_path: []const u8, result: *const clap.Result(clap.Help, &params, clap.parsers.default)) !FilePaths {
+fn handleArguments(allocator: Allocator, data_path: []const u8, result: *const clap.Result(clap.Help, &params, clap.parsers.default)) !FilePaths {
     const rom_path = romPath(result);
     log.info("ROM path: {s}", .{rom_path});
 

src/platform.zig

@@ -64,7 +64,7 @@ pub const Gui = struct {
         const ctx = SDL.SDL_GL_CreateContext(window) orelse panic();
         if (SDL.SDL_GL_MakeCurrent(window, ctx) < 0) panic();
 
-        try gl.load(ctx, Self.glGetProcAddress);
+        gl.load(ctx, Self.glGetProcAddress) catch {};
         if (SDL.SDL_GL_SetSwapInterval(@boolToInt(config.config().host.vsync)) < 0) panic();
 
         const program_id = try compileShaders();
@@ -154,9 +154,17 @@ pub const Gui = struct {
         return tex_id;
     }
 
-    pub fn run(self: *Self, cpu: *Arm7tdmi, scheduler: *Scheduler) !void {
+    const RunOptions = struct {
-        var quit = std.atomic.Atomic(bool).init(false);
+        quit: *std.atomic.Atomic(bool),
-        var tracker = FpsTracker.init();
+        tracker: ?*FpsTracker = null,
+        cpu: *Arm7tdmi,
+        scheduler: *Scheduler,
+    };
+
+    pub fn run(self: *Self, opt: RunOptions) !void {
+        const cpu = opt.cpu;
+        const tracker = opt.tracker;
+        const quit = opt.quit;
 
         var buffer_ids = Self.generateBuffers();
         defer {
@@ -169,13 +177,15 @@ pub const Gui = struct {
         const tex_id = Self.generateTexture(cpu.bus.ppu.framebuf.get(.Renderer));
         defer gl.deleteTextures(1, &tex_id);
 
-        const thread = try std.Thread.spawn(.{}, emu.run, .{ &quit, scheduler, cpu, &tracker });
-        defer thread.join();
-
         var title_buf: [0x100]u8 = undefined;
 
         emu_loop: while (true) {
             var event: SDL.SDL_Event = undefined;
+
+            // This might be true if the emu is running via a gdbstub server
+            // and the gdb stub exits first
+            if (quit.load(.Monotonic)) break :emu_loop;
+
             while (SDL.SDL_PollEvent(&event) != 0) {
                 switch (event.type) {
                     SDL.SDL_QUIT => break :emu_loop,
@@ -238,8 +248,10 @@ pub const Gui = struct {
             gl.drawElements(gl.TRIANGLES, 6, gl.UNSIGNED_INT, null);
             SDL.SDL_GL_SwapWindow(self.window);
 
-            const dyn_title = std.fmt.bufPrintZ(&title_buf, "ZBA | {s} [Emu: {}fps] ", .{ self.title, tracker.value() }) catch unreachable;
+            if (tracker) |t| {
-            SDL.SDL_SetWindowTitle(self.window, dyn_title.ptr);
+                const dyn_title = std.fmt.bufPrintZ(&title_buf, "ZBA | {s} [Emu: {}fps] ", .{ self.title, t.value() }) catch unreachable;
+                SDL.SDL_SetWindowTitle(self.window, dyn_title.ptr);
+            }
         }
 
         quit.store(true, .Monotonic); // Terminate Emulator Thread

src/util.zig

@@ -5,6 +5,8 @@ const config = @import("config.zig");
 const Log2Int = std.math.Log2Int;
 const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
 
+const Allocator = std.mem.Allocator;
+
 // Sign-Extend value of type `T` to type `U`
 pub fn sext(comptime T: type, comptime U: type, value: T) T {
     // U must have less bits than T
@@ -123,6 +125,7 @@ pub const io = struct {
 
 pub const Logger = struct {
     const Self = @This();
+    const FmtArgTuple = std.meta.Tuple(&.{ u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32 });
 
     buf: std.io.BufferedWriter(4096 << 2, std.fs.File.Writer),
 
@@ -181,8 +184,6 @@ pub const Logger = struct {
     }
 };
 
-const FmtArgTuple = struct { u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32 };
-
 pub const audio = struct {
     const _io = @import("core/bus/io.zig");
 
@@ -275,3 +276,44 @@ fn HalfInt(comptime T: type) type {
 
     return std.meta.Int(type_info.Int.signedness, type_info.Int.bits >> 1);
 }
+
+/// Double Buffering Implementation
+pub const FrameBuffer = struct {
+    const Self = @This();
+
+    layers: [2][]u8,
+    buf: []u8,
+    current: u1,
+
+    allocator: Allocator,
+
+    // TODO: Rename
+    const Device = enum { Emulator, Renderer };
+
+    pub fn init(allocator: Allocator, comptime len: comptime_int) !Self {
+        const buf = try allocator.alloc(u8, len * 2);
+        std.mem.set(u8, buf, 0);
+
+        return .{
+            // Front and Back Framebuffers
+            .layers = [_][]u8{ buf[0..][0..len], buf[len..][0..len] },
+            .buf = buf,
+            .current = 0,
+
+            .allocator = allocator,
+        };
+    }
+
+    pub fn deinit(self: *Self) void {
+        self.allocator.free(self.buf);
+        self.* = undefined;
+    }
+
+    pub fn swap(self: *Self) void {
+        self.current = ~self.current;
+    }
+
+    pub fn get(self: *Self, comptime dev: Device) []u8 {
+        return self.layers[if (dev == .Emulator) self.current else ~self.current];
+    }
+};