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7adc7c8802
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fix(cpu): make Data Processing instructions r15-aware
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2022-01-12 07:20:24 -04:00 |
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072a66cfdb
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fix(cpu): write results of ORR to destination register
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2022-01-10 10:56:41 -04:00 |
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ed3bdd90fb
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feat(cpu): implement TEQ
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2022-01-10 08:09:02 -04:00 |
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e9c1c94cae
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feat(cpu): Implement ORR
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2022-01-10 08:06:00 -04:00 |
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568c374131
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chore: code cleanup
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2022-01-07 20:00:42 -04:00 |
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910745f442
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chore(bus): refactor bus.zig
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2022-01-07 19:49:58 -04:00 |
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f8c6af3247
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chore: refactor instruction exec code
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2022-01-07 19:44:48 -04:00 |
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5037b8f0cc
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feat: implement S (when rd != 15) for several data processing instructions
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2022-01-05 15:45:52 -05:00 |
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28a70d0112
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feat: implement dedicated Barrel Shifter SHL and SHR
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2022-01-05 13:58:11 -05:00 |
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7473ffedc7
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chore: stub TST
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2022-01-04 04:08:02 -06:00 |
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ed9c1413b1
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fix(cpu): properly implement SUB/CMP CSPSR carry bit condition
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2022-01-04 03:08:08 -06:00 |
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1c42d1795a
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feat(bus): add Io Struct
Also, add more information to all panic messages
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2022-01-02 14:40:49 -06:00 |
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de9045fba3
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chore: use bitfield library
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2022-01-02 13:01:11 -06:00 |
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c40a1af534
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chore: conform to zig style guides
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2022-01-01 21:08:47 -06:00 |
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92a06e49c3
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chore(cpu): iron out some false assumptions
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2022-01-01 03:41:50 -06:00 |
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5b3b81e4dc
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Initial Commit
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2021-12-29 15:09:00 -06:00 |
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