Commit Graph

478 Commits

Author SHA1 Message Date
Rekai Nyangadzayi Musuka d85e0c8d05 feat(cpu): implement format 1 THUMB instructions 2022-01-29 17:29:30 -04:00
Rekai Nyangadzayi Musuka 995633e9e8 fix: dont close file handle early 2022-01-29 01:18:45 -04:00
Rekai Nyangadzayi Musuka cfbd292edc feat(cpu): implement format 6 THUMB instructions 2022-01-29 01:18:41 -04:00
Rekai Nyangadzayi Musuka 95efb3f35d chore: rename title 2022-01-28 23:27:03 -04:00
Rekai Nyangadzayi Musuka 6a6dccf4d8 chore: refactor GBA Display Timings
This change should reflect that the Hblank bit of DISPSTAT is toggled on all scanlines
while also ensuring that the Vblank bit is set on all Vblank scanlines
2022-01-28 22:58:19 -04:00
Rekai Nyangadzayi Musuka ad1db4dc2e chore: move a single statement lol 2022-01-28 22:57:48 -04:00
Rekai Nyangadzayi Musuka 19359f7ee4 chore: mark indexing methods as inline 2022-01-28 17:11:29 -04:00
Rekai Nyangadzayi Musuka 24f0922f86 feat: create emulator thread 2022-01-28 16:33:38 -04:00
Rekai Nyangadzayi Musuka b1cc985230 chore: disable logging by default 2022-01-25 18:20:30 -04:00
Rekai Nyangadzayi Musuka e5c8f0ce07 chore: revert fastboot changes 2022-01-25 18:20:01 -04:00
Rekai Nyangadzayi Musuka fbc5b309b0 chore: binary logging + file logging + DP chanes + fastBoot changes 2022-01-25 18:18:52 -04:00
Rekai Nyangadzayi Musuka 899a9ead76 chore: ignore .bin files 2022-01-25 12:58:25 -04:00
Rekai Nyangadzayi Musuka 540fbf739a chore: rename skipBios to fastBoot 2022-01-25 11:15:17 -04:00
Rekai Nyangadzayi Musuka 0546b1c308 chore: set correct values for select banked registers on fast boot 2022-01-25 11:14:15 -04:00
Rekai Nyangadzayi Musuka 997dc1314c feat(cpu): implement SWI 2022-01-25 10:34:21 -04:00
Rekai Nyangadzayi Musuka 1456d0f317 chore(bios): allow reading from BIOS 2022-01-25 10:32:28 -04:00
Rekai Nyangadzayi Musuka 6257418405 fix(cpu): interim solution to weird program counter behaviour on illegal tst instruction 2022-01-25 09:23:32 -04:00
Rekai Nyangadzayi Musuka 985fefb9f6 chore(cpu): implement behaviour for undefined test instruction 2022-01-25 08:05:42 -04:00
Rekai Nyangadzayi Musuka 95dd3e3df8 fix(cpu): fix PC offset when barrel shifter and bit 4 of DP is set 2022-01-24 17:52:01 -04:00
Rekai Nyangadzayi Musuka 038c0a9283 chore: remove reccomended extension 2022-01-23 23:13:16 -04:00
Rekai Nyangadzayi Musuka 702ff288d8 fix(cpu): implement S set + rd == 15 case for data processing 2022-01-19 07:46:49 -04:00
Rekai Nyangadzayi Musuka bf36a23722 feat(cpu): implement banked registers 2022-01-19 07:29:49 -04:00
Rekai Nyangadzayi Musuka fc5a3460dd fix(cpu): improve MRS and MSR instructions 2022-01-18 20:17:00 -04:00
Rekai Nyangadzayi Musuka 6177927049 feat(cpu): implement CMN 2022-01-18 15:09:25 -04:00
Rekai Nyangadzayi Musuka 903b75c7c4 fix(barrel_shifter): fix PC being 1 word ahead in barrel shifter 2022-01-18 15:08:29 -04:00
Rekai Nyangadzayi Musuka 8d786cbe25 feat(cpu): Implement RSC 2022-01-18 14:46:57 -04:00
Rekai Nyangadzayi Musuka 212bc9e11d feat(cpu): implement RSB 2022-01-18 14:36:03 -04:00
Rekai Nyangadzayi Musuka 63a57ac954 feat(cpu): implement BIC 2022-01-18 14:28:47 -04:00
Rekai Nyangadzayi Musuka 85dae5e1d7 feat(cpu): implement EOR 2022-01-18 14:27:07 -04:00
Rekai Nyangadzayi Musuka 6189bf0315 feat(cpu): implement ADD 2022-01-18 14:25:29 -04:00
Rekai Nyangadzayi Musuka 2f3213f693 feat(cpu): implement fix for ADC and implement SBC 2022-01-18 14:20:01 -04:00
Rekai Nyangadzayi Musuka a62cd9aa40 chore(barrel_shifter): remove panic from ASR 2022-01-18 14:19:58 -04:00
Rekai Nyangadzayi Musuka 25c57a4cc7 fix(barrel_shifter): should not modify cpsr when amount == 0 2022-01-18 13:30:41 -04:00
Rekai Nyangadzayi Musuka a7a44c4463 chore(cpu): refactor the barrel shifter once again 2022-01-17 15:55:55 -04:00
Rekai Nyangadzayi Musuka d4d2fedfbe feat(cpu): implement ADC
ADC interacting w/ the Barrel Shifter is not working though
2022-01-17 14:29:34 -04:00
Rekai Nyangadzayi Musuka 483e149b32 feat(cpu): implement RRX for Barrel Shifter 2022-01-17 14:19:40 -04:00
Rekai Nyangadzayi Musuka 85ffdf44f5 feat(cpu): implement SUB in THUMB format 3 2022-01-17 11:36:02 -04:00
Rekai Nyangadzayi Musuka 9098a55ae3 feat(cpu): implement ARM SUB in data processing 2022-01-17 11:35:41 -04:00
Rekai Nyangadzayi Musuka c0d956ea95 feat(cpu): implement MVN 2022-01-17 11:30:59 -04:00
Rekai Nyangadzayi Musuka 1025500407 chore(cpu): refactor barrel shifter 2022-01-17 11:17:04 -04:00
Rekai Nyangadzayi Musuka d05a924420 fix(cpu): use barrel shifter in data processing immediates 2022-01-17 11:02:34 -04:00
Rekai Nyangadzayi Musuka 2a416fb2c6 feat(cpu): implement format 12 thumb instructions 2022-01-17 10:07:50 -04:00
Rekai Nyangadzayi Musuka ea5f0ce552 feat(cpu): implement some already decoded format 3 instructions 2022-01-17 09:29:11 -04:00
Rekai Nyangadzayi Musuka e55d2dc323 feat(cpu): implement THUMB format 5 instructions 2022-01-17 09:28:46 -04:00
Rekai Nyangadzayi Musuka 3037407ebe chore: mgba log now supports printing THUMB instructions 2022-01-17 07:18:44 -04:00
Rekai Nyangadzayi Musuka 1915d98bdd feat(cpu): implement like 1 THUMB instruction 2022-01-16 12:46:59 -04:00
Rekai Nyangadzayi Musuka 4606a1ab25 chore: distinguish between undefined ARM and THUMB instr 2022-01-14 05:30:32 -04:00
Rekai Nyangadzayi Musuka 0cf052838d chore(cpu): lay groundwork for THUMB instruction decoding and execution 2022-01-14 05:23:16 -04:00
Rekai Nyangadzayi Musuka ae37b1218b chore(cpu): refactor ARM functions to make room for THUMB 2022-01-14 04:26:09 -04:00
Rekai Nyangadzayi Musuka 070322064d fix(cpu): fix conditions for GT cond 2022-01-14 04:19:54 -04:00