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39ab363afa
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fix: improve perf of instructions w/ rotr
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2022-03-16 22:56:37 -03:00 |
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237beb9caa
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feat(cpu): Pass all LDR/STR ARMwrestler tests
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2022-02-02 14:07:18 -04:00 |
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e0acabf050
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chore: relocate barrel_shifter zig file
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2022-01-29 18:52:16 -04:00 |
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ae37b1218b
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chore(cpu): refactor ARM functions to make room for THUMB
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2022-01-14 04:26:09 -04:00 |
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7adc7c8802
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fix(cpu): make Data Processing instructions r15-aware
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2022-01-12 07:20:24 -04:00 |
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74abd3df4d
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feat(cpu): implement MSR and MRS
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2022-01-12 04:48:57 -04:00 |
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0d4c850218
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chore: remove premature inlines
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2022-01-10 01:24:14 -04:00 |
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568c374131
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chore: code cleanup
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2022-01-07 20:00:42 -04:00 |
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5037b8f0cc
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feat: implement S (when rd != 15) for several data processing instructions
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2022-01-05 15:45:52 -05:00 |
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28a70d0112
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feat: implement dedicated Barrel Shifter SHL and SHR
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2022-01-05 13:58:11 -05:00 |
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