|  | 39ab363afa | fix: improve perf of instructions w/ rotr | 2022-03-16 22:56:37 -03:00 |  | 
			
				
					|  | cb4d3a9a51 | chore: replace unnecessarily complex sign extension implementation | 2022-02-28 20:38:50 -04:00 |  | 
			
				
					|  | b93bd53529 | chore: make use of scoped logging | 2022-02-11 01:33:33 -04:00 |  | 
			
				
					|  | ee27053db3 | chore: remove TODOs and some useless imports | 2022-02-06 19:07:23 -04:00 |  | 
			
				
					|  | bbd4447734 | fix(cpu): force align thumb and arm block data transfers | 2022-02-06 17:08:12 -04:00 |  | 
			
				
					|  | 225c0f7d55 | feat: pass arm.gba | 2022-02-06 05:06:25 -04:00 |  | 
			
				
					|  | fcde905ae1 | chore: reimplement ARM LDM/STM | 2022-02-06 04:34:45 -04:00 |  | 
			
				
					|  | 798987eba0 | chore: improve arm ldm/stm | 2022-02-05 23:29:34 -04:00 |  | 
			
				
					|  | adfd501fc4 | fix(cpu): force-align SWP reads and writes | 2022-02-05 23:18:23 -04:00 |  | 
			
				
					|  | 9581e3b3cb | fix: force-align ARM STRH reads | 2022-02-05 23:09:13 -04:00 |  | 
			
				
					|  | 1b9ab1f1d7 | fix: implement the same LDRSH logic as THUMB LDRSH | 2022-02-05 23:09:02 -04:00 |  | 
			
				
					|  | c52dc5adb1 | fix: PC is 12 ahead when it is rd in str and strb | 2022-02-05 21:42:04 -04:00 |  | 
			
				
					|  | 7bfb87a859 | fix: listen to my past self By deleting this line I go from test 234 to test 355 in arm.gba | 2022-02-05 21:35:26 -04:00 |  | 
			
				
					|  | 2842345111 | chore: remove unnecessary @as calls | 2022-02-05 21:01:39 -04:00 |  | 
			
				
					|  | b233981a34 | feat: rename ARM and THUMB SWI functions | 2022-02-04 04:34:47 -04:00 |  | 
			
				
					|  | 1b8db0c427 | chore: group THUMB and select ARM instructions together (same file) | 2022-02-04 04:18:20 -04:00 |  | 
			
				
					|  | c6bb4bf8e1 | fix(cpu): allow for select values to overflow FuzzARM found these operations which panicked, when they should
have overflowed. These are now fixed
n = 8000 | 2022-02-02 22:49:33 -04:00 |  | 
			
				
					|  | c2901ee0d8 | fix(cpu): account for rn in rlist in block data transfer | 2022-02-02 17:35:33 -04:00 |  | 
			
				
					|  | d95efa5b12 | feat: implement LDM/STM behaviour when S is set | 2022-02-02 16:12:47 -04:00 |  | 
			
				
					|  | 237beb9caa | feat(cpu): Pass all LDR/STR ARMwrestler tests | 2022-02-02 14:07:18 -04:00 |  | 
			
				
					|  | c34c2ee6eb | feat(cpu): implement ARM SWP and SWPB | 2022-02-02 08:44:33 -04:00 |  | 
			
				
					|  | 48017b45f5 | feat(cpu): Implement Multiply Long ARM instructions | 2022-02-01 22:09:38 -04:00 |  | 
			
				
					|  | 0d7600ed7a | chore: more detailed panic message | 2022-02-01 19:11:56 -04:00 |  | 
			
				
					|  | 85927a943f | feat(cpu): implement SWP | 2022-02-01 16:30:55 -04:00 |  | 
			
				
					|  | b27bf4a85c | fix(cpu): perform MUL with u64s, throw away upper 32 bits | 2022-02-01 16:15:08 -04:00 |  | 
			
				
					|  | dd632975f8 | fix(cpu): properly decode multiply instructions | 2022-01-30 02:16:12 -04:00 |  | 
			
				
					|  | a459d4b433 | feat(cpu): implement ARM multiply instructions | 2022-01-30 02:04:24 -04:00 |  | 
			
				
					|  | ae4023e51c | chore: dedup code in THUMB instructions | 2022-01-29 20:05:27 -04:00 |  | 
			
				
					|  | bce067557f | chore: refactor and genericize ARM data processing calculations | 2022-01-29 19:40:58 -04:00 |  | 
			
				
					|  | e0acabf050 | chore: relocate barrel_shifter zig file | 2022-01-29 18:52:16 -04:00 |  | 
			
				
					|  | 599e068c7e | feat(cpu): implement format2 THUMB instructions | 2022-01-29 18:46:27 -04:00 |  | 
			
				
					|  | fbc5b309b0 | chore: binary logging + file logging + DP chanes + fastBoot changes | 2022-01-25 18:18:52 -04:00 |  | 
			
				
					|  | 997dc1314c | feat(cpu): implement SWI | 2022-01-25 10:34:21 -04:00 |  | 
			
				
					|  | 6257418405 | fix(cpu): interim solution to weird program counter behaviour on illegal tst instruction | 2022-01-25 09:23:32 -04:00 |  | 
			
				
					|  | 985fefb9f6 | chore(cpu): implement behaviour for undefined test instruction | 2022-01-25 08:05:42 -04:00 |  | 
			
				
					|  | 95dd3e3df8 | fix(cpu): fix PC offset when barrel shifter and bit 4 of DP is set | 2022-01-24 17:52:01 -04:00 |  | 
			
				
					|  | 702ff288d8 | fix(cpu): implement S set + rd == 15 case for data processing | 2022-01-19 07:46:49 -04:00 |  | 
			
				
					|  | bf36a23722 | feat(cpu): implement banked registers | 2022-01-19 07:29:49 -04:00 |  | 
			
				
					|  | fc5a3460dd | fix(cpu): improve MRS and MSR instructions | 2022-01-18 20:17:00 -04:00 |  | 
			
				
					|  | 6177927049 | feat(cpu): implement CMN | 2022-01-18 15:09:25 -04:00 |  | 
			
				
					|  | 903b75c7c4 | fix(barrel_shifter): fix PC being 1 word ahead in barrel shifter | 2022-01-18 15:08:29 -04:00 |  | 
			
				
					|  | 8d786cbe25 | feat(cpu): Implement RSC | 2022-01-18 14:46:57 -04:00 |  | 
			
				
					|  | 212bc9e11d | feat(cpu): implement RSB | 2022-01-18 14:36:03 -04:00 |  | 
			
				
					|  | 63a57ac954 | feat(cpu): implement BIC | 2022-01-18 14:28:47 -04:00 |  | 
			
				
					|  | 85dae5e1d7 | feat(cpu): implement EOR | 2022-01-18 14:27:07 -04:00 |  | 
			
				
					|  | 6189bf0315 | feat(cpu): implement ADD | 2022-01-18 14:25:29 -04:00 |  | 
			
				
					|  | 2f3213f693 | feat(cpu): implement fix for ADC and implement SBC | 2022-01-18 14:20:01 -04:00 |  | 
			
				
					|  | a62cd9aa40 | chore(barrel_shifter): remove panic from ASR | 2022-01-18 14:19:58 -04:00 |  | 
			
				
					|  | 25c57a4cc7 | fix(barrel_shifter): should not modify cpsr when amount == 0 | 2022-01-18 13:30:41 -04:00 |  | 
			
				
					|  | a7a44c4463 | chore(cpu): refactor the barrel shifter once again | 2022-01-17 15:55:55 -04:00 |  |