feat(cpu): Implement Multiply Long ARM instructions
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@ -18,6 +18,7 @@ const branch = @import("cpu/arm/branch.zig").branch;
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const branchAndExchange = @import("cpu/arm/branch.zig").branchAndExchange;
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const softwareInterrupt = @import("cpu/arm/software_interrupt.zig").softwareInterrupt;
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const multiply = @import("cpu/arm/multiply.zig").multiply;
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const multiplyLong = @import("cpu/arm/multiply_long.zig").multiplyLong;
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// THUMB Instruction Groups
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const format1 = @import("cpu/thumb/format1.zig").format1;
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@ -533,6 +534,14 @@ fn armPopulate() [0x1000]ArmInstrFn {
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lut[i] = multiply(A, S);
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}
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if (i >> 7 & 0x1F == 0b00001 and i & 0xF == 0b1001) {
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const U = i >> 6 & 1 == 1;
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const A = i >> 5 & 1 == 1;
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const S = i >> 4 & 1 == 1;
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lut[i] = multiplyLong(U, A, S);
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}
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if (i >> 10 & 0x3 == 0b01) {
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const I = i >> 9 & 1 == 1;
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const P = i >> 8 & 1 == 1;
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@ -0,0 +1,38 @@
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const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ArmInstrFn;
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pub fn multiplyLong(comptime U: bool, comptime A: bool, comptime S: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
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const rd_hi = opcode >> 16 & 0xF;
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const rd_lo = opcode >> 12 & 0xF;
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const rs = opcode >> 8 & 0xF;
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const rm = opcode & 0xF;
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if (U) {
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// Signed (WHY IS IT U THEN?)
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var result: i64 = @as(i64, @bitCast(i32, cpu.r[rm])) * @as(i64, @bitCast(i32, cpu.r[rs]));
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if (A) result += @bitCast(i64, @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]));
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cpu.r[rd_hi] = @bitCast(u32, @truncate(i32, result >> 32));
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cpu.r[rd_lo] = @bitCast(u32, @truncate(i32, result));
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} else {
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// Unsigned
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var result: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]);
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if (A) result += @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]);
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cpu.r[rd_hi] = @truncate(u32, result >> 32);
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cpu.r[rd_lo] = @truncate(u32, result);
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}
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if (S) {
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cpu.cpsr.z.write(cpu.r[rd_hi] == 0 and cpu.r[rd_lo] == 0);
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cpu.cpsr.n.write(cpu.r[rd_hi] >> 31 & 1 == 1);
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// C and V are set to meaningless values
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}
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}
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}.inner;
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}
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