chore: update to Zig v0.13.0

- impl behaviour of running v5te instrs on v4t cpu
- impl undefined instruction exception handler
- panic on what I think are still unimplemented v5te opcodes

.gitignore

@@ -1,2 +1,3 @@
 zig-out/
 zig-cache/
+.zig-cache/

build.zig

@@ -15,33 +15,33 @@ pub fn build(b: *std.Build) void {
     // set a preferred release mode, allowing the user to decide how to optimize.
     const optimize = b.standardOptimizeOption(.{});
 
-    const lib = b.addStaticLibrary(.{
+    const util_dep = b.dependency("zba-util", .{}); // https://git.musuka.dev/paoda/zba-util
-        .name = "arm32",
+    const bitfield_mod = b.createModule(.{ .root_source_file = b.path("lib/bitfield.zig") }); // https://github.com/FlorenceOS/Florence
-        // In this case the main source file is merely a path, however, in more
-        // complicated build scripts, this could be a generated file.
-        .root_source_file = .{ .path = "src/lib.zig" },
-        .target = target,
-        .optimize = optimize,
-    });
 
-    // This declares intent for the library to be installed into the standard
+    _ = b.addModule("arm32", .{
-    // location when the user invokes the "install" step (the default step when
+        .root_source_file = b.path("src/lib.zig"),
-    // running `zig build`).
+        .imports = &.{
-    b.installArtifact(lib);
+            .{ .name = "zba-util", .module = util_dep.module("zba-util") },
+            .{ .name = "bitfield", .module = bitfield_mod },
+        },
+    });
 
     // Creates a step for unit testing. This only builds the test executable
     // but does not run it.
-    const main_tests = b.addTest(.{
+    const lib_unit_tests = b.addTest(.{
-        .root_source_file = .{ .path = "src/lib.zig" },
+        .root_source_file = b.path("src/lib.zig"),
         .target = target,
         .optimize = optimize,
     });
 
-    const run_main_tests = b.addRunArtifact(main_tests);
+    lib_unit_tests.root_module.addImport("zba-util", util_dep.module("zba-util"));
+    lib_unit_tests.root_module.addImport("bitfield", bitfield_mod);
 
-    // This creates a build step. It will be visible in the `zig build --help` menu,
+    const run_lib_unit_tests = b.addRunArtifact(lib_unit_tests);
-    // and can be selected like this: `zig build test`
+
-    // This will evaluate the `test` step rather than the default, which is "install".
+    // Similar to creating the run step earlier, this exposes a `test` step to
-    const test_step = b.step("test", "Run library tests");
+    // the `zig build --help` menu, providing a way for the user to request
-    test_step.dependOn(&run_main_tests.step);
+    // running the unit tests.
+    const test_step = b.step("test", "Run unit tests");
+    test_step.dependOn(&run_lib_unit_tests.step);
 }

build.zig.zon

@@ -0,0 +1,77 @@
+.{
+    // This is the default name used by packages depending on this one. For
+    // example, when a user runs `zig fetch --save <url>`, this field is used
+    // as the key in the `dependencies` table. Although the user can choose a
+    // different name, most users will stick with this provided value.
+    //
+    // It is redundant to include "zig" in this name because it is already
+    // within the Zig package namespace.
+    .name = "zba-util",
+
+    // This is a [Semantic Version](https://semver.org/).
+    // In a future version of Zig it will be used for package deduplication.
+    .version = "0.1.0",
+
+    // This field is optional.
+    // This is currently advisory only; Zig does not yet do anything
+    // with this value.
+    //.minimum_zig_version = "0.11.0",
+
+    // This field is optional.
+    // Each dependency must either provide a `url` and `hash`, or a `path`.
+    // `zig build --fetch` can be used to fetch all dependencies of a package, recursively.
+    // Once all dependencies are fetched, `zig build` no longer requires
+    // internet connectivity.
+    .dependencies = .{
+        // See `zig fetch --save <url>` for a command-line interface for adding dependencies.
+        //.example = .{
+        //    // When updating this field to a new URL, be sure to delete the corresponding
+        //    // `hash`, otherwise you are communicating that you expect to find the old hash at
+        //    // the new URL.
+        //    .url = "https://example.com/foo.tar.gz",
+        //
+        //    // This is computed from the file contents of the directory of files that is
+        //    // obtained after fetching `url` and applying the inclusion rules given by
+        //    // `paths`.
+        //    //
+        //    // This field is the source of truth; packages do not come from a `url`; they
+        //    // come from a `hash`. `url` is just one of many possible mirrors for how to
+        //    // obtain a package matching this `hash`.
+        //    //
+        //    // Uses the [multihash](https://multiformats.io/multihash/) format.
+        //    .hash = "...",
+        //
+        //    // When this is provided, the package is found in a directory relative to the
+        //    // build root. In this case the package's hash is irrelevant and therefore not
+        //    // computed. This field and `url` are mutually exclusive.
+        //    .path = "foo",
+
+        //    // When this is set to `true`, a package is declared to be lazily
+        //    // fetched. This makes the dependency only get fetched if it is
+        //    // actually used.
+        //    .lazy = false,
+        //},
+        .@"zba-util" = .{
+            .url = "https://git.musuka.dev/paoda/zba-util/archive/bf0e744047ce1ec90172dbcc0c72bfcc29a063e3.tar.gz",
+            .hash = "1220d044ecfbeacc3b3cebeff131d587e24167d61435a3cb96dffd4d4521bb06aed0",
+        },
+    },
+
+    // Specifies the set of files and directories that are included in this package.
+    // Only files and directories listed here are included in the `hash` that
+    // is computed for this package. Only files listed here will remain on disk
+    // when using the zig package manager. As a rule of thumb, one should list
+    // files required for compilation plus any license(s).
+    // Paths are relative to the build root. Use the empty string (`""`) to refer to
+    // the build root itself.
+    // A directory listed here means that all files within, recursively, are included.
+    .paths = .{
+        "build.zig",
+        "build.zig.zon",
+        "src",
+        "lib/bitfield.zig",
+        // For example...
+        //"LICENSE",
+        //"README.md",
+    },
+}

lib/bitfield.zig

@@ -0,0 +1,146 @@
+const std = @import("std");
+
+fn PtrCastPreserveCV(comptime T: type, comptime PtrToT: type, comptime NewT: type) type {
+    return switch (PtrToT) {
+        *T => *NewT,
+        *const T => *const NewT,
+        *volatile T => *volatile NewT,
+        *const volatile T => *const volatile NewT,
+
+        else => @compileError("wtf you doing"),
+    };
+}
+
+fn BitType(comptime FieldType: type, comptime ValueType: type, comptime shamt: usize) type {
+    const self_bit: FieldType = (1 << shamt);
+
+    return extern struct {
+        bits: Bitfield(FieldType, shamt, 1),
+
+        pub fn set(self: anytype) void {
+            self.bits.field().* |= self_bit;
+        }
+
+        pub fn unset(self: anytype) void {
+            self.bits.field().* &= ~self_bit;
+        }
+
+        pub fn read(self: anytype) ValueType {
+            return @as(ValueType, @bitCast(@as(u1, @truncate(self.bits.field().* >> shamt))));
+        }
+
+        // Since these are mostly used with MMIO, I want to avoid
+        // reading the memory just to write it again, also races
+        pub fn write(self: anytype, val: ValueType) void {
+            if (@as(bool, @bitCast(val))) {
+                self.set();
+            } else {
+                self.unset();
+            }
+        }
+    };
+}
+
+// Original Bit Constructor
+// pub fn Bit(comptime FieldType: type, comptime shamt: usize) type {
+//     return BitType(FieldType, u1, shamt);
+// }
+
+pub fn Bit(comptime FieldType: type, comptime shamt: usize) type {
+    return BitType(FieldType, bool, shamt);
+}
+
+fn Boolean(comptime FieldType: type, comptime shamt: usize) type {
+    return BitType(FieldType, bool, shamt);
+}
+
+pub fn Bitfield(comptime FieldType: type, comptime shamt: usize, comptime num_bits: usize) type {
+    if (shamt + num_bits > @bitSizeOf(FieldType)) {
+        @compileError("bitfield doesn't fit");
+    }
+
+    const self_mask: FieldType = ((1 << num_bits) - 1) << shamt;
+
+    const ValueType = std.meta.Int(.unsigned, num_bits);
+
+    return extern struct {
+        dummy: FieldType,
+
+        fn field(self: anytype) PtrCastPreserveCV(@This(), @TypeOf(self), FieldType) {
+            return @as(PtrCastPreserveCV(@This(), @TypeOf(self), FieldType), @ptrCast(self));
+        }
+
+        pub fn write(self: anytype, val: ValueType) void {
+            self.field().* &= ~self_mask;
+            self.field().* |= @as(FieldType, @intCast(val)) << shamt;
+        }
+
+        pub fn read(self: anytype) ValueType {
+            const val: FieldType = self.field().*;
+            return @as(ValueType, @intCast((val & self_mask) >> shamt));
+        }
+    };
+}
+
+test "bit" {
+    const S = extern union {
+        low: Bit(u32, 0),
+        high: Bit(u32, 1),
+        val: u32,
+    };
+
+    std.testing.expect(@sizeOf(S) == 4);
+    std.testing.expect(@bitSizeOf(S) == 32);
+
+    var s: S = .{ .val = 1 };
+
+    std.testing.expect(s.low.read() == 1);
+    std.testing.expect(s.high.read() == 0);
+
+    s.low.write(0);
+    s.high.write(1);
+
+    std.testing.expect(s.val == 2);
+}
+
+test "boolean" {
+    const S = extern union {
+        low: Boolean(u32, 0),
+        high: Boolean(u32, 1),
+        val: u32,
+    };
+
+    std.testing.expect(@sizeOf(S) == 4);
+    std.testing.expect(@bitSizeOf(S) == 32);
+
+    var s: S = .{ .val = 2 };
+
+    std.testing.expect(s.low.read() == false);
+    std.testing.expect(s.high.read() == true);
+
+    s.low.write(true);
+    s.high.write(false);
+
+    std.testing.expect(s.val == 1);
+}
+
+test "bitfield" {
+    const S = extern union {
+        low: Bitfield(u32, 0, 16),
+        high: Bitfield(u32, 16, 16),
+        val: u32,
+    };
+
+    std.testing.expect(@sizeOf(S) == 4);
+    std.testing.expect(@bitSizeOf(S) == 32);
+
+    var s: S = .{ .val = 0x13376969 };
+
+    std.testing.expect(s.low.read() == 0x6969);
+    std.testing.expect(s.high.read() == 0x1337);
+
+    s.low.write(0x1337);
+    s.high.write(0x6969);
+
+    std.testing.expect(s.val == 0x69691337);
+}

src/arm.zig

@@ -0,0 +1,586 @@
+const std = @import("std");
+
+const Architecture = enum { v4t, v5te };
+const Interpreter = @import("lib.zig").Interpreter;
+const Bus = @import("lib.zig").Bus;
+const Scheduler = @import("lib.zig").Scheduler;
+const Coprocessor = @import("lib.zig").Coprocessor;
+
+const Bitfield = @import("bitfield").Bitfield;
+const Bit = @import("bitfield").Bit;
+
+fn condition_lut(comptime isa: Architecture) [16]u16 {
+    return [_]u16{
+        0xF0F0, // EQ - Equal
+        0x0F0F, // NE - Not Equal
+        0xCCCC, // CS - Unsigned higher or same
+        0x3333, // CC - Unsigned lower
+        0xFF00, // MI - Negative
+        0x00FF, // PL - Positive or Zero
+        0xAAAA, // VS - Overflow
+        0x5555, // VC - No Overflow
+        0x0C0C, // HI - unsigned hierh
+        0xF3F3, // LS - unsigned lower or same
+        0xAA55, // GE - greater or equal
+        0x55AA, // LT - less than
+        0x0A05, // GT - greater than
+        0xF5FA, // LE - less than or equal
+        0xFFFF, // AL - always
+        if (isa == .v4t) 0x0000 else 0xFFFF, // NV - never
+    };
+}
+
+pub fn Arm32(comptime isa: Architecture) type {
+    const is_v5te = isa == .v5te;
+
+    return struct {
+        const Self = @This();
+        pub const arch = isa;
+
+        r: [16]u32 = [_]u32{0x00} ** 16,
+        pipe: Pipeline = Pipeline.init(),
+        sched: Scheduler,
+        bus: Bus,
+        cpsr: PSR,
+        spsr: PSR,
+
+        bank: Bank = Bank.create(),
+
+        // The following will be `void` on.v4t but exist on v5te
+        itcm: if (is_v5te) Itcm else void,
+        dtcm: if (is_v5te) Dtcm else void,
+        cp15: if (is_v5te) Coprocessor else void,
+
+        const arm = switch (isa) {
+            .v4t => @import("arm/v4t.zig").arm,
+            .v5te => @import("arm/v5te.zig").arm,
+        };
+
+        const thumb = switch (isa) {
+            .v4t => @import("arm/v4t.zig").thumb,
+            .v5te => @import("arm/v5te.zig").thumb,
+        };
+
+        // FIXME: What about .v5te?
+        const Pipeline = struct {
+            stage: [2]?u32,
+            flushed: bool,
+
+            fn init() @This() {
+                return .{
+                    .stage = [_]?u32{null} ** 2,
+                    .flushed = false,
+                };
+            }
+
+            pub fn isFull(self: *const @This()) bool {
+                return self.stage[0] != null and self.stage[1] != null;
+            }
+
+            // TODO: Why does this not return T?
+            pub fn step(self: *@This(), cpu: *Self, comptime T: type) ?u32 {
+                comptime std.debug.assert(T == u32 or T == u16);
+
+                const opcode = self.stage[0];
+                self.stage[0] = self.stage[1];
+                self.stage[1] = cpu.fetch(T, cpu.r[15]);
+
+                return opcode;
+            }
+
+            pub fn reload(self: *@This(), cpu: *Self) void {
+                if (cpu.cpsr.t.read()) {
+                    self.stage[0] = cpu.fetch(u16, cpu.r[15]);
+                    self.stage[1] = cpu.fetch(u16, cpu.r[15] + 2);
+                    cpu.r[15] += 4;
+                } else {
+                    self.stage[0] = cpu.fetch(u32, cpu.r[15]);
+                    self.stage[1] = cpu.fetch(u32, cpu.r[15] + 4);
+                    cpu.r[15] += 8;
+                }
+
+                self.flushed = true;
+            }
+        };
+
+        /// Bank of Registers from other CPU Modes
+        pub const Bank = struct {
+            /// Storage for r13_<mode>, r14_<mode>
+            /// e.g. [r13, r14, r13_svc, r14_svc]
+            r: [2 * 6]u32,
+
+            /// Storage  for R8_fiq -> R12_fiq and their normal counterparts
+            /// e.g [r[0 + 8], fiq_r[0 + 8], r[1 + 8], fiq_r[1 + 8]...]
+            fiq: [2 * 5]u32,
+
+            spsr: [5]PSR,
+
+            const Kind = enum(u1) {
+                R13 = 0,
+                R14,
+            };
+
+            pub fn create() Bank {
+                return .{
+                    .r = [_]u32{0x00} ** 12,
+                    .fiq = [_]u32{0x00} ** 10,
+                    .spsr = [_]PSR{.{ .raw = 0x0000_0000 }} ** 5,
+                };
+            }
+
+            // public so that we can set up fast-boot
+            pub inline fn regIdx(mode: Mode, kind: Kind) usize {
+                const idx: usize = switch (mode) {
+                    .User, .System => 0,
+                    .Supervisor => 1,
+                    .Abort => 2,
+                    .Undefined => 3,
+                    .Irq => 4,
+                    .Fiq => 5,
+                };
+
+                return (idx * 2) + if (kind == .R14) @as(usize, 1) else 0;
+            }
+
+            pub inline fn spsrIdx(mode: Mode) usize {
+                return switch (mode) {
+                    .Supervisor => 0,
+                    .Abort => 1,
+                    .Undefined => 2,
+                    .Irq => 3,
+                    .Fiq => 4,
+                    else => std.debug.panic("[CPU/Mode] {} does not have a SPSR Register", .{mode}),
+                };
+            }
+
+            inline fn fiqIdx(i: usize, mode: Mode) usize {
+                return (i * 2) + if (mode == .Fiq) @as(usize, 1) else 0;
+            }
+        };
+
+        // FIXME: Is this a hack or idiomatic?
+        // See https://github.com/ziglang/zig/blob/1a0e6bcdb140c844384d62b78a7f4247753f9ffd/lib/std/atomic/Atomic.zig#L156-L176
+        pub usingnamespace if (is_v5te) struct {
+            // FIXME: this is pretty NDS9 specific lol
+            pub fn init(scheduler: Scheduler, bus: Bus, cp15: Coprocessor) Self {
+                return .{
+                    .sched = scheduler,
+                    .bus = bus,
+                    .cpsr = .{ .raw = 0x0000_001F },
+                    .spsr = .{ .raw = 0x0000_0000 },
+
+                    .cp15 = cp15,
+                    .dtcm = .{},
+                    .itcm = .{},
+                };
+            }
+
+            // FIXME: Resetting disables logging (if enabled)
+            pub fn reset(self: *Self) void {
+                self.* = .{
+                    .sched = self.sched,
+                    .bus = self.bus,
+                    .cpsr = .{ .raw = 0x0000_001F },
+                    .spsr = .{ .raw = 0x0000_0000 },
+
+                    .dtcm = .{},
+                    .itcm = .{},
+                    .cp15 = self.cp15,
+                };
+            }
+        } else struct {
+            pub fn init(scheduler: Scheduler, bus: Bus) Self {
+                return .{
+                    .sched = scheduler,
+                    .bus = bus,
+                    .cpsr = .{ .raw = 0x0000_001F },
+                    .spsr = .{ .raw = 0x0000_0000 },
+
+                    .cp15 = {},
+                    .dtcm = {},
+                    .itcm = {},
+                };
+            }
+
+            // FIXME: Resetting disables logging (if enabled)
+            pub fn reset(self: *Self) void {
+                self.* = .{
+                    .sched = self.sched,
+                    .bus = self.bus,
+                    .cpsr = .{ .raw = 0x0000_001F },
+                    .spsr = .{ .raw = 0x0000_0000 },
+
+                    .dtcm = {},
+                    .itcm = {},
+                    .cp15 = {},
+                };
+            }
+        };
+
+        pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
+            if (is_v5te) {
+                if (self.itcm.read(T, address)) |val| return val;
+                if (self.dtcm.read(T, address)) |val| return val;
+            }
+
+            return self.bus.dbgRead(T, address);
+        }
+
+        pub fn dbgWrite(self: *Self, comptime T: type, address: u32, value: T) void {
+            if (is_v5te) {
+                if (self.itcm.write(T, address, value)) return;
+                if (self.dtcm.write(T, address, value)) return;
+            }
+
+            return self.bus.dbgWrite(T, address, value);
+        }
+
+        // CPU needs it's own read/write fns due to ICTM and DCTM present in v5te
+        // I considered implementing Bus.cpu_read and Bus.cpu_write but ended up considering that a bit too leaky
+        pub fn read(self: *Self, comptime T: type, address: u32) T {
+            if (is_v5te) {
+                if (self.itcm.read(T, address)) |val| return val;
+                if (self.dtcm.read(T, address)) |val| return val;
+            }
+
+            return self.bus.read(T, address);
+        }
+
+        pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
+            if (is_v5te) {
+                if (self.itcm.write(T, address, value)) return;
+                if (self.dtcm.write(T, address, value)) return;
+            }
+
+            return self.bus.write(T, address, value);
+        }
+
+        pub inline fn hasSPSR(self: *const Self) bool {
+            const mode = Mode.getChecked(self, self.cpsr.mode.read());
+            return switch (mode) {
+                .System, .User => false,
+                else => true,
+            };
+        }
+
+        pub inline fn isPrivileged(self: *const Self) bool {
+            const mode = Mode.getChecked(self, self.cpsr.mode.read());
+            return switch (mode) {
+                .User => false,
+                else => true,
+            };
+        }
+
+        pub fn setCpsr(self: *Self, value: u32) void {
+            if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(value & 0x1F));
+            self.cpsr.raw = value;
+        }
+
+        fn changeModeFromIdx(self: *Self, next: u5) void {
+            self.changeMode(Mode.getChecked(self, next));
+        }
+
+        pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
+            const current = Mode.getChecked(self, self.cpsr.mode.read());
+
+            switch (idx) {
+                8...12 => {
+                    if (current == .Fiq) {
+                        self.bank.fiq[Bank.fiqIdx(idx - 8, .User)] = value;
+                    } else self.r[idx] = value;
+                },
+                13, 14 => switch (current) {
+                    .User, .System => self.r[idx] = value,
+                    else => {
+                        const kind = std.meta.intToEnum(Bank.Kind, idx - 13) catch unreachable;
+                        self.bank.r[Bank.regIdx(.User, kind)] = value;
+                    },
+                },
+                else => self.r[idx] = value, // R0 -> R7  and R15
+            }
+        }
+
+        pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
+            const current = Mode.getChecked(self, self.cpsr.mode.read());
+
+            return switch (idx) {
+                8...12 => if (current == .Fiq) self.bank.fiq[Bank.fiqIdx(idx - 8, .User)] else self.r[idx],
+                13, 14 => switch (current) {
+                    .User, .System => self.r[idx],
+                    else => blk: {
+                        const kind = std.meta.intToEnum(Bank.Kind, idx - 13) catch unreachable;
+                        break :blk self.bank.r[Bank.regIdx(.User, kind)];
+                    },
+                },
+                else => self.r[idx], // R0 -> R7  and R15
+            };
+        }
+
+        pub fn changeMode(self: *Self, next: Mode) void {
+            const now = Mode.getChecked(self, self.cpsr.mode.read());
+
+            // Bank R8 -> r12
+            for (0..5) |i| {
+                self.bank.fiq[Bank.fiqIdx(i, now)] = self.r[8 + i];
+            }
+
+            // Bank r13, r14, SPSR
+            switch (now) {
+                .User, .System => {
+                    self.bank.r[Bank.regIdx(now, .R13)] = self.r[13];
+                    self.bank.r[Bank.regIdx(now, .R14)] = self.r[14];
+                },
+                else => {
+                    self.bank.r[Bank.regIdx(now, .R13)] = self.r[13];
+                    self.bank.r[Bank.regIdx(now, .R14)] = self.r[14];
+                    self.bank.spsr[Bank.spsrIdx(now)] = self.spsr;
+                },
+            }
+
+            // Grab R8 -> R12
+            for (0..5) |i| {
+                self.r[8 + i] = self.bank.fiq[Bank.fiqIdx(i, next)];
+            }
+
+            // Grab r13, r14, SPSR
+            switch (next) {
+                .User, .System => {
+                    self.r[13] = self.bank.r[Bank.regIdx(next, .R13)];
+                    self.r[14] = self.bank.r[Bank.regIdx(next, .R14)];
+                },
+                else => {
+                    self.r[13] = self.bank.r[Bank.regIdx(next, .R13)];
+                    self.r[14] = self.bank.r[Bank.regIdx(next, .R14)];
+                    self.spsr = self.bank.spsr[Bank.spsrIdx(next)];
+                },
+            }
+
+            self.cpsr.mode.write(@intFromEnum(next));
+        }
+
+        pub fn step(self: *Self) void {
+            defer {
+                if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+                self.pipe.flushed = false;
+            }
+
+            if (self.cpsr.t.read()) {
+                const opcode: u16 = @truncate(self.pipe.step(self, u16) orelse return);
+                thumb.lut[thumb.idx(opcode)](self, opcode);
+            } else {
+                const opcode = self.pipe.step(self, u32) orelse return;
+                const cond: u4 = @truncate(opcode >> 28);
+
+                if (self.cpsr.check(Self.arch, cond)) {
+                    if (isa == .v5te and cond == 0b1111) {
+                        std.log.debug("TODO: Unconditional Instruction Extension Space\nopcode: 0x{X:0>8} | idx: 0x{X:} | ptr: {any}", .{ opcode, arm.idx(opcode), arm.lut[arm.idx(opcode)] });
+                    }
+
+                    arm.lut[arm.idx(opcode)](self, opcode);
+                }
+            }
+        }
+
+        inline fn fetch(self: *Self, comptime T: type, address: u32) T {
+            comptime std.debug.assert(T == u32 or T == u16); // Opcode may be 32-bit (ARM) or 16-bit (THUMB)
+
+            // Bus.read will advance the scheduler. There are different timings for CPU fetches,
+            // so we want to undo what Bus.read will apply. We can do this by caching the current tick
+            // This is very dumb.
+            //
+            // FIXME: Please rework this
+            // FIXME: Please Re-enable this
+            // const tick_cache = self.sched.tick;
+            // defer self.sched.tick = tick_cache + Bus.fetch_timings[@boolToInt(T == u32)][@truncate(u4, address >> 24)];
+
+            return self.read(T, address);
+        }
+
+        pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
+            var i: usize = 0;
+            while (i < 16) : (i += 4) {
+                const i_1 = i + 1;
+                const i_2 = i + 2;
+                const i_3 = i + 3;
+                std.debug.print("R{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\n", .{ i, self.r[i], i_1, self.r[i_1], i_2, self.r[i_2], i_3, self.r[i_3] });
+            }
+            std.debug.print("cpsr: 0x{X:0>8} ", .{self.cpsr.raw});
+            self.cpsr.toString();
+
+            std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
+            self.spsr.toString();
+
+            std.debug.print("pipeline: {??X:0>8}\n", .{self.pipe.stage});
+
+            if (self.cpsr.t.read()) {
+                const opcode = self.bus.dbgRead(u16, self.r[15] - 4);
+                const id = thumb.idx(opcode);
+                std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
+            } else {
+                const opcode = self.bus.dbgRead(u32, self.r[15] - 4);
+                const id = arm.idx(opcode);
+                std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
+            }
+
+            std.debug.print("tick: {}\n\n", .{self.sched.now()});
+
+            std.debug.panic(format, args);
+        }
+
+        // TODO: Rename
+        pub fn undefinedInstructionTrap(self: *Self) void {
+            // Copy Values from Current Mode
+            const ret_addr = self.r[15] - @as(u32, if (self.cpsr.t.read()) 2 else 4);
+            const cpsr = self.cpsr.raw;
+
+            // Switch Mode
+            self.changeMode(.Undefined);
+            self.cpsr.t.write(false); // Force ARM Mode
+            self.cpsr.i.write(true); // Disable normal interrupts
+
+            self.r[14] = ret_addr; // Resume Execution
+            self.spsr.raw = cpsr; // Previous mode CPSR
+            self.r[15] = switch (Self.arch) {
+                .v4t => 0x0000_0004,
+                .v5te => blk: {
+                    const ctrl = self.cp15.read(0, 1, 0, 0);
+                    break :blk if (ctrl >> 13 & 1 == 1) 0xFFFF_0004 else 0x0000_0004;
+                },
+            };
+            self.pipe.reload(self);
+        }
+
+        pub fn interface(self: *Self) Interpreter {
+            return switch (isa) {
+                .v4t => .{ .v4t = self },
+                .v5te => .{ .v5te = self },
+            };
+        }
+    };
+}
+
+fn Tcm(comptime count: usize, comptime default_addr: u32) type {
+    const KiB = 0x400;
+
+    return struct {
+        buf: [count * KiB]u8 = [_]u8{0x00} ** (count * KiB),
+        base_address: u32 = default_addr,
+        virt: struct { size: u32, mask: u32 } = .{ .size = count * KiB, .mask = (count * KiB) - 1 },
+
+        enabled: bool = true,
+        load_mode: bool = false,
+
+        /// Read from TCM
+        ///
+        /// Returns `T` on success, which is the value we have read from TCM.
+        /// Returns `null` on failure for one of the following reasons:
+        /// - TCM is disabled
+        /// - TCM is in load mode (TODO: What about SWP and SWPB)
+        /// - TCM Address is not mapped to TCM
+        ///
+        /// The caller doesn't particularly care about "why" though.
+        pub fn read(self: *const @This(), comptime T: type, address: u32) ?T {
+            if (!self.enabled) return null;
+            if (self.load_mode) return null;
+
+            const start_addr = self.base_address;
+            const end_addr = self.base_address + self.virt.size;
+
+            if (start_addr <= address and address < end_addr) {
+                return std.mem.readInt(T, self.buf[address & self.virt.mask ..][0..@sizeOf(T)], .little);
+            }
+
+            return null;
+        }
+
+        /// Write to TCM
+        ///
+        /// Returns `true` on success. Will return `false` for one of the following reasons:
+        /// - TCM is disabled
+        /// - Address is not mapped to TCM
+        ///
+        /// The caller doesn't particularly care about "why" though.
+        pub fn write(self: *@This(), comptime T: type, address: u32, value: T) bool {
+            if (!self.enabled) return false;
+
+            const start_addr = self.base_address;
+            const end_addr = self.base_address + self.virt.size;
+
+            if (start_addr <= address and address < end_addr) {
+                std.mem.writeInt(T, self.buf[address & self.virt.mask ..][0..@sizeOf(T)], value, .little);
+                return true;
+            }
+
+            return false;
+        }
+    };
+}
+
+const Itcm = Tcm(32, 0x0000_0000);
+const Dtcm = Tcm(16, 0x0080_0000); // GBATEK says default is 0x027C_0000...
+
+pub const Mode = enum(u5) {
+    User = 0b10000,
+    Fiq = 0b10001,
+    Irq = 0b10010,
+    Supervisor = 0b10011,
+    Abort = 0b10111,
+    Undefined = 0b11011,
+    System = 0b11111,
+
+    pub fn toString(self: Mode) []const u8 {
+        return switch (self) {
+            .User => "usr",
+            .Fiq => "fiq",
+            .Irq => "irq",
+            .Supervisor => "svc",
+            .Abort => "abt",
+            .Undefined => "und",
+            .System => "sys",
+        };
+    }
+
+    fn get(bits: u5) ?Mode {
+        return std.meta.intToEnum(Mode, bits) catch null;
+    }
+
+    fn getChecked(cpu: anytype, bits: u5) Mode {
+        return get(bits) orelse cpu.panic("[CPU/CPSR] 0b{b:0>5} is an invalid CPU mode", .{bits});
+    }
+};
+
+pub const PSR = extern union {
+    mode: Bitfield(u32, 0, 5),
+    t: Bit(u32, 5),
+    f: Bit(u32, 6),
+    i: Bit(u32, 7),
+
+    q: Bit(u32, 27), // ARMv5TE only
+    v: Bit(u32, 28),
+    c: Bit(u32, 29),
+    z: Bit(u32, 30),
+    n: Bit(u32, 31),
+    raw: u32,
+
+    fn toString(self: @This()) void {
+        std.debug.print("[", .{});
+
+        if (self.n.read()) std.debug.print("N", .{}) else std.debug.print("-", .{});
+        if (self.z.read()) std.debug.print("Z", .{}) else std.debug.print("-", .{});
+        if (self.c.read()) std.debug.print("C", .{}) else std.debug.print("-", .{});
+        if (self.v.read()) std.debug.print("V", .{}) else std.debug.print("-", .{});
+        if (self.i.read()) std.debug.print("I", .{}) else std.debug.print("-", .{});
+        if (self.f.read()) std.debug.print("F", .{}) else std.debug.print("-", .{});
+        if (self.t.read()) std.debug.print("T", .{}) else std.debug.print("-", .{});
+        std.debug.print("|", .{});
+        if (Mode.get(self.mode.read())) |m| std.debug.print("{s}", .{m.toString()}) else std.debug.print("---", .{});
+
+        std.debug.print("]\n", .{});
+    }
+
+    pub inline fn check(self: @This(), isa: Architecture, cond: u4) bool {
+        const flags: u4 = @truncate(self.raw >> 28);
+
+        return condition_lut(isa)[cond] & (@as(u16, 1) << flags) != 0;
+    }
+};

src/arm/cpu/arm/block_data_transfer.zig

@@ -0,0 +1,153 @@
+pub fn blockDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const rn: u4 = @truncate(opcode >> 16 & 0xF);
+            const rlist: u16 = @intCast(opcode & 0xFFFF);
+
+            const reg_count: u32 = @popCount(rlist);
+            const first_in_list: u4 = @truncate(@ctz(rlist)); // note that @ctz(0x0000) and @ctz(0x0001) collide
+
+            // U determines whether the LDM/STM transfer is made upwards (U == 1)
+            // or downwards (U == 0).
+
+            const base_addr = cpu.r[rn];
+
+            const start_addr: u32 = if (U) blk: {
+                break :blk base_addr + if (P) 4 else 0;
+            } else blk: {
+                break :blk base_addr - (4 * reg_count) + if (!P) 4 else 0;
+            };
+
+            const new_base_addr: u32 = if (U) blk: {
+                break :blk base_addr + 4 * reg_count;
+            } else blk: {
+                break :blk base_addr - 4 * reg_count;
+            };
+
+            var address = start_addr;
+
+            // On Empty List:
+            //
+            // ARMv4 Only: R15 is Loaded/Stored
+            // ARMv4/Armv5: Rn = Rn +/- 0x40
+
+            if (rlist == 0) {
+                if (Arm32.arch == .v4t) {
+                    const undefined_addr: u32 = if (U) blk: {
+                        break :blk base_addr + if (P) 4 else 0;
+                    } else blk: {
+                        break :blk base_addr - (0x40 - if (!P) 4 else 0);
+                    };
+
+                    if (L) {
+                        cpu.r[15] = cpu.read(u32, undefined_addr);
+                        cpu.pipe.reload(cpu);
+                    } else {
+                        cpu.write(u32, undefined_addr, cpu.r[15] + 4);
+                    }
+                }
+
+                cpu.r[rn] = if (U) base_addr + 0x40 else base_addr - 0x40;
+                return;
+            }
+
+            for (first_in_list..16) |idx| {
+                const i: u4 = @intCast(idx);
+
+                if (rlist >> i & 1 == 1) {
+                    if (L) {
+                        load(cpu, i, rlist, address);
+                    } else {
+                        store(cpu, rn, i, rlist, address, .{ .old_addr = base_addr, .new_addr = new_base_addr });
+                    }
+
+                    address += 4;
+                }
+            }
+
+            if (W and !L)
+                cpu.r[rn] = new_base_addr;
+
+            if (W and L) {
+                // What happens when W is set and Rn is in the rlist? (LDM)
+                //
+                // ARMv4: No writeback
+                // ARMv5: writeback if Rn is "the ONLY register" or NOT the LAST register
+
+                if (rlist >> rn & 1 == 0) { // rn is not in rlist
+                    cpu.r[rn] = new_base_addr;
+                    return;
+                }
+
+                switch (Arm32.arch) {
+                    .v4t => {}, // No Writeback
+                    .v5te => {
+                        const rn_is_last = (15 - @clz(rlist)) <= rn;
+
+                        if (reg_count == 1 or !rn_is_last) {
+                            cpu.r[rn] = new_base_addr;
+                        }
+                    },
+                }
+            }
+        }
+
+        fn load(cpu: *Arm32, ri: u4, rlist: u16, address: u32) void {
+            const has_r15 = rlist >> 15 & 1 == 1;
+
+            if (S and !has_r15) {
+                // Always Transfer User mode Registers
+                cpu.setUserModeRegister(ri, cpu.read(u32, address));
+            } else {
+                const value = cpu.read(u32, address);
+                cpu.r[ri] = value;
+
+                if (ri == 0xF) {
+                    const mask: u32 = if (Arm32.arch == .v5te) 1 else 3;
+                    cpu.r[ri] &= ~mask;
+
+                    if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
+                    if (S) cpu.setCpsr(cpu.spsr.raw); // FIXME: before or after the reload?
+
+                    cpu.pipe.reload(cpu);
+                }
+            }
+        }
+
+        const BaseAddrs = struct { old_addr: u32, new_addr: u32 };
+
+        fn store(cpu: *Arm32, rn: u4, ri: u4, rlist: u16, address: u32, base: BaseAddrs) void {
+            const value = if (S) blk: {
+                // if S == true:
+                //     Always Transfer User mode Registers
+                //     This happens regardless if r15 is in the list
+
+                break :blk cpu.getUserModeRegister(ri);
+            } else blk: {
+                if (ri == rn) {
+                    // What happens when W is set and Rn is in the rlist? (STM)
+                    //
+                    // Armv4: Store OLD Base if Rb is FIRST entry in Rlist, otherwise store NEW base
+                    // Armv5: Always store OLD Base
+
+                    if (rlist >> rn & 1 == 0)
+                        break :blk base.new_addr;
+
+                    const mask = @as(u16, 1) << rn;
+                    const is_first = @popCount(rlist & (mask - 1)) == 0;
+
+                    break :blk switch (Arm32.arch) {
+                        .v4t => if (is_first) base.old_addr else base.new_addr,
+                        .v5te => base.old_addr,
+                    };
+                }
+
+                break :blk cpu.r[ri];
+            };
+
+            cpu.write(u32, address, value + if (ri == 0xF) 4 else @as(u32, 0));
+        }
+    }.inner;
+}

src/arm/cpu/arm/branch.zig

@@ -0,0 +1,45 @@
+const sext = @import("zba-util").sext;
+
+pub fn branch(comptime InstrFn: type, comptime L: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const cond: u4 = @truncate(opcode >> 28);
+            switch (cond) {
+                0b1111 => { // BLX
+                    const H = L;
+                    const offset = sext(u32, u24, opcode) << 2 | @as(u32, @intFromBool(H)) << 1;
+
+                    cpu.r[14] = cpu.r[15] - 4;
+                    cpu.cpsr.t.set();
+
+                    cpu.r[15] +%= offset;
+                },
+                else => {
+                    if (L) cpu.r[14] = cpu.r[15] - 4;
+
+                    cpu.r[15] +%= sext(u32, u24, opcode) << 2;
+                },
+            }
+
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}
+
+pub fn branchAndExchange(comptime InstrFn: type) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        pub fn inner(cpu: *Arm32, opcode: u32) void {
+            const rn = opcode & 0xF;
+
+            const thumb = cpu.r[rn] & 1 == 1;
+            cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
+
+            cpu.cpsr.t.write(thumb);
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}

src/arm/cpu/arm/coprocessor.zig

@@ -0,0 +1,176 @@
+const std = @import("std");
+const Bit = @import("bitfield").Bit;
+
+const log = std.log.scoped(.coprocessor_handler);
+
+pub fn dataTransfer(
+    comptime InstrFn: type,
+    comptime P: bool,
+    comptime U: bool,
+    comptime N: bool,
+    comptime W: bool,
+    comptime L: bool,
+) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            if (!P and !W and !U) return copExt(cpu, opcode); // Coprocessor Extension Space
+
+            const rn = opcode >> 16 & 0xF;
+            const crd = opcode >> 12 & 0xF;
+            const cp_num = opcode >> 8 & 0xF;
+            const offset = (opcode & 0xFF) << 2;
+
+            // TODO: Make sure this is comptime
+            const addr_mode: u2 = comptime @as(u2, @intFromBool(P)) << 1 | @intFromBool(W);
+
+            const start_address: u32 = switch (addr_mode) {
+                0b00 => blk: {
+                    // Unindexed Addressing
+                    std.debug.assert(U == true);
+
+                    break :blk cpu.r[rn];
+                },
+                0b01 => blk: {
+                    // Immediate Post-Indexed Addressing
+                    const addr = cpu.r[rn];
+                    cpu.r[rn] = if (U) cpu.r[rn] + offset else cpu.r[rn] - offset;
+
+                    break :blk addr;
+                },
+                0b10 => if (U) cpu.r[rn] + offset else cpu.r[rn] - offset, // Immediate Offset Addressing
+                0b11 => blk: {
+                    // Immediate Pre-Indexed Addressing
+                    cpu.r[rn] = if (U) cpu.r[rn] + offset else cpu.r[rn] - offset;
+
+                    break :blk cpu.r[rn];
+                },
+            };
+
+            // TODO: Increment address + 4 (and perform op) until coprocessor says stop
+
+            if (L) {
+                cpu.panic("TODO: ldc{s} p{}, c{}, 0x{X:0>8}", .{ [_]u8{if (N) 'l' else ' '}, cp_num, crd, start_address });
+            } else {
+                cpu.panic("TODO: stc{s} p{}, c{}, 0x{X:0>8}", .{ [_]u8{if (N) 'l' else ' '}, cp_num, crd, start_address });
+            }
+        }
+
+        fn copExt(cpu: *Arm32, opcode: u32) void {
+            const cp_num = opcode >> 8 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+            const rn = opcode >> 16 & 0xF;
+            const crm = opcode & 0xF;
+
+            const cp_opcode = opcode >> 4 & 0xF; // FIXME: We could get this value at comptime
+
+            std.debug.assert(rd != 15); // UNPREDICTABLE
+            std.debug.assert(rn != 15); // UNPREDICTABLE
+
+            if (L) {
+                // MRRC
+                cpu.panic("TODO: mrrc p{}, {}, r{}, r{}, c{}", .{ cp_num, cp_opcode, rd, rn, crm });
+            } else {
+                // MCRR
+                cpu.panic("TODO: mcrr p{}, {}, r{}, r{}, c{}", .{ cp_num, cp_opcode, rd, rn, crm });
+            }
+        }
+    }.inner;
+}
+
+pub fn registerTransfer(comptime InstrFn: type, comptime opcode1: u3, comptime L: bool, comptime opcode2: u3) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const crn: u4 = @intCast(opcode >> 16 & 0xF);
+            const rd = opcode >> 12 & 0xF;
+            const cp_num = opcode >> 8 & 0xF;
+            const crm: u4 = @intCast(opcode & 0xF);
+
+            switch (cp_num) {
+                14 => return,
+                15 => if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap(),
+                else => cpu.panic("MRC: unexpected coprocessor #: {}", .{cp_num}),
+            }
+
+            if (L) {
+                // MRC
+                const value = cpu.cp15.read(opcode1, crn, crm, opcode2);
+
+                if (rd != 0xF) {
+                    cpu.r[rd] = value;
+                    return;
+                }
+
+                // TODO: I can probably do this with a mask and the like
+                cpu.cpsr.n.write(value >> 31 & 1 == 1);
+                cpu.cpsr.z.write(value >> 30 & 1 == 1);
+                cpu.cpsr.c.write(value >> 29 & 1 == 1);
+                cpu.cpsr.v.write(value >> 28 & 1 == 1);
+            } else {
+                // MCR
+                std.debug.assert(rd != 0xF); // UNPREDICTABLE
+
+                cpu.cp15.write(opcode1, crn, crm, opcode2, cpu.r[rd]);
+
+                {
+                    // OK so the idea is that I don't want to pass the coprocessor a reference to the CPU,
+                    // so there's some side effects that we need to deal with. Right now I think I'll just process
+                    // all side affects on every MCR write and hope this isn't too awful
+                    // TODO: there has to be a better way.....
+
+                    // ICTM / DTCM Stuff
+                    const ctrl: cp15.Control = @bitCast(cpu.cp15.read(0, 1, 0, 0));
+                    cpu.dtcm.enabled = ctrl.dtcm_enable.read();
+                    cpu.dtcm.load_mode = ctrl.dtcm_load_mode.read();
+
+                    cpu.itcm.enabled = ctrl.itcm_enable.read();
+                    cpu.itcm.load_mode = ctrl.itcm_load_mode.read();
+
+                    const dtcm_size_base = cpu.cp15.read(0, 9, 1, 0); // mrc 0, c9, c1, 0
+                    const itcm_size_base = cpu.cp15.read(0, 9, 1, 1); // mrc 0, c9, c1, 1
+
+                    cpu.dtcm.base_address = dtcm_size_base & 0xFFFF_F000;
+                    cpu.dtcm.virt.size = @as(u32, 0x200) << @truncate(std.math.clamp(dtcm_size_base >> 1 & 0x1F, 3, 23));
+                    cpu.dtcm.virt.mask = std.math.clamp(cpu.dtcm.virt.size, 0, @as(u32, @intCast(cpu.dtcm.buf.len))) - 1;
+
+                    cpu.itcm.virt.size = @as(u32, 0x200) << @truncate(std.math.clamp(itcm_size_base >> 1 & 0x1F, 3, 23));
+                    cpu.itcm.virt.mask = std.math.clamp(cpu.itcm.virt.size, 0, @as(u32, @intCast(cpu.itcm.buf.len))) - 1;
+                }
+            }
+        }
+    }.inner;
+}
+
+pub fn dataProcessing(comptime InstrFn: type, comptime opcode1: u4, comptime opcode2: u3) InstrFn {
+    _ = opcode2;
+    _ = opcode1;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            cpu.panic("TODO: handle 0x{X:0>8} which is a coprocessor data processing instr", .{opcode});
+        }
+    }.inner;
+}
+
+const cp15 = struct {
+    // Only the bits that are R/W on the NDS (for now)
+    const Control = extern union {
+        pu_enable: Bit(u32, 0),
+        unified_cache: Bit(u32, 2),
+        endian: Bit(u32, 7),
+        instruction_cache: Bit(u32, 12),
+        exception_vectors: Bit(u32, 13),
+        cache_replacement: Bit(u32, 14),
+        pre_armv5_mode: Bit(u32, 15),
+        dtcm_enable: Bit(u32, 16),
+        dtcm_load_mode: Bit(u32, 17),
+        itcm_enable: Bit(u32, 18),
+        itcm_load_mode: Bit(u32, 19),
+
+        raw: u32,
+    };
+};

src/arm/cpu/arm/data_processing.zig

@@ -0,0 +1,181 @@
+const exec = @import("../barrel_shifter.zig").exec;
+const ror = @import("../barrel_shifter.zig").ror;
+
+pub fn dataProcessing(comptime InstrFn: type, comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const rd: u4 = @truncate(opcode >> 12 & 0xF);
+            const rn = opcode >> 16 & 0xF;
+            const old_carry = @intFromBool(cpu.cpsr.c.read());
+
+            // If certain conditions are met, PC is 12 ahead instead of 8
+            // TODO: Why these conditions?
+            if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
+            const op1 = cpu.r[rn];
+
+            const amount: u8 = @truncate((opcode >> 8 & 0xF) << 1);
+            const op2 = if (I) ror(S, &cpu.cpsr, opcode & 0xFF, amount) else exec(S, cpu, opcode);
+
+            // Undo special condition from above
+            if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
+
+            var result: u32 = undefined;
+            var overflow: u1 = undefined;
+
+            // Perform Data Processing Logic
+            switch (kind) {
+                0x0 => result = op1 & op2, // AND
+                0x1 => result = op1 ^ op2, // EOR
+                0x2 => result = op1 -% op2, // SUB
+                0x3 => result = op2 -% op1, // RSB
+                0x4 => result = add(&overflow, op1, op2), // ADD
+                0x5 => result = adc(&overflow, op1, op2, old_carry), // ADC
+                0x6 => result = sbc(op1, op2, old_carry), // SBC
+                0x7 => result = sbc(op2, op1, old_carry), // RSC
+                0x8 => {
+                    // TST
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    result = op1 & op2;
+                },
+                0x9 => {
+                    // TEQ
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    result = op1 ^ op2;
+                },
+                0xA => {
+                    // CMP
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    result = op1 -% op2;
+                },
+                0xB => {
+                    // CMN
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    const tmp = @addWithOverflow(op1, op2);
+                    result = tmp[0];
+                    overflow = tmp[1];
+                },
+                0xC => result = op1 | op2, // ORR
+                0xD => result = op2, // MOV
+                0xE => result = op1 & ~op2, // BIC
+                0xF => result = ~op2, // MVN
+            }
+
+            // Write to Destination Register
+            switch (kind) {
+                0x8, 0x9, 0xA, 0xB => {}, // Test Operations
+                else => {
+                    cpu.r[rd] = result;
+                    if (rd == 0xF) {
+                        if (S) cpu.setCpsr(cpu.spsr.raw);
+                        cpu.pipe.reload(cpu);
+                    }
+                },
+            }
+
+            // Write Flags
+            switch (kind) {
+                0x0, 0x1, 0xC, 0xD, 0xE, 0xF => if (S and rd != 0xF) {
+                    // Logic Operation Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // C set by Barrel Shifter, V is unaffected
+
+                },
+                0x2, 0x3 => if (S and rd != 0xF) {
+                    // SUB, RSB Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0x2) {
+                        // SUB specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // RSB Specific
+                        cpu.cpsr.c.write(op1 <= op2);
+                        cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
+                0x4, 0x5 => if (S and rd != 0xF) {
+                    // ADD, ADC Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(overflow == 0b1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0x6, 0x7 => if (S and rd != 0xF) {
+                    // SBC, RSC Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0x6) {
+                        // SBC specific
+                        const subtrahend = @as(u64, op2) -% old_carry +% 1;
+                        cpu.cpsr.c.write(subtrahend <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // RSC Specific
+                        const subtrahend = @as(u64, op1) -% old_carry +% 1;
+                        cpu.cpsr.c.write(subtrahend <= op2);
+                        cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
+                0x8, 0x9, 0xA, 0xB => {
+                    // Test Operation Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0xA) {
+                        // CMP specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else if (kind == 0xB) {
+                        // CMN specific
+                        cpu.cpsr.c.write(overflow == 0b1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // TST, TEQ specific
+                        // Barrel Shifter should always calc CPSR C in TST
+                        if (!S) _ = exec(true, cpu, opcode);
+                    }
+                },
+            }
+        }
+
+        fn undefinedTestBehaviour(cpu: *Arm32) void {
+            @setCold(true);
+            cpu.setCpsr(cpu.spsr.raw);
+        }
+    }.inner;
+}
+
+pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
+    // TODO: Make your own version (thanks peach.bot)
+    const subtrahend = @as(u64, right) -% old_carry +% 1;
+    return @truncate(left -% subtrahend);
+}
+
+pub fn add(overflow: *u1, left: u32, right: u32) u32 {
+    const ret = @addWithOverflow(left, right);
+    overflow.* = ret[1];
+
+    return ret[0];
+}
+
+pub fn adc(overflow: *u1, left: u32, right: u32, old_carry: u1) u32 {
+    const tmp = @addWithOverflow(left, right);
+    const ret = @addWithOverflow(tmp[0], old_carry);
+    overflow.* = tmp[1] | ret[1];
+
+    return ret[0];
+}

src/arm/cpu/arm/half_signed_data_transfer.zig

@@ -0,0 +1,117 @@
+const std = @import("std");
+const sext = @import("zba-util").sext;
+const rotr = @import("zba-util").rotr;
+
+const log = std.log.scoped(.half_and_signed_data_transfer);
+
+pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+            const rm = opcode & 0xF;
+            const imm_offset_high = opcode >> 8 & 0xF;
+
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
+            const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
+
+            const modified_base = if (U) base +% offset else base -% offset;
+            var address = if (P) modified_base else base;
+
+            const op: u2 = @truncate(opcode >> 5);
+            var result: u32 = undefined;
+
+            if (L) {
+                switch (op) {
+                    0b01 => {
+                        // LDRH
+                        result = switch (Arm32.arch) {
+                            .v4t => rotr(u32, cpu.read(u16, address), 8 * (address & 1)),
+                            .v5te => cpu.read(u16, address),
+                        };
+                    },
+                    0b10 => {
+                        // LDRSB
+                        result = sext(u32, u8, cpu.read(u8, address));
+                    },
+                    0b11 => {
+                        // LDRSH
+                        result = switch (Arm32.arch) {
+                            .v4t => blk: {
+                                const value = cpu.read(u16, address);
+
+                                break :blk switch (address & 1 == 1) {
+                                    true => sext(u32, u8, @as(u8, @truncate(value >> 8))),
+                                    false => sext(u32, u16, value),
+                                };
+                            },
+                            .v5te => sext(u32, u16, cpu.read(u16, address)),
+                        };
+                    },
+                    0b00 => unreachable,
+                }
+            } else {
+                switch (op) {
+                    0b00 => {
+                        const B = I;
+                        const swap_addr = cpu.r[rn];
+
+                        if (B) {
+                            // SWPB
+                            const value = cpu.read(u8, swap_addr);
+                            cpu.write(u8, swap_addr, @as(u8, @truncate(cpu.r[rm])));
+
+                            cpu.r[rd] = value;
+                        } else {
+                            // SWP
+                            const value = rotr(u32, cpu.read(u32, swap_addr), 8 * (swap_addr & 0x3));
+                            cpu.write(u32, swap_addr, cpu.r[rm]);
+
+                            cpu.r[rd] = value;
+                        }
+                    },
+                    0b01 => {
+                        // STRH
+
+                        // FIXME: I shouldn't have to use @as(u16, ...) here
+                        cpu.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
+                    },
+                    0b10 => blk: {
+                        // LDRD
+                        if (Arm32.arch == .v4t) break :blk;
+                        if (rd & 0 != 0) cpu.panic("LDRD: UNDEFINED behaviour when Rd is not even", .{});
+                        if (rd == 0xE) cpu.panic("LDRD: UNPREDICTABLE behaviour when rd == 14", .{});
+                        if (address & 0x7 != 0b000) cpu.panic("LDRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
+
+                        // Why do we not make use of result here?
+                        //
+                        // It's because L is not set so there's no chance of writing an undefined
+                        // value to the register
+                        //
+                        // despite this reason, this is bad design imo
+                        // TODO: Refactor this handler
+
+                        cpu.r[rd] = cpu.read(u32, address);
+                        cpu.r[rd + 1] = cpu.read(u32, address + 4);
+                    },
+                    0b11 => {
+                        // STRD
+                        if (Arm32.arch != .v5te) cpu.panic("STRD: unsupported on arm{s}", .{@tagName(Arm32.arch)});
+                        if (rd & 0 != 0) cpu.panic("STRD: UNDEFINED behaviour when Rd is not even", .{});
+                        if (rd == 0xE) cpu.panic("STRD: UNPREDICTABLE behaviour when rd == 14", .{});
+                        if (address & 0x7 != 0b000) cpu.panic("STRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
+
+                        cpu.write(u32, address, cpu.r[rd]);
+                        cpu.write(u32, address + 4, cpu.r[rd + 1]);
+                    },
+                }
+            }
+
+            address = modified_base;
+            if (W and P or !P) cpu.r[rn] = address;
+            if (L) cpu.r[rd] = result; // // This emulates the LDR rd == rn behaviour
+        }
+    }.inner;
+}

src/arm/cpu/arm/multiply.zig

@@ -0,0 +1,49 @@
+pub fn multiply(comptime InstrFn: type, comptime L: bool, comptime U: bool, comptime A: bool, comptime S: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const rd = opcode >> 16 & 0xF;
+            const rn = opcode >> 12 & 0xF;
+            const rs = opcode >> 8 & 0xF;
+            const rm = opcode & 0xF;
+
+            if (L) {
+                const rd_hi = rd;
+                const rd_lo = rn;
+
+                if (U) {
+                    // Signed (WHY IS IT U THEN?)
+                    var result: i64 = @as(i64, @as(i32, @bitCast(cpu.r[rm]))) * @as(i64, @as(i32, @bitCast(cpu.r[rs])));
+                    if (A) result +%= @bitCast(@as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]));
+
+                    cpu.r[rd_hi] = @bitCast(@as(i32, @truncate(result >> 32)));
+                    cpu.r[rd_lo] = @bitCast(@as(i32, @truncate(result)));
+                } else {
+                    // Unsigned
+                    var result: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]);
+                    if (A) result +%= @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]);
+
+                    cpu.r[rd_hi] = @truncate(result >> 32);
+                    cpu.r[rd_lo] = @truncate(result);
+                }
+
+                if (S) {
+                    cpu.cpsr.z.write(cpu.r[rd_hi] == 0 and cpu.r[rd_lo] == 0);
+                    cpu.cpsr.n.write(cpu.r[rd_hi] >> 31 & 1 == 1);
+                    // C and V are set to meaningless values
+                }
+            } else {
+                const temp: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]) + if (A) cpu.r[rn] else 0;
+                const result: u32 = @truncate(temp);
+                cpu.r[rd] = result;
+
+                if (S) {
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // V is unaffected, C is *actually* undefined in ARMv4
+                }
+            }
+        }
+    }.inner;
+}

src/arm/cpu/arm/psr_transfer.zig

@@ -0,0 +1,207 @@
+const std = @import("std");
+
+const PSR = @import("../../../arm.zig").PSR;
+const rotr = @import("zba-util").rotr;
+
+const log = std.log.scoped(.ctrl_ext_space);
+
+pub fn control(comptime InstrFn: type, comptime I: bool, comptime op: u6) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            if (I) {
+                // MSR Immediate
+                const R = op >> 5 & 1 == 1;
+                return msr(R, I, cpu, opcode);
+            }
+
+            switch (op) {
+                0b00_0000, 0b10_0000 => { // MRS
+                    const R = op >> 5 & 1 == 1;
+                    const rd = opcode >> 12 & 0xF;
+
+                    if (R and !cpu.hasSPSR()) log.err("Tried to read SPSR from User/System Mode", .{});
+                    cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw;
+                },
+                0b01_0000, 0b11_0000 => { // MSR (register)
+                    const R = op >> 5 & 1 == 1;
+                    msr(R, false, cpu, opcode);
+                },
+                0b01_0001 => cpu.panic("TODO: implement v5TE BX", .{}),
+                0b11_0001 => { // CLZ
+                    if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap();
+                    const rd = opcode >> 12 & 0xF;
+                    const rm = opcode & 0xF;
+
+                    if (rd == 0xF) cpu.panic("CLZ: UNPREDICTABLE behaviour when rd == 15", .{});
+                    if (rm == 0xF) cpu.panic("CLZ: UNPREDICTABLE behaviour when rm == 15", .{});
+
+                    cpu.r[rd] = @clz(cpu.r[rm]);
+                },
+                0b01_0011 => { // BLX
+                    const rm = opcode & 0xF;
+
+                    const thumb = cpu.r[rm] & 1 == 1;
+                    cpu.r[14] = cpu.r[15] - 4; // TODO: Why - 4?
+
+                    cpu.r[15] = cpu.r[rm] & ~@as(u32, 1);
+                    cpu.cpsr.t.write(thumb);
+
+                    cpu.pipe.reload(cpu);
+                },
+                0b00_0101, 0b01_0101, 0b10_0101, 0b11_0101 => { // QADD / QDADD / QSUB / QDSUB
+                    if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap();
+                    const U = op >> 4 & 1 == 1;
+                    const D = op >> 5 & 1 == 1;
+
+                    const rm = opcode & 0xF;
+                    const rd = opcode >> 12 & 0xF;
+                    const rn = opcode >> 16 & 0xF;
+
+                    const left: i32 = @bitCast(cpu.r[rm]);
+                    const right: i32 = blk: {
+                        if (!D) break :blk @bitCast(cpu.r[rn]);
+
+                        const ret = @mulWithOverflow(@as(i32, @bitCast(cpu.r[rn])), 2);
+                        var product: i32 = ret[0];
+
+                        if (ret[1] == 0b1) {
+                            product = if (product < 0) std.math.maxInt(i32) else std.math.minInt(i32);
+                            cpu.cpsr.q.set();
+                        }
+
+                        break :blk product;
+                    };
+
+                    const ret = if (U) @subWithOverflow(left, right) else @addWithOverflow(left, right);
+                    var result: i32 = ret[0];
+
+                    if (ret[1] == 0b1) {
+                        result = if (result < 0) std.math.maxInt(i32) else std.math.minInt(i32);
+                        cpu.cpsr.q.set();
+                    }
+
+                    cpu.r[rd] = @bitCast(result);
+                },
+                0b01_0111 => cpu.panic("TODO: handle BKPT", .{}),
+                0b00_1000, 0b00_1010, 0b00_1100, 0b00_1110 => { // SMLA<x><y>
+                    if (Arm32.arch == .v4t) return; // no-op
+                    const X = op >> 1 & 1;
+                    const Y = op >> 2 & 1;
+
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rn = opcode >> 12 & 0xF;
+                    const rd = opcode >> 16 & 0xF;
+
+                    const left: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rm] >> 16 * X))));
+                    const right: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+                    const accumulate: i32 = @bitCast(cpu.r[rn]);
+
+                    const result = @addWithOverflow(left * right, accumulate);
+                    cpu.r[rd] = @bitCast(result[0]);
+
+                    if (result[1] == 0b1) cpu.cpsr.q.set();
+                },
+
+                0b10_1000, 0b10_1010, 0b10_1100, 0b10_1110 => { // SMLAL<x><y>
+                    const X = op >> 1 & 1;
+                    const Y = op >> 2 & 1;
+
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rdlo = opcode >> 12 & 0xF;
+                    const rdhi = opcode >> 16 & 0xF;
+
+                    const left: i64 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rm] >> 16 * X))));
+                    const right: i64 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+                    const product = left * right;
+
+                    const rdhi_val: i32 = @bitCast(cpu.r[rdhi]);
+                    const rdlo_val: i32 = @bitCast(cpu.r[rdlo]);
+
+                    const accumulate = @as(i64, rdhi_val) << 32 | rdlo_val;
+                    const sum = product +% accumulate;
+
+                    cpu.r[rdhi] = @bitCast(@as(i32, @truncate(sum >> 32)));
+                    cpu.r[rdlo] = @bitCast(@as(i32, @truncate(sum)));
+                },
+                0b01_1000, 0b01_1100 => { // SMLAW<y>
+                    const Y = op >> 2 & 1;
+
+                    // TODO: deduplicate all this
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rn = opcode >> 12 & 0xF;
+                    const rd = opcode >> 16 & 0xF;
+
+                    const right: i16 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+                    const left: i48 = @as(i32, @bitCast(cpu.r[rm]));
+                    const accumulate: i32 = @bitCast(cpu.r[rn]);
+
+                    const ret = @addWithOverflow(@as(i32, @truncate((left * right) >> 16)), accumulate);
+
+                    cpu.r[rd] = @bitCast(ret[0]);
+                    if (ret[1] == 0b1) cpu.cpsr.q.set();
+                },
+
+                0b01_1010, 0b01_1110 => { // SMULW<y>
+                    const Y = op >> 2 & 1;
+
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rd = opcode >> 16 & 0xF;
+
+                    const right: i64 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+                    const left: i64 = @as(i32, @bitCast(cpu.r[rm]));
+
+                    const product: i32 = @truncate((left * right) >> 16);
+                    cpu.r[rd] = @bitCast(product);
+                },
+                0b11_1000, 0b11_1010, 0b11_1100, 0b11_1110 => { // SMUL<x><y>
+                    const X = op >> 1 & 1;
+                    const Y = op >> 2 & 1;
+
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rd = opcode >> 16 & 0xF;
+
+                    const left: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rm] >> 16 * X))));
+                    const right: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+
+                    cpu.r[rd] = @bitCast(left *% right);
+                },
+                else => cpu.panic("0x{X:0>8} was improperly handled by the control instruction extension space", .{opcode}),
+            }
+        }
+
+        inline fn msr(comptime R: bool, comptime imm: bool, cpu: *Arm32, opcode: u32) void {
+            const field_mask: u4 = @truncate(opcode >> 16 & 0xF);
+            const rm_idx = opcode & 0xF;
+            const right = if (imm) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) * 2) else cpu.r[rm_idx];
+
+            if (R and !cpu.hasSPSR()) log.err("Tried to write to SPSR in User/System Mode", .{});
+
+            if (R) {
+                // arm.gba seems to expect the SPSR to do somethign in SYS mode,
+                // so we just assume that despite writing to the SPSR in USR or SYS mode
+                // being UNPREDICTABLE, it just magically has a working SPSR somehow
+                cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);
+            } else {
+                if (cpu.isPrivileged()) cpu.setCpsr(fieldMask(&cpu.cpsr, field_mask, right));
+            }
+        }
+    }.inner;
+}
+
+fn fieldMask(psr: *const PSR, field_mask: u4, right: u32) u32 {
+    var mask: u32 = 0;
+
+    inline for (0..4) |i| {
+        if (field_mask & @as(u4, 1) << i != 0)
+            mask |= @as(u32, 0xFF) << 8 * i;
+    }
+
+    return (psr.raw & ~mask) | (right & mask);
+}

src/arm/cpu/arm/single_data_transfer.zig

@@ -0,0 +1,64 @@
+const shifter = @import("../barrel_shifter.zig");
+
+const rotr = @import("zba-util").rotr;
+
+pub fn singleDataTransfer(comptime InstrFn: type, comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+
+            const base = cpu.r[rn];
+            const offset = if (I) shifter.immediate(false, cpu, opcode) else opcode & 0xFFF;
+
+            const modified_base = if (U) base +% offset else base -% offset;
+            var address = if (P) modified_base else base;
+
+            var result: u32 = undefined;
+            if (L) {
+                if (B) {
+                    // LDRB
+                    result = cpu.read(u8, address);
+                } else {
+                    // LDR
+                    const value = cpu.read(u32, address);
+                    result = rotr(u32, value, 8 * (address & 0x3));
+                }
+            } else {
+                if (B) {
+                    // STRB
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
+
+                    // FIXME: I shouldn't have to use @as(u8, ...) here
+                    cpu.write(u8, address, @as(u8, @truncate(value)));
+                } else {
+                    // STR
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);
+                    cpu.write(u32, address, value);
+                }
+            }
+
+            address = modified_base;
+            if (W and P or !P) {
+                cpu.r[rn] = address;
+                if (rn == 0xF) cpu.pipe.reload(cpu);
+            }
+
+            if (L) {
+                // This emulates the LDR rd == rn behaviour
+                cpu.r[rd] = result;
+
+                if (rd == 0xF) {
+                    if (Arm32.arch == .v5te) {
+                        cpu.r[rd] &= ~@as(u32, 1);
+                        cpu.cpsr.t.write(result & 1 == 1);
+                    }
+
+                    cpu.pipe.reload(cpu);
+                }
+            }
+        }
+    }.inner;
+}

src/arm/cpu/arm/software_interrupt.zig

@@ -0,0 +1,27 @@
+pub fn armSoftwareInterrupt(comptime InstrFn: type) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, _: u32) void {
+            // Copy Values from Current Mode
+            const ret_addr = cpu.r[15] - 4;
+            const cpsr = cpu.cpsr.raw;
+
+            // Switch Mode
+            cpu.changeMode(.Supervisor);
+            cpu.cpsr.t.write(false); // Force ARM Mode
+            cpu.cpsr.i.write(true); // Disable normal interrupts
+
+            cpu.r[14] = ret_addr; // Resume Execution
+            cpu.spsr.raw = cpsr; // Previous mode CPSR
+            cpu.r[15] = switch (Arm32.arch) {
+                .v4t => 0x0000_0008,
+                .v5te => blk: {
+                    const ctrl = cpu.cp15.read(0, 1, 0, 0);
+                    break :blk if (ctrl >> 13 & 1 == 1) 0xFFFF_0008 else 0x0000_0008;
+                },
+            };
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}

src/arm/cpu/barrel_shifter.zig

@@ -0,0 +1,147 @@
+const CPSR = @import("../../arm.zig").PSR;
+
+const rotr = @import("zba-util").rotr;
+
+pub fn exec(comptime S: bool, cpu: anytype, opcode: u32) u32 {
+    var result: u32 = undefined;
+    if (opcode >> 4 & 1 == 1) {
+        result = register(S, cpu, opcode);
+    } else {
+        result = immediate(S, cpu, opcode);
+    }
+
+    return result;
+}
+
+fn register(comptime S: bool, cpu: anytype, opcode: u32) u32 {
+    const rs_idx = opcode >> 8 & 0xF;
+    const rm = cpu.r[opcode & 0xF];
+    const rs: u8 = @truncate(cpu.r[rs_idx]);
+
+    return switch (@as(u2, @truncate(opcode >> 5))) {
+        0b00 => lsl(S, &cpu.cpsr, rm, rs),
+        0b01 => lsr(S, &cpu.cpsr, rm, rs),
+        0b10 => asr(S, &cpu.cpsr, rm, rs),
+        0b11 => ror(S, &cpu.cpsr, rm, rs),
+    };
+}
+
+pub fn immediate(comptime S: bool, cpu: anytype, opcode: u32) u32 {
+    const amount: u8 = @truncate(opcode >> 7 & 0x1F);
+    const rm = cpu.r[opcode & 0xF];
+
+    // FIXME: I don't think result needs to be mutable here
+    var result: u32 = undefined;
+    if (amount == 0) {
+        switch (@as(u2, @truncate(opcode >> 5))) {
+            0b00 => {
+                // LSL #0
+                result = rm;
+            },
+            0b01 => {
+                // LSR #0 aka LSR #32
+                if (S) cpu.cpsr.c.write(rm >> 31 & 1 == 1);
+                result = 0x0000_0000;
+            },
+            0b10 => {
+                // ASR #0 aka ASR #32
+                result = @bitCast(@as(i32, @bitCast(rm)) >> 31);
+                if (S) cpu.cpsr.c.write(result >> 31 & 1 == 1);
+            },
+            0b11 => {
+                // ROR #0 aka RRX
+                const carry: u32 = @intFromBool(cpu.cpsr.c.read());
+                if (S) cpu.cpsr.c.write(rm & 1 == 1);
+
+                result = (carry << 31) | (rm >> 1);
+            },
+        }
+    } else {
+        switch (@as(u2, @truncate(opcode >> 5))) {
+            0b00 => result = lsl(S, &cpu.cpsr, rm, amount),
+            0b01 => result = lsr(S, &cpu.cpsr, rm, amount),
+            0b10 => result = asr(S, &cpu.cpsr, rm, amount),
+            0b11 => result = ror(S, &cpu.cpsr, rm, amount),
+        }
+    }
+
+    return result;
+}
+
+pub fn lsl(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
+    const amount: u5 = @truncate(total_amount);
+    const bit_count: u8 = @typeInfo(u32).Int.bits;
+
+    var result: u32 = 0x0000_0000;
+    if (total_amount < bit_count) {
+        // We can perform a well-defined shift here
+        result = rm << amount;
+
+        if (S and total_amount != 0) {
+            const carry_bit: u5 = @truncate(bit_count - amount);
+            cpsr.c.write(rm >> carry_bit & 1 == 1);
+        }
+    } else {
+        if (S) {
+            if (total_amount == bit_count) {
+                // Shifted all bits out, carry bit is bit 0 of rm
+                cpsr.c.write(rm & 1 == 1);
+            } else {
+                cpsr.c.write(false);
+            }
+        }
+    }
+
+    return result;
+}
+
+pub fn lsr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 {
+    const amount: u5 = @truncate(total_amount);
+    const bit_count: u8 = @typeInfo(u32).Int.bits;
+
+    var result: u32 = 0x0000_0000;
+    if (total_amount < bit_count) {
+        // We can perform a well-defined shift
+        result = rm >> amount;
+        if (S and total_amount != 0) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
+    } else {
+        if (S) {
+            if (total_amount == bit_count) {
+                // LSR #32
+                cpsr.c.write(rm >> 31 & 1 == 1);
+            } else {
+                // All bits have been shifted out, including carry bit
+                cpsr.c.write(false);
+            }
+        }
+    }
+
+    return result;
+}
+
+pub fn asr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
+    const amount: u5 = @truncate(total_amount);
+    const bit_count: u8 = @typeInfo(u32).Int.bits;
+
+    var result: u32 = 0x0000_0000;
+    if (total_amount < bit_count) {
+        result = @bitCast(@as(i32, @bitCast(rm)) >> amount);
+        if (S and total_amount != 0) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
+    } else {
+        // ASR #32 and ASR #>32 have the same result
+        result = @bitCast(@as(i32, @bitCast(rm)) >> 31);
+        if (S) cpsr.c.write(result >> 31 & 1 == 1);
+    }
+
+    return result;
+}
+
+pub fn ror(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
+    const result = rotr(u32, rm, total_amount);
+
+    if (S and total_amount != 0) {
+        cpsr.c.write(result >> 31 & 1 == 1);
+    }
+
+    return result;
+}

src/arm/cpu/thumb/alu.zig

@@ -0,0 +1,106 @@
+const adc = @import("../arm/data_processing.zig").adc;
+const sbc = @import("../arm/data_processing.zig").sbc;
+
+const lsl = @import("../barrel_shifter.zig").lsl;
+const lsr = @import("../barrel_shifter.zig").lsr;
+const asr = @import("../barrel_shifter.zig").asr;
+const ror = @import("../barrel_shifter.zig").ror;
+
+pub fn fmt4(comptime InstrFn: type, comptime op: u4) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const rs = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+            const carry = @intFromBool(cpu.cpsr.c.read());
+
+            const op1 = cpu.r[rd];
+            const op2 = cpu.r[rs];
+
+            var result: u32 = undefined;
+            var overflow: u1 = undefined;
+
+            switch (op) {
+                0x0 => result = op1 & op2, // AND
+                0x1 => result = op1 ^ op2, // EOR
+                0x2 => result = lsl(true, &cpu.cpsr, op1, @truncate(op2)), // LSL
+                0x3 => result = lsr(true, &cpu.cpsr, op1, @truncate(op2)), // LSR
+                0x4 => result = asr(true, &cpu.cpsr, op1, @truncate(op2)), // ASR
+                0x5 => result = adc(&overflow, op1, op2, carry), // ADC
+                0x6 => result = sbc(op1, op2, carry), // SBC
+                0x7 => result = ror(true, &cpu.cpsr, op1, @truncate(op2)), // ROR
+                0x8 => result = op1 & op2, // TST
+                0x9 => result = 0 -% op2, // NEG
+                0xA => result = op1 -% op2, // CMP
+                0xB => {
+                    // CMN
+                    const tmp = @addWithOverflow(op1, op2);
+                    result = tmp[0];
+                    overflow = tmp[1];
+                },
+                0xC => result = op1 | op2, // ORR
+                0xD => result = @truncate(@as(u64, op2) * @as(u64, op1)),
+                0xE => result = op1 & ~op2,
+                0xF => result = ~op2,
+            }
+
+            // Write to Destination Register
+            switch (op) {
+                0x8, 0xA, 0xB => {},
+                else => cpu.r[rd] = result,
+            }
+
+            // Write Flags
+            switch (op) {
+                0x0, 0x1, 0x2, 0x3, 0x4, 0x7, 0xC, 0xE, 0xF => {
+                    // Logic Operations
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // C set by Barrel Shifter, V is unaffected
+                },
+                0x8, 0xA => {
+                    // Test Flags
+                    // CMN (0xB) is handled with ADC
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (op == 0xA) {
+                        // CMP specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
+                0x5, 0xB => {
+                    // ADC, CMN
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(overflow == 0b1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0x6 => {
+                    // SBC
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    const subtrahend = @as(u64, op2) -% carry +% 1;
+                    cpu.cpsr.c.write(subtrahend <= op1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0x9 => {
+                    // NEG
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(op2 <= 0);
+                    cpu.cpsr.v.write(((0 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0xD => {
+                    // Multiplication
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // V is unaffected, assuming similar behaviour to ARMv4 MUL C is undefined
+                },
+            }
+        }
+    }.inner;
+}

src/arm/cpu/thumb/block_data_transfer.zig

@@ -0,0 +1,102 @@
+pub fn fmt14(comptime InstrFn: type, comptime L: bool, comptime R: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const count = @intFromBool(R) + countRlist(opcode);
+            const start = cpu.r[13] - if (!L) count * 4 else 0;
+
+            var end = cpu.r[13];
+            if (L) {
+                end += count * 4;
+            } else {
+                end -= 4;
+            }
+
+            var address = start;
+
+            var i: u4 = 0;
+            while (i < 8) : (i += 1) {
+                if (opcode >> i & 1 == 1) {
+                    if (L) {
+                        cpu.r[i] = cpu.read(u32, address);
+                    } else {
+                        cpu.write(u32, address, cpu.r[i]);
+                    }
+
+                    address += 4;
+                }
+            }
+
+            if (R) {
+                if (L) {
+                    const value = cpu.read(u32, address);
+                    cpu.r[15] = value & ~@as(u32, 1);
+
+                    if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
+                    cpu.pipe.reload(cpu);
+                } else {
+                    cpu.write(u32, address, cpu.r[14]);
+                }
+                address += 4;
+            }
+
+            cpu.r[13] = if (L) end else start;
+        }
+    }.inner;
+}
+
+pub fn fmt15(comptime InstrFn: type, comptime L: bool, comptime rb: u3) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            var address = cpu.r[rb];
+            const end_address = cpu.r[rb] + 4 * countRlist(opcode);
+
+            if (opcode & 0xFF == 0) {
+                if (L) {
+                    cpu.r[15] = cpu.read(u32, address);
+                    cpu.pipe.reload(cpu);
+                } else {
+                    cpu.write(u32, address, cpu.r[15] + 2);
+                }
+
+                cpu.r[rb] += 0x40;
+                return;
+            }
+
+            var i: u4 = 0;
+            var first_write = true;
+
+            while (i < 8) : (i += 1) {
+                if (opcode >> i & 1 == 1) {
+                    if (L) {
+                        cpu.r[i] = cpu.read(u32, address);
+                    } else {
+                        cpu.write(u32, address, cpu.r[i]);
+                    }
+
+                    if (!L and first_write) {
+                        cpu.r[rb] = end_address;
+                        first_write = false;
+                    }
+
+                    address += 4;
+                }
+            }
+
+            if (L and opcode >> rb & 1 != 1) cpu.r[rb] = address;
+        }
+    }.inner;
+}
+
+inline fn countRlist(opcode: u16) u32 {
+    var count: u32 = 0;
+
+    inline for (0..8) |i| {
+        if (opcode >> (7 - i) & 1 == 1) count += 1;
+    }
+
+    return count;
+}

src/arm/cpu/thumb/branch.zig

@@ -0,0 +1,54 @@
+const sext = @import("zba-util").sext;
+
+pub fn fmt16(comptime InstrFn: type, comptime cond: u4) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            // B
+            if (cond == 0xE or cond == 0xF)
+                cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
+
+            if (!cpu.cpsr.check(Arm32.arch, cond)) return;
+
+            cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}
+
+pub fn linkExchange(comptime InstrFn: type, comptime H: u2) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const offset = opcode & 0x7FF;
+
+            switch (H) {
+                0b00 => { // Unconditional Branch
+                    cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
+                    cpu.pipe.reload(cpu);
+                },
+                0b01 => { // BLX Pt. 2
+                    if (Arm32.arch == .v4t) cpu.panic("attempted to execute THUMB BLX(1), despite ARMv4T CPU", .{});
+                    const next_addr = cpu.r[15] - 2;
+
+                    cpu.r[15] = (cpu.r[14] +% (offset << 1)) & ~@as(u32, 0x3);
+                    cpu.r[14] = next_addr | 1;
+                    cpu.cpsr.t.unset();
+
+                    cpu.pipe.reload(cpu);
+                },
+                0b10 => cpu.r[14] = cpu.r[15] +% (sext(u32, u11, offset) << 12), // BL / BLX Pt. 1
+                0b11 => { // BL Pt. 2
+                    const next_addr = cpu.r[15] - 2;
+
+                    cpu.r[15] = cpu.r[14] +% (offset << 1);
+                    cpu.r[14] = next_addr | 1;
+
+                    cpu.pipe.reload(cpu);
+                },
+            }
+        }
+    }.inner;
+}

src/arm/cpu/thumb/data_processing.zig

@@ -0,0 +1,228 @@
+const add = @import("../arm/data_processing.zig").add;
+
+const lsl = @import("../barrel_shifter.zig").lsl;
+const lsr = @import("../barrel_shifter.zig").lsr;
+const asr = @import("../barrel_shifter.zig").asr;
+
+pub fn fmt1(comptime InstrFn: type, comptime op: u2, comptime offset: u5) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const rs = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            const result: u32 = switch (op) {
+                0b00 => blk: {
+                    // LSL
+                    if (offset == 0) {
+                        break :blk cpu.r[rs];
+                    } else {
+                        break :blk lsl(true, &cpu.cpsr, cpu.r[rs], offset);
+                    }
+                },
+                0b01 => blk: {
+                    // LSR
+                    if (offset == 0) {
+                        cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
+                        break :blk @as(u32, 0);
+                    } else {
+                        break :blk lsr(true, &cpu.cpsr, cpu.r[rs], offset);
+                    }
+                },
+                0b10 => blk: {
+                    // ASR
+                    if (offset == 0) {
+                        cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
+                        break :blk @bitCast(@as(i32, @bitCast(cpu.r[rs])) >> 31);
+                    } else {
+                        break :blk asr(true, &cpu.cpsr, cpu.r[rs], offset);
+                    }
+                },
+                else => cpu.panic("[CPU/THUMB.1] 0b{b:0>2} is not a valid op", .{op}),
+            };
+
+            // Equivalent to an ARM MOVS
+            cpu.r[rd] = result;
+
+            // Write Flags
+            cpu.cpsr.n.write(result >> 31 & 1 == 1);
+            cpu.cpsr.z.write(result == 0);
+        }
+    }.inner;
+}
+
+pub fn fmt5(comptime InstrFn: type, comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
+            const rd = @as(u4, h1) << 3 | (opcode & 0x7);
+
+            if (Arm32.arch == .v5te and op == 0b11 and h1 == 0b1) {
+                // BLX
+                const rm = rs;
+
+                cpu.r[14] = (cpu.r[15] - 2) | 1;
+                cpu.cpsr.t.write(cpu.r[rm] & 1 == 1);
+
+                cpu.r[15] = cpu.r[rm] & ~@as(u32, 1);
+                cpu.pipe.reload(cpu);
+            }
+
+            const op1 = cpu.r[rd];
+            const op2 = cpu.r[rs];
+
+            var result: u32 = undefined;
+            var overflow: u1 = undefined;
+            switch (op) {
+                0b00 => result = add(&overflow, op1, op2), // ADD
+                0b01 => result = op1 -% op2, // CMP
+                0b10 => result = op2, // MOV
+                0b11 => {},
+            }
+
+            // Write to Destination Register
+            switch (op) {
+                0b01 => {}, // Test Instruction
+                0b11 => {
+                    // BX
+                    const is_thumb = op2 & 1 == 1;
+                    cpu.r[15] = op2 & ~@as(u32, 1);
+
+                    cpu.cpsr.t.write(is_thumb);
+                    cpu.pipe.reload(cpu);
+                },
+                else => {
+                    cpu.r[rd] = result;
+                    if (rd == 0xF) {
+                        cpu.r[15] &= ~@as(u32, 1);
+                        cpu.pipe.reload(cpu);
+                    }
+                },
+            }
+
+            // Write Flags
+            switch (op) {
+                0b01 => {
+                    // CMP
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(op2 <= op1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0b00, 0b10, 0b11 => {}, // MOV and Branch Instruction
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt2(comptime InstrFn: type, comptime I: bool, is_sub: bool, rn: u3) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const rs = opcode >> 3 & 0x7;
+            const rd: u3 = @truncate(opcode);
+            const op1 = cpu.r[rs];
+            const op2: u32 = if (I) rn else cpu.r[rn];
+
+            if (is_sub) {
+                // SUB
+                const result = op1 -% op2;
+                cpu.r[rd] = result;
+
+                cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                cpu.cpsr.z.write(result == 0);
+                cpu.cpsr.c.write(op2 <= op1);
+                cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+            } else {
+                // ADD
+                var overflow: u1 = undefined;
+                const result = add(&overflow, op1, op2);
+                cpu.r[rd] = result;
+
+                cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                cpu.cpsr.z.write(result == 0);
+                cpu.cpsr.c.write(overflow == 0b1);
+                cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt3(comptime InstrFn: type, comptime op: u2, comptime rd: u3) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const op1 = cpu.r[rd];
+            const op2: u32 = opcode & 0xFF; // Offset
+
+            var overflow: u1 = undefined;
+            const result: u32 = switch (op) {
+                0b00 => op2, // MOV
+                0b01 => op1 -% op2, // CMP
+                0b10 => add(&overflow, op1, op2), // ADD
+                0b11 => op1 -% op2, // SUB
+            };
+
+            // Write to Register
+            if (op != 0b01) cpu.r[rd] = result;
+
+            // Write Flags
+            cpu.cpsr.n.write(result >> 31 & 1 == 1);
+            cpu.cpsr.z.write(result == 0);
+
+            switch (op) {
+                0b00 => {}, // MOV | C set by Barrel Shifter, V is unaffected
+                0b01, 0b11 => {
+                    // SUB, CMP
+                    cpu.cpsr.c.write(op2 <= op1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0b10 => {
+                    // ADD
+                    cpu.cpsr.c.write(overflow == 0b1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                },
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt12(comptime InstrFn: type, comptime isSP: bool, comptime rd: u3) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            // ADD
+            const left = if (isSP) cpu.r[13] else cpu.r[15] & ~@as(u32, 2);
+            const right = (opcode & 0xFF) << 2;
+            cpu.r[rd] = left + right;
+        }
+    }.inner;
+}
+
+pub fn fmt13(comptime InstrFn: type, comptime S: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            // ADD
+            const offset = (opcode & 0x7F) << 2;
+            cpu.r[13] = if (S) cpu.r[13] - offset else cpu.r[13] + offset;
+        }
+    }.inner;
+}
+
+pub fn bkpt(comptime InstrFn: type) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, _: u16) void {
+            cpu.panic("TODO: handle THUMB BKPT", .{});
+        }
+    }.inner;
+}

src/arm/cpu/thumb/data_transfer.zig

@@ -0,0 +1,172 @@
+const rotr = @import("zba-util").rotr;
+const sext = @import("zba-util").sext;
+
+pub fn fmt6(comptime InstrFn: type, comptime rd: u3) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            // LDR
+            const offset = (opcode & 0xFF) << 2;
+
+            // Bit 1 of the PC intentionally ignored
+            cpu.r[rd] = cpu.read(u32, (cpu.r[15] & ~@as(u32, 2)) + offset);
+        }
+    }.inner;
+}
+
+pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const ro = opcode >> 6 & 0x7;
+            const rb = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            const address = cpu.r[rb] +% cpu.r[ro];
+
+            if (T) {
+                // Format 8
+                switch (op) {
+                    0b00 => {
+                        // STRH
+
+                        // FIXME: I shouldn't have to use @as(u8, ...) here
+                        cpu.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
+                    },
+                    0b01 => {
+                        // LDSB
+                        cpu.r[rd] = sext(u32, u8, cpu.read(u8, address));
+                    },
+                    0b10 => {
+                        // LDRH
+                        cpu.r[rd] = switch (Arm32.arch) {
+                            .v4t => rotr(u32, cpu.read(u16, address), 8 * (address & 1)),
+                            .v5te => cpu.read(u16, address),
+                        };
+                    },
+                    0b11 => {
+                        // LDRSH
+                        cpu.r[rd] = switch (Arm32.arch) {
+                            .v4t => blk: {
+                                const value = cpu.read(u16, address);
+
+                                break :blk switch (address & 1 == 1) {
+                                    true => sext(u32, u8, @as(u8, @truncate(value >> 8))),
+                                    false => sext(u32, u16, value),
+                                };
+                            },
+                            .v5te => sext(u32, u16, cpu.read(u16, address)),
+                        };
+                    },
+                }
+            } else {
+                // Format 7
+                switch (op) {
+                    0b00 => {
+                        // STR
+                        cpu.write(u32, address, cpu.r[rd]);
+                    },
+                    0b01 => {
+                        // STRB
+
+                        // FIXME: I shouldn't have to use @as(u8, ...) here
+                        cpu.write(u8, address, @as(u8, @truncate(cpu.r[rd])));
+                    },
+                    0b10 => {
+                        // LDR
+                        const value = cpu.read(u32, address);
+                        cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
+                    },
+                    0b11 => {
+                        // LDRB
+                        cpu.r[rd] = cpu.read(u8, address);
+                    },
+                }
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt9(comptime InstrFn: type, comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const rb = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            if (L) {
+                if (B) {
+                    // LDRB
+                    const address = cpu.r[rb] + offset;
+                    cpu.r[rd] = cpu.read(u8, address);
+                } else {
+                    // LDR
+                    const address = cpu.r[rb] + (@as(u32, offset) << 2);
+                    const value = cpu.read(u32, address);
+                    cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
+                }
+            } else {
+                if (B) {
+                    // STRB
+                    const address = cpu.r[rb] + offset;
+
+                    // FIXME: I shouldn't have to use @as(u8, ...) here
+                    cpu.write(u8, address, @as(u8, @truncate(cpu.r[rd])));
+                } else {
+                    // STR
+                    const address = cpu.r[rb] + (@as(u32, offset) << 2);
+                    cpu.write(u32, address, cpu.r[rd]);
+                }
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt10(comptime InstrFn: type, comptime L: bool, comptime offset: u5) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const rb = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            const address = cpu.r[rb] + (@as(u6, offset) << 1);
+
+            if (L) {
+                // LDRH
+                cpu.r[rd] = switch (Arm32.arch) {
+                    .v4t => rotr(u32, cpu.read(u16, address), 8 * (address & 1)),
+                    .v5te => cpu.read(u16, address),
+                };
+            } else {
+                // STRH
+
+                // FIXME: I shouldn't have to use @as(u8, ...) here
+                cpu.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt11(comptime InstrFn: type, comptime L: bool, comptime rd: u3) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, opcode: u16) void {
+            const offset = (opcode & 0xFF) << 2;
+            const address = cpu.r[13] + offset;
+
+            if (L) {
+                // LDR
+                const value = cpu.read(u32, address);
+                cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
+            } else {
+                // STR
+                cpu.write(u32, address, cpu.r[rd]);
+            }
+        }
+    }.inner;
+}

src/arm/cpu/thumb/software_interrupt.zig

@@ -0,0 +1,27 @@
+pub fn fmt17(comptime InstrFn: type) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, _: u16) void {
+            // Copy Values from Current Mode
+            const ret_addr = cpu.r[15] - 2;
+            const cpsr = cpu.cpsr.raw;
+
+            // Switch Mode
+            cpu.changeMode(.Supervisor);
+            cpu.cpsr.t.write(false); // Force ARM Mode
+            cpu.cpsr.i.write(true); // Disable normal interrupts
+
+            cpu.r[14] = ret_addr; // Resume Execution
+            cpu.spsr.raw = cpsr; // Previous mode CPSR
+            cpu.r[15] = switch (Arm32.arch) {
+                .v4t => 0x0000_0008,
+                .v5te => blk: {
+                    const ctrl = cpu.cp15.read(0, 1, 0, 0);
+                    break :blk if (ctrl >> 13 & 1 == 1) 0xFFFF_0008 else 0x0000_0008;
+                },
+            };
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}

src/arm/v4t.zig

@@ -0,0 +1,242 @@
+const Arm7tdmi = @import("../arm.zig").Arm32(.v4t);
+
+pub const arm = struct {
+    pub const InstrFn = *const fn (*Arm7tdmi, u32) void;
+    pub const lut: [0x1000]InstrFn = populate();
+
+    const processing = @import("cpu/arm/data_processing.zig").dataProcessing;
+    const transfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
+    const blockTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
+    const branch = @import("cpu/arm/branch.zig").branch;
+    const branchExchange = @import("cpu/arm/branch.zig").branchAndExchange;
+    const swi = @import("cpu/arm/software_interrupt.zig").armSoftwareInterrupt;
+
+    /// Load Store Instruction Extention Space
+    const loadStoreExt = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
+
+    /// Control Instruction Extension Space
+    const controlExt = @import("cpu/arm/psr_transfer.zig").control;
+
+    /// Arithmetic Instruction Extension Space
+    const multiplyExt = @import("cpu/arm/multiply.zig").multiply;
+
+    const cop = @import("cpu/arm/coprocessor.zig");
+
+    /// Determine index into ARM InstrFn LUT
+    pub fn idx(opcode: u32) u12 {
+        // FIXME: omit these?
+        return @as(u12, @truncate(opcode >> 20 & 0xFF)) << 4 | @as(u12, @truncate(opcode >> 4 & 0xF));
+    }
+
+    // Undefined ARM Instruction handler
+    fn und(cpu: *Arm7tdmi, opcode: u32) void {
+        const id = idx(opcode);
+        cpu.panic("[CPU/Decode] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
+    }
+
+    fn populate() [0x1000]InstrFn {
+        return comptime comptime_blk: {
+            @setEvalBranchQuota(0xE000);
+            var table = [_]InstrFn{und} ** 0x1000;
+
+            for (&table, 0..) |*handler, i| {
+                handler.* = switch (@as(u2, i >> 10)) {
+                    0b00 => if (i == 0x121) blk: { // 12 bits
+                        break :blk branchExchange(InstrFn);
+                    } else if (i & 0xF0F == 0x009) blk: { // 8 bits
+                        const L = i >> 7 & 1 == 1;
+                        const U = i >> 6 & 1 == 1;
+                        const A = i >> 5 & 1 == 1;
+                        const S = i >> 4 & 1 == 1;
+                        break :blk multiplyExt(InstrFn, L, U, A, S);
+                    } else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: { // 6 bits
+                        const P = i >> 8 & 1 == 1;
+                        const U = i >> 7 & 1 == 1;
+                        const I = i >> 6 & 1 == 1;
+                        const W = i >> 5 & 1 == 1;
+                        const L = i >> 4 & 1 == 1;
+                        break :blk loadStoreExt(InstrFn, P, U, I, W, L);
+                    } else if (i & 0xD90 == 0x100) blk: { // 5 bits
+                        const I = i >> 9 & 1 == 1;
+                        const op = ((i >> 5) & 0x3) << 4 | (i & 0xF);
+                        break :blk controlExt(InstrFn, I, op);
+                    } else blk: {
+                        const I = i >> 9 & 1 == 1;
+                        const S = i >> 4 & 1 == 1;
+                        const instr_kind = i >> 5 & 0xF;
+                        break :blk processing(InstrFn, I, S, instr_kind);
+                    },
+                    0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) und else blk: {
+                        const I = i >> 9 & 1 == 1;
+                        const P = i >> 8 & 1 == 1;
+                        const U = i >> 7 & 1 == 1;
+                        const B = i >> 6 & 1 == 1;
+                        const W = i >> 5 & 1 == 1;
+                        const L = i >> 4 & 1 == 1;
+                        break :blk transfer(InstrFn, I, P, U, B, W, L);
+                    },
+                    else => switch (@as(u2, i >> 9 & 0x3)) {
+                        // MSB is guaranteed to be 1
+                        0b00 => blk: {
+                            const P = i >> 8 & 1 == 1;
+                            const U = i >> 7 & 1 == 1;
+                            const S = i >> 6 & 1 == 1;
+                            const W = i >> 5 & 1 == 1;
+                            const L = i >> 4 & 1 == 1;
+                            break :blk blockTransfer(InstrFn, P, U, S, W, L);
+                        },
+                        0b01 => blk: {
+                            const L = i >> 8 & 1 == 1;
+                            break :blk branch(InstrFn, L);
+                        },
+                        0b10 => blk: {
+                            const P = i >> 8 & 1 == 1;
+                            const U = i >> 7 & 1 == 1;
+                            const N = i >> 6 & 1 == 1;
+                            const W = i >> 5 & 1 == 1;
+                            const L = i >> 4 & 1 == 1;
+
+                            break :blk cop.dataTransfer(InstrFn, P, U, N, W, L);
+                        },
+                        0b11 => blk: {
+                            if (i >> 8 & 1 == 1) break :blk swi(InstrFn);
+
+                            const data_opcode1 = i >> 4 & 0xF; // bits 20 -> 23
+                            const reg_opcode1 = i >> 5 & 0x7; // bits 21 -> 23
+                            const opcode2 = i >> 1 & 0x7; // bits 5 -> 7
+                            const L = i >> 4 & 1 == 1; // bit 20
+
+                            // Bit 4 (index pos of 0) distinguishes between these classes of instructions
+                            break :blk switch (i & 1 == 1) {
+                                true => cop.registerTransfer(InstrFn, reg_opcode1, L, opcode2),
+                                false => cop.dataProcessing(InstrFn, data_opcode1, opcode2),
+                            };
+                        },
+                    },
+                };
+            }
+
+            break :comptime_blk table;
+        };
+    }
+};
+
+pub const thumb = struct {
+    pub const InstrFn = *const fn (*Arm7tdmi, u16) void;
+    pub const lut: [0x400]InstrFn = populate();
+
+    const processing = @import("cpu/thumb/data_processing.zig");
+    const alu = @import("cpu/thumb/alu.zig").fmt4;
+    const transfer = @import("cpu/thumb/data_transfer.zig");
+    const block_transfer = @import("cpu/thumb/block_data_transfer.zig");
+    const swi = @import("cpu/thumb/software_interrupt.zig").fmt17;
+    const branch = @import("cpu/thumb/branch.zig");
+
+    /// Determine index into THUMB InstrFn LUT
+    pub fn idx(opcode: u16) u10 {
+        return @truncate(opcode >> 6);
+    }
+
+    /// Undefined THUMB Instruction Handler
+    fn und(cpu: *Arm7tdmi, opcode: u16) void {
+        const id = idx(opcode);
+        cpu.panic("[CPU/Decode] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
+    }
+
+    fn populate() [0x400]InstrFn {
+        return comptime comptime_blk: {
+            @setEvalBranchQuota(5025); // This is exact
+            var table = [_]InstrFn{und} ** 0x400;
+
+            for (&table, 0..) |*handler, i| {
+                handler.* = switch (@as(u3, i >> 7 & 0x7)) {
+                    0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
+                        const I = i >> 4 & 1 == 1;
+                        const is_sub = i >> 3 & 1 == 1;
+                        const rn = i & 0x7;
+                        break :blk processing.fmt2(InstrFn, I, is_sub, rn);
+                    } else blk: {
+                        const op = i >> 5 & 0x3;
+                        const offset = i & 0x1F;
+                        break :blk processing.fmt1(InstrFn, op, offset);
+                    },
+                    0b001 => blk: {
+                        const op = i >> 5 & 0x3;
+                        const rd = i >> 2 & 0x7;
+                        break :blk processing.fmt3(InstrFn, op, rd);
+                    },
+                    0b010 => switch (@as(u2, i >> 5 & 0x3)) {
+                        0b00 => if (i >> 4 & 1 == 1) blk: {
+                            const op = i >> 2 & 0x3;
+                            const h1 = i >> 1 & 1;
+                            const h2 = i & 1;
+                            break :blk processing.fmt5(InstrFn, op, h1, h2);
+                        } else blk: {
+                            const op = i & 0xF;
+                            break :blk alu(InstrFn, op);
+                        },
+                        0b01 => blk: {
+                            const rd = i >> 2 & 0x7;
+                            break :blk transfer.fmt6(InstrFn, rd);
+                        },
+                        else => blk: {
+                            const op = i >> 4 & 0x3;
+                            const T = i >> 3 & 1 == 1;
+                            break :blk transfer.fmt78(InstrFn, op, T);
+                        },
+                    },
+                    0b011 => blk: {
+                        const B = i >> 6 & 1 == 1;
+                        const L = i >> 5 & 1 == 1;
+                        const offset = i & 0x1F;
+                        break :blk transfer.fmt9(InstrFn, B, L, offset);
+                    },
+                    else => switch (@as(u3, i >> 6 & 0x7)) {
+                        // MSB is guaranteed to be 1
+                        0b000 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const offset = i & 0x1F;
+                            break :blk transfer.fmt10(InstrFn, L, offset);
+                        },
+                        0b001 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const rd = i >> 2 & 0x7;
+                            break :blk transfer.fmt11(InstrFn, L, rd);
+                        },
+                        0b010 => blk: {
+                            const isSP = i >> 5 & 1 == 1;
+                            const rd = i >> 2 & 0x7;
+                            break :blk processing.fmt12(InstrFn, isSP, rd);
+                        },
+                        0b011 => if (i >> 4 & 1 == 1) blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const R = i >> 2 & 1 == 1;
+                            break :blk block_transfer.fmt14(InstrFn, L, R);
+                        } else blk: {
+                            const S = i >> 1 & 1 == 1;
+                            break :blk processing.fmt13(InstrFn, S);
+                        },
+                        0b100 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const rb = i >> 2 & 0x7;
+
+                            break :blk block_transfer.fmt15(InstrFn, L, rb);
+                        },
+                        0b101 => if (i >> 2 & 0xF == 0b1111) blk: {
+                            break :blk swi(InstrFn);
+                        } else blk: {
+                            const cond = i >> 2 & 0xF;
+                            break :blk branch.fmt16(InstrFn, cond);
+                        },
+                        0b110, 0b111 => blk: {
+                            const H = i >> 5 & 0x3;
+                            break :blk branch.linkExchange(InstrFn, H);
+                        },
+                    },
+                };
+            }
+
+            break :comptime_blk table;
+        };
+    }
+};

src/arm/v5te.zig

@@ -0,0 +1,251 @@
+const Arm946es = @import("../arm.zig").Arm32(.v5te);
+
+pub const arm = struct {
+    pub const InstrFn = *const fn (*Arm946es, u32) void;
+    pub const lut: [0x1000]InstrFn = populate();
+
+    const processing = @import("cpu/arm/data_processing.zig").dataProcessing;
+    const transfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
+    const blockTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
+    const branch = @import("cpu/arm/branch.zig").branch;
+    const branchExchange = @import("cpu/arm/branch.zig").branchAndExchange;
+    const swi = @import("cpu/arm/software_interrupt.zig").armSoftwareInterrupt;
+
+    /// Load Store Instruction Extention Space
+    const loadStoreExt = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
+
+    /// Control Instruction Extension Space
+    const controlExt = @import("cpu/arm/psr_transfer.zig").control;
+
+    /// Arithmetic Instruction Extension Space
+    const multiplyExt = @import("cpu/arm/multiply.zig").multiply;
+
+    const cop = @import("cpu/arm/coprocessor.zig");
+
+    /// Determine index into ARM InstrFn LUT
+    pub fn idx(opcode: u32) u12 {
+        // FIXME: omit these?
+        return @as(u12, @truncate(opcode >> 20 & 0xFF)) << 4 | @as(u12, @truncate(opcode >> 4 & 0xF));
+    }
+
+    // Undefined ARM Instruction handler
+    fn und(cpu: *Arm946es, opcode: u32) void {
+        const id = idx(opcode);
+        cpu.panic("[CPU/Decode] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
+    }
+
+    fn populate() [0x1000]InstrFn {
+        return comptime comptime_blk: {
+            @setEvalBranchQuota(0xE000);
+            var table = [_]InstrFn{und} ** 0x1000;
+            // op : 27 26 25 24 23 22 21 20 07 06 05 04
+            // idx: 11 10 09 08 07 06 05 04 03 02 01 00
+
+            for (&table, 0..) |*handler, i| {
+                handler.* = switch (@as(u2, i >> 10)) {
+                    0b00 => if (i == 0x121) blk: { // 12 bits
+                        break :blk branchExchange(InstrFn);
+                    } else if (i & 0xF0F == 0x009) blk: { // 8 bits
+                        const L = i >> 7 & 1 == 1;
+                        const U = i >> 6 & 1 == 1;
+                        const A = i >> 5 & 1 == 1;
+                        const S = i >> 4 & 1 == 1;
+                        break :blk multiplyExt(InstrFn, L, U, A, S);
+                    } else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: { // 6 bits
+                        const P = i >> 8 & 1 == 1;
+                        const U = i >> 7 & 1 == 1;
+                        const I = i >> 6 & 1 == 1;
+                        const W = i >> 5 & 1 == 1;
+                        const L = i >> 4 & 1 == 1;
+                        break :blk loadStoreExt(InstrFn, P, U, I, W, L);
+                    } else if (i & 0xD90 == 0x100) blk: { // 6 bits
+                        const I = i >> 9 & 1 == 1;
+                        const op = ((i >> 5) & 0x3) << 4 | (i & 0xF);
+                        break :blk controlExt(InstrFn, I, op);
+                    } else blk: {
+                        const I = i >> 9 & 1 == 1;
+                        const S = i >> 4 & 1 == 1;
+                        const instr_kind = i >> 5 & 0xF;
+                        break :blk processing(InstrFn, I, S, instr_kind);
+                    },
+                    0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) und else blk: {
+                        const I = i >> 9 & 1 == 1;
+                        const P = i >> 8 & 1 == 1;
+                        const U = i >> 7 & 1 == 1;
+                        const B = i >> 6 & 1 == 1;
+                        const W = i >> 5 & 1 == 1;
+                        const L = i >> 4 & 1 == 1;
+                        break :blk transfer(InstrFn, I, P, U, B, W, L);
+                    },
+                    else => switch (@as(u2, i >> 9 & 0x3)) {
+                        // MSB is guaranteed to be 1
+                        0b00 => blk: {
+                            const P = i >> 8 & 1 == 1;
+                            const U = i >> 7 & 1 == 1;
+                            const S = i >> 6 & 1 == 1;
+                            const W = i >> 5 & 1 == 1;
+                            const L = i >> 4 & 1 == 1;
+                            break :blk blockTransfer(InstrFn, P, U, S, W, L);
+                        },
+                        0b01 => blk: {
+                            const L = i >> 8 & 1 == 1;
+                            break :blk branch(InstrFn, L);
+                        },
+                        0b10 => blk: {
+                            const P = i >> 8 & 1 == 1;
+                            const U = i >> 7 & 1 == 1;
+                            const N = i >> 6 & 1 == 1;
+                            const W = i >> 5 & 1 == 1;
+                            const L = i >> 4 & 1 == 1;
+
+                            break :blk cop.dataTransfer(InstrFn, P, U, N, W, L);
+                        },
+                        0b11 => blk: {
+                            if (i >> 8 & 1 == 1) break :blk swi(InstrFn);
+
+                            const data_opcode1 = i >> 4 & 0xF; // bits 20 -> 23
+                            const reg_opcode1 = i >> 5 & 0x7; // bits 21 -> 23
+                            const opcode2 = i >> 1 & 0x7; // bits 5 -> 7
+                            const L = i >> 4 & 1 == 1; // bit 20
+
+                            // Bit 4 (index pos of 0) distinguishes between these classes of instructions
+                            break :blk switch (i & 1 == 1) {
+                                true => cop.registerTransfer(InstrFn, reg_opcode1, L, opcode2),
+                                false => cop.dataProcessing(InstrFn, data_opcode1, opcode2),
+                            };
+                        },
+                    },
+                };
+            }
+
+            break :comptime_blk table;
+        };
+    }
+};
+
+pub const thumb = struct {
+    pub const InstrFn = *const fn (*Arm946es, u16) void;
+    pub const lut: [0x400]InstrFn = populate();
+
+    const processing = @import("cpu/thumb/data_processing.zig");
+    const alu = @import("cpu/thumb/alu.zig").fmt4;
+    const transfer = @import("cpu/thumb/data_transfer.zig");
+    const block_transfer = @import("cpu/thumb/block_data_transfer.zig");
+    const swi = @import("cpu/thumb/software_interrupt.zig").fmt17;
+    const branch = @import("cpu/thumb/branch.zig");
+
+    /// Determine index into THUMB InstrFn LUT
+    pub fn idx(opcode: u16) u10 {
+        return @truncate(opcode >> 6);
+    }
+
+    /// Undefined THUMB Instruction Handler
+    fn und(cpu: *Arm946es, opcode: u16) void {
+        const id = idx(opcode);
+        cpu.panic("[CPU/Decode] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
+    }
+
+    fn populate() [0x400]InstrFn {
+        return comptime comptime_blk: {
+            @setEvalBranchQuota(5025); // This is exact
+            var table = [_]InstrFn{und} ** 0x400;
+            //  9  8  7  6  5  4  3  2  1  0
+            // 15 14 13 12 11 10  9  8  7  6
+
+            for (&table, 0..) |*handler, i| {
+                handler.* = switch (@as(u3, i >> 7 & 0x7)) {
+                    0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
+                        const I = i >> 4 & 1 == 1;
+                        const is_sub = i >> 3 & 1 == 1;
+                        const rn = i & 0x7;
+                        break :blk processing.fmt2(InstrFn, I, is_sub, rn);
+                    } else blk: {
+                        const op = i >> 5 & 0x3;
+                        const offset = i & 0x1F;
+                        break :blk processing.fmt1(InstrFn, op, offset);
+                    },
+                    0b001 => blk: {
+                        const op = i >> 5 & 0x3;
+                        const rd = i >> 2 & 0x7;
+                        break :blk processing.fmt3(InstrFn, op, rd);
+                    },
+                    0b010 => switch (@as(u2, i >> 5 & 0x3)) {
+                        0b00 => if (i >> 4 & 1 == 1) blk: {
+                            const op = i >> 2 & 0x3;
+                            const h1 = i >> 1 & 1;
+                            const h2 = i & 1;
+                            break :blk processing.fmt5(InstrFn, op, h1, h2);
+                        } else blk: {
+                            const op = i & 0xF;
+                            break :blk alu(InstrFn, op);
+                        },
+                        0b01 => blk: {
+                            const rd = i >> 2 & 0x7;
+                            break :blk transfer.fmt6(InstrFn, rd);
+                        },
+                        else => blk: {
+                            const op = i >> 4 & 0x3;
+                            const T = i >> 3 & 1 == 1;
+                            break :blk transfer.fmt78(InstrFn, op, T);
+                        },
+                    },
+                    0b011 => blk: {
+                        const B = i >> 6 & 1 == 1;
+                        const L = i >> 5 & 1 == 1;
+                        const offset = i & 0x1F;
+                        break :blk transfer.fmt9(InstrFn, B, L, offset);
+                    },
+                    else => switch (@as(u3, i >> 6 & 0x7)) {
+                        // MSB is guaranteed to be 1
+                        0b000 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const offset = i & 0x1F;
+                            break :blk transfer.fmt10(InstrFn, L, offset);
+                        },
+                        0b001 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const rd = i >> 2 & 0x7;
+                            break :blk transfer.fmt11(InstrFn, L, rd);
+                        },
+                        0b010 => blk: {
+                            const isSP = i >> 5 & 1 == 1;
+                            const rd = i >> 2 & 0x7;
+                            break :blk processing.fmt12(InstrFn, isSP, rd);
+                        },
+                        0b011 => switch (@as(u2, @truncate(i >> 3 & 0x3))) {
+                            0b10 => blk: {
+                                // PUSH / POP
+                                const L = i >> 5 & 1 == 1;
+                                const R = i >> 2 & 1 == 1;
+                                break :blk block_transfer.fmt14(InstrFn, L, R);
+                            },
+                            0b11 => processing.bkpt(InstrFn),
+                            else => blk: {
+                                const S = i >> 1 & 1 == 1;
+                                break :blk processing.fmt13(InstrFn, S);
+                            },
+                        },
+                        0b100 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const rb = i >> 2 & 0x7;
+
+                            break :blk block_transfer.fmt15(InstrFn, L, rb);
+                        },
+                        0b101 => if (i >> 2 & 0xF == 0b1111) blk: {
+                            break :blk swi(InstrFn);
+                        } else blk: {
+                            const cond = i >> 2 & 0xF;
+                            break :blk branch.fmt16(InstrFn, cond);
+                        },
+                        0b110, 0b111 => blk: {
+                            const H = i >> 5 & 0x3;
+                            break :blk branch.linkExchange(InstrFn, H);
+                        },
+                    },
+                };
+            }
+
+            break :comptime_blk table;
+        };
+    }
+};

src/lib.zig

@@ -1,10 +1,473 @@
 const std = @import("std");
 const testing = std.testing;
 
-export fn add(a: i32, b: i32) i32 {
+pub const arm = @import("arm.zig");
-    return a + b;
+
+const Arm32 = @import("arm.zig").Arm32;
+pub const Arm7tdmi = Arm32(.v4t);
+pub const Arm946es = Arm32(.v5te);
+
+pub const Interpreter = union(enum) {
+    const Self = @This();
+
+    v4t: *Arm7tdmi,
+    v5te: *Arm946es,
+
+    pub fn reset(self: Self) void {
+        switch (self) {
+            inline else => |s| s.reset(),
+        }
+    }
+
+    pub fn step(self: Self) void {
+        switch (self) {
+            inline else => |s| s.step(),
+        }
+    }
+
+    pub fn panic(self: Self, comptime format: []const u8, comptime args: anytype) noreturn {
+        switch (self) {
+            inline else => |s| s.panic(format, args),
+        }
+    }
+};
+
+test "create ARMv4T interface" {
+    var bus_impl = ExampleBus{};
+    var scheduler_impl = ExampleScheduler{};
+
+    const bus_interface = Bus.init(&bus_impl);
+    const scheduler_interface = Scheduler.init(&scheduler_impl);
+
+    var arm7tdmi = Arm7tdmi.init(scheduler_interface, bus_interface);
+    var icpu = arm7tdmi.interface();
+
+    icpu.reset();
+    icpu.step();
+    // TODO: call icpu.panic()
 }
 
-test "basic add functionality" {
+test "create ARMv5TE interface" {
-    try testing.expect(add(3, 7) == 10);
+    var bus_impl = ExampleBus{};
+    var scheduler_impl = ExampleScheduler{};
+    var cop_impl = ExampleCoprocessor{};
+
+    const bus_interface = Bus.init(&bus_impl);
+    const scheduler_interface = Scheduler.init(&scheduler_impl);
+    const coprocessor_interface = Coprocessor.init(&cop_impl);
+
+    var arm946es = Arm946es.init(scheduler_interface, bus_interface, coprocessor_interface);
+    var icpu = arm946es.interface();
+
+    icpu.reset();
+    icpu.step();
+    // TODO: call icpu.panic();
 }
+
+pub const Bus = struct {
+    ptr: *anyopaque,
+    vtable: *const Vtable,
+
+    const Vtable = struct {
+        read8: *const fn (ptr: *anyopaque, address: u32) u8,
+        read16: *const fn (ptr: *anyopaque, address: u32) u16,
+        read32: *const fn (ptr: *anyopaque, address: u32) u32,
+
+        write8: *const fn (ptr: *anyopaque, address: u32, value: u8) void,
+        write16: *const fn (ptr: *anyopaque, address: u32, value: u16) void,
+        write32: *const fn (ptr: *anyopaque, address: u32, value: u32) void,
+
+        dbg_read8: *const fn (ptr: *anyopaque, address: u32) u8,
+        dbg_read16: *const fn (ptr: *anyopaque, address: u32) u16,
+        dbg_read32: *const fn (ptr: *anyopaque, address: u32) u32,
+
+        dbg_write8: *const fn (ptr: *anyopaque, address: u32, value: u8) void,
+        dbg_write16: *const fn (ptr: *anyopaque, address: u32, value: u16) void,
+        dbg_write32: *const fn (ptr: *anyopaque, address: u32, value: u32) void,
+
+        reset: *const fn (ptr: *anyopaque) void,
+    };
+
+    pub fn init(obj: anytype) @This() {
+        const P = @TypeOf(obj);
+        const info = @typeInfo(P);
+
+        std.debug.assert(info == .Pointer); // `anytype` is a Pointer
+        std.debug.assert(info.Pointer.size == .One); // Single-Item Pointer
+        std.debug.assert(@typeInfo(info.Pointer.child) == .Struct); // Pointer Child is a `struct`
+
+        const impl = struct {
+            fn read8(ptr: *anyopaque, address: u32) u8 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.read(u8, address);
+            }
+
+            fn read16(ptr: *anyopaque, address: u32) u16 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.read(u16, address);
+            }
+
+            fn read32(ptr: *anyopaque, address: u32) u32 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.read(u32, address);
+            }
+
+            fn write8(ptr: *anyopaque, address: u32, value: u8) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                self.write(u8, address, value);
+            }
+
+            fn write16(ptr: *anyopaque, address: u32, value: u16) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                self.write(u16, address, value);
+            }
+
+            fn write32(ptr: *anyopaque, address: u32, value: u32) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                self.write(u32, address, value);
+            }
+
+            fn dbgRead8(ptr: *anyopaque, address: u32) u8 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.dbgRead(u8, address);
+            }
+
+            fn dbgRead16(ptr: *anyopaque, address: u32) u16 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.dbgRead(u16, address);
+            }
+
+            fn dbgRead32(ptr: *anyopaque, address: u32) u32 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.dbgRead(u32, address);
+            }
+
+            fn dbgWrite8(ptr: *anyopaque, address: u32, value: u8) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                self.dbgWrite(u8, address, value);
+            }
+
+            fn dbgWrite16(ptr: *anyopaque, address: u32, value: u16) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                self.dbgWrite(u16, address, value);
+            }
+
+            fn dbgWrite32(ptr: *anyopaque, address: u32, value: u32) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                self.dbgWrite(u32, address, value);
+            }
+
+            fn reset(ptr: *anyopaque) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                self.reset();
+            }
+        };
+
+        return .{
+            .ptr = obj,
+            .vtable = &.{
+                .read8 = impl.read8,
+                .read16 = impl.read16,
+                .read32 = impl.read32,
+
+                .write8 = impl.write8,
+                .write16 = impl.write16,
+                .write32 = impl.write32,
+
+                .dbg_read8 = impl.dbgRead8,
+                .dbg_read16 = impl.dbgRead16,
+                .dbg_read32 = impl.dbgRead32,
+
+                .dbg_write8 = impl.dbgWrite8,
+                .dbg_write16 = impl.dbgWrite16,
+                .dbg_write32 = impl.dbgWrite32,
+
+                .reset = impl.reset,
+            },
+        };
+    }
+
+    pub fn read(self: @This(), comptime T: type, address: u32) T {
+        return switch (T) {
+            u32 => self.vtable.read32(self.ptr, address),
+            u16 => self.vtable.read16(self.ptr, address),
+            u8 => self.vtable.read8(self.ptr, address),
+            else => @compileError("TODO: Fill this in"),
+        };
+    }
+
+    pub fn write(self: @This(), comptime T: type, address: u32, value: T) void {
+        switch (T) {
+            u32 => self.vtable.write32(self.ptr, address, value),
+            u16 => self.vtable.write16(self.ptr, address, value),
+            u8 => self.vtable.write8(self.ptr, address, value),
+            else => @compileError("TODO: Fill this in"),
+        }
+    }
+
+    pub fn dbgRead(self: @This(), comptime T: type, address: u32) T {
+        return switch (T) {
+            u32 => self.vtable.dbg_read32(self.ptr, address),
+            u16 => self.vtable.dbg_read16(self.ptr, address),
+            u8 => self.vtable.dbg_read8(self.ptr, address),
+            else => @compileError("TODO: Fill this in"),
+        };
+    }
+
+    pub fn dbgWrite(self: @This(), comptime T: type, address: u32, value: T) void {
+        switch (T) {
+            u32 => self.vtable.dbg_write32(self.ptr, address, value),
+            u16 => self.vtable.dbg_write16(self.ptr, address, value),
+            u8 => self.vtable.dbg_write8(self.ptr, address, value),
+            else => @compileError("TODO: Fill this in"),
+        }
+    }
+
+    pub fn reset(self: @This()) void {
+        self.vtable.reset(self.ptr);
+    }
+};
+
+test "create Bus" {
+    var bus_impl = ExampleBus{};
+    const iface = Bus.init(&bus_impl);
+    _ = iface;
+}
+
+test "call Bus reads" {
+    var bus_impl = ExampleBus{};
+    const iface = Bus.init(&bus_impl);
+
+    _ = iface.read(u32, 0x0000_0000);
+    _ = iface.read(u16, 0x0000_0000);
+    _ = iface.read(u8, 0x0000_0000);
+
+    _ = iface.dbgRead(u32, 0x0000_0000);
+    _ = iface.dbgRead(u16, 0x0000_0000);
+    _ = iface.dbgRead(u8, 0x0000_0000);
+}
+
+test "call Bus writes" {
+    var bus_impl = ExampleBus{};
+    const iface = Bus.init(&bus_impl);
+
+    _ = iface.write(u32, 0x0000_0000, 0x0000_0000);
+    _ = iface.write(u16, 0x0000_0000, 0x0000);
+    _ = iface.write(u8, 0x0000_0000, 0x00);
+
+    _ = iface.dbgWrite(u32, 0x0000_0000, 0x0000_0000);
+    _ = iface.dbgWrite(u16, 0x0000_0000, 0x0000);
+    _ = iface.dbgWrite(u8, 0x0000_0000, 0x00);
+}
+
+pub const Coprocessor = struct {
+    ptr: *anyopaque,
+
+    // VTable
+    readFn: *const fn (ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3) u32,
+    writeFn: *const fn (ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void,
+    resetFn: *const fn (ptr: *anyopaque) void,
+
+    pub fn init(obj: anytype) @This() {
+        const P = @TypeOf(obj);
+        const info = @typeInfo(P);
+
+        std.debug.assert(info == .Pointer); // `anytype` is a Pointer
+        std.debug.assert(info.Pointer.size == .One); // Single-Item Pointer
+        std.debug.assert(@typeInfo(info.Pointer.child) == .Struct); // Pointer Child is a `struct`
+
+        const impl = struct {
+            fn read(ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3) u32 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.read(op1, cn, cm, op2);
+            }
+
+            fn write(ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.write(op1, cn, cm, op2, value);
+            }
+
+            fn reset(ptr: *anyopaque) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.reset();
+            }
+        };
+
+        return .{
+            .ptr = obj,
+            .readFn = impl.read,
+            .writeFn = impl.write,
+            .resetFn = impl.reset,
+        };
+    }
+
+    pub fn read(self: @This(), op1: u3, cn: u4, cm: u4, op2: u3) u32 {
+        return self.readFn(self.ptr, op1, cn, cm, op2);
+    }
+
+    pub fn write(self: @This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
+        return self.writeFn(self.ptr, op1, cn, cm, op2, value);
+    }
+
+    pub fn reset(self: @This()) void {
+        return self.resetFn(self.ptr);
+    }
+};
+
+test "create Coprocessor" {
+    var cop_impl = ExampleCoprocessor{};
+    _ = Coprocessor.init(&cop_impl);
+}
+
+test "Coprocessor.read" {
+    var cop_impl = ExampleCoprocessor{};
+    const iface = Coprocessor.init(&cop_impl);
+
+    try testing.expectEqual(@as(u32, 0xDEADBEEF), iface.read(0, 0, 0, 0));
+}
+
+test "Coprocessor.write" {
+    var cop_impl = ExampleCoprocessor{};
+    const iface = Coprocessor.init(&cop_impl);
+
+    iface.write(0, 0, 0, 0, 0xDEADBEEF);
+}
+
+test "Coprocessor.reset" {
+    var cop_impl = ExampleCoprocessor{};
+    const iface = Coprocessor.init(&cop_impl);
+
+    iface.reset();
+}
+
+pub const Scheduler = struct {
+    ptr: *anyopaque,
+
+    // VTable
+    nowFn: *const fn (ptr: *anyopaque) u64,
+    resetFn: *const fn (ptr: *anyopaque) void,
+
+    pub fn init(obj: anytype) @This() {
+        const P = @TypeOf(obj);
+        const info = @typeInfo(P);
+
+        std.debug.assert(info == .Pointer); // `anytype` is a Pointer
+        std.debug.assert(info.Pointer.size == .One); // Single-Item Pointer
+        std.debug.assert(@typeInfo(info.Pointer.child) == .Struct); // Pointer Child is a `struct`
+
+        const impl = struct {
+            fn now(ptr: *anyopaque) u64 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.now();
+            }
+
+            fn reset(ptr: *anyopaque) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                self.reset();
+            }
+        };
+
+        return .{ .ptr = obj, .nowFn = impl.now, .resetFn = impl.reset };
+    }
+
+    pub fn now(self: @This()) u64 {
+        return self.nowFn(self.ptr);
+    }
+
+    pub fn reset(self: @This()) void {
+        self.resetFn(self.ptr);
+    }
+};
+
+test "create Scheduler" {
+    var scheduler_impl = ExampleScheduler{};
+    const iface = Scheduler.init(&scheduler_impl);
+    _ = iface;
+}
+
+test "Scheduler.now()" {
+    var scheduler_impl = ExampleScheduler{};
+    const iface = Scheduler.init(&scheduler_impl);
+
+    try testing.expectEqual(@as(u64, 0), iface.now());
+}
+
+test "Scheduler.reset()" {
+    var scheduler_impl = ExampleScheduler{ .tick = std.math.maxInt(u64) };
+    const iface = Scheduler.init(&scheduler_impl);
+    iface.reset();
+
+    try testing.expectEqual(@as(u64, 0), scheduler_impl.tick);
+}
+
+// ---
+// TESTING
+// ---
+
+const ExampleBus = struct {
+    _: u32 = 0, // Note: need this field so that the ptr align of *lib.ExampleBus != 0
+
+    pub fn read(self: *@This(), comptime T: type, address: u32) T {
+        _ = self;
+        _ = address;
+        return 0;
+    }
+
+    pub fn write(self: *@This(), comptime T: type, address: u32, value: T) void {
+        _ = self;
+        _ = value;
+        _ = address;
+    }
+    pub fn dbgRead(self: *@This(), comptime T: type, address: u32) T {
+        _ = self;
+        _ = address;
+        return 0;
+    }
+
+    pub fn dbgWrite(self: *@This(), comptime T: type, address: u32, value: T) void {
+        _ = self;
+        _ = value;
+        _ = address;
+    }
+
+    pub fn reset(self: *@This()) void {
+        self._ = 0;
+    }
+};
+
+const ExampleScheduler = struct {
+    tick: u64 = 0,
+
+    pub fn now(self: *const @This()) u64 {
+        return self.tick;
+    }
+
+    pub fn reset(self: *@This()) void {
+        self.tick = 0;
+    }
+};
+
+const ExampleCoprocessor = struct {
+    pub fn read(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3) u32 {
+        _ = op2;
+        _ = cm;
+        _ = cn;
+        _ = op1;
+        _ = self;
+
+        return 0xDEADBEEF;
+    }
+
+    pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
+        _ = value;
+        _ = op2;
+        _ = cm;
+        _ = cn;
+        _ = op1;
+        _ = self;
+    }
+
+    pub fn reset(self: *@This()) void {
+        self.* = .{};
+    }
+};