Implement Instruction Pipeline #3
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@ -2,8 +2,8 @@ const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").arm.InstrFn;
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const rotateRight = @import("../barrel_shifter.zig").rotateRight;
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const execute = @import("../barrel_shifter.zig").execute;
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const exec = @import("../barrel_shifter.zig").exec;
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const ror = @import("../barrel_shifter.zig").ror;
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pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
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return struct {
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@ -18,7 +18,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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const op1 = cpu.r[rn];
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const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
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const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
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const op2 = if (I) ror(S, &cpu.cpsr, opcode & 0xFF, amount) else exec(S, cpu, opcode);
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// Undo special condition from above
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if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
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@ -146,7 +146,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
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} else {
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// TST, TEQ specific
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// Barrel Shifter should always calc CPSR C in TST
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if (!S) _ = execute(true, cpu, opcode);
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if (!S) _ = exec(true, cpu, opcode);
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}
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},
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}
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@ -17,7 +17,7 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
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// rn is r15 and L is not set, the PC is 12 ahead
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const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
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const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
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const offset = if (I) shifter.immediate(false, cpu, opcode) else opcode & 0xFFF;
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const modified_base = if (U) base +% offset else base -% offset;
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var address = if (P) modified_base else base;
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@ -5,31 +5,31 @@ const CPSR = @import("../cpu.zig").PSR;
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const rotr = @import("../../util.zig").rotr;
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pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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pub fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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var result: u32 = undefined;
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if (opcode >> 4 & 1 == 1) {
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result = registerShift(S, cpu, opcode);
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result = register(S, cpu, opcode);
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} else {
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result = immShift(S, cpu, opcode);
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result = immediate(S, cpu, opcode);
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}
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return result;
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}
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fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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fn register(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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const rs_idx = opcode >> 8 & 0xF;
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const rm = cpu.r[opcode & 0xF];
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const rs = @truncate(u8, cpu.r[rs_idx]);
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return switch (@truncate(u2, opcode >> 5)) {
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0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
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0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
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0b10 => arithmeticRight(S, &cpu.cpsr, rm, rs),
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0b11 => rotateRight(S, &cpu.cpsr, rm, rs),
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0b00 => lsl(S, &cpu.cpsr, rm, rs),
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0b01 => lsr(S, &cpu.cpsr, rm, rs),
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0b10 => asr(S, &cpu.cpsr, rm, rs),
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0b11 => ror(S, &cpu.cpsr, rm, rs),
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};
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}
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pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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pub fn immediate(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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const amount = @truncate(u8, opcode >> 7 & 0x1F);
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const rm = cpu.r[opcode & 0xF];
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@ -60,17 +60,17 @@ pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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}
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} else {
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switch (@truncate(u2, opcode >> 5)) {
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0b00 => result = logicalLeft(S, &cpu.cpsr, rm, amount),
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0b01 => result = logicalRight(S, &cpu.cpsr, rm, amount),
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0b10 => result = arithmeticRight(S, &cpu.cpsr, rm, amount),
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0b11 => result = rotateRight(S, &cpu.cpsr, rm, amount),
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0b00 => result = lsl(S, &cpu.cpsr, rm, amount),
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0b01 => result = lsr(S, &cpu.cpsr, rm, amount),
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0b10 => result = asr(S, &cpu.cpsr, rm, amount),
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0b11 => result = ror(S, &cpu.cpsr, rm, amount),
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}
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}
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return result;
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}
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pub fn logicalLeft(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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pub fn lsl(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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const amount = @truncate(u5, total_amount);
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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@ -97,7 +97,7 @@ pub fn logicalLeft(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32
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return result;
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}
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pub fn logicalRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 {
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pub fn lsr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 {
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const amount = @truncate(u5, total_amount);
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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@ -121,7 +121,7 @@ pub fn logicalRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u
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return result;
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}
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pub fn arithmeticRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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pub fn asr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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const amount = @truncate(u5, total_amount);
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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@ -138,7 +138,7 @@ pub fn arithmeticRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8)
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return result;
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}
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pub fn rotateRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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pub fn ror(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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const result = rotr(u32, rm, total_amount);
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if (S and total_amount != 0) {
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@ -5,10 +5,10 @@ const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
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const adc = @import("../arm/data_processing.zig").adc;
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const sbc = @import("../arm/data_processing.zig").sbc;
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const lsl = @import("../barrel_shifter.zig").logicalLeft;
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const lsr = @import("../barrel_shifter.zig").logicalRight;
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const asr = @import("../barrel_shifter.zig").arithmeticRight;
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const ror = @import("../barrel_shifter.zig").rotateRight;
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const lsl = @import("../barrel_shifter.zig").lsl;
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const lsr = @import("../barrel_shifter.zig").lsr;
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const asr = @import("../barrel_shifter.zig").asr;
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const ror = @import("../barrel_shifter.zig").ror;
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pub fn fmt4(comptime op: u4) InstrFn {
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return struct {
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@ -6,9 +6,9 @@ const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
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const add = @import("../arm/data_processing.zig").add;
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const lsl = @import("../barrel_shifter.zig").logicalLeft;
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const lsr = @import("../barrel_shifter.zig").logicalRight;
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const asr = @import("../barrel_shifter.zig").arithmeticRight;
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const lsl = @import("../barrel_shifter.zig").lsl;
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const lsr = @import("../barrel_shifter.zig").lsr;
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const asr = @import("../barrel_shifter.zig").asr;
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pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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return struct {
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Loading…
Reference in New Issue