Implement Instruction Pipeline #3
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@ -46,7 +46,7 @@ iwram: Iwram,
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ewram: Ewram,
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ewram: Ewram,
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io: Io,
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io: Io,
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cpu: ?*Arm7tdmi,
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cpu: *Arm7tdmi,
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sched: *Scheduler,
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sched: *Scheduler,
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pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
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pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
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@ -82,7 +82,7 @@ pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
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// General Internal Memory
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// General Internal Memory
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0x00 => blk: {
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0x00 => blk: {
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if (address < Bios.size)
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if (address < Bios.size)
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break :blk self.bios.dbgRead(T, self.cpu.?.r[15], aligned_addr);
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break :blk self.bios.dbgRead(T, self.cpu.r[15], aligned_addr);
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break :blk self.readOpenBus(T, address);
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break :blk self.readOpenBus(T, address);
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},
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},
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@ -119,11 +119,11 @@ fn readIo(self: *const Self, comptime T: type, unaligned_address: u32) T {
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}
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}
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fn readOpenBus(self: *const Self, comptime T: type, address: u32) T {
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fn readOpenBus(self: *const Self, comptime T: type, address: u32) T {
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const r15 = self.cpu.?.r[15];
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const r15 = self.cpu.r[15];
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const word = blk: {
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const word = blk: {
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// If u32 Open Bus, read recently fetched opcode (PC + 8)
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// If u32 Open Bus, read recently fetched opcode (PC + 8)
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if (!self.cpu.?.cpsr.t.read()) break :blk self.dbgRead(u32, r15 + 4);
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if (!self.cpu.cpsr.t.read()) break :blk self.dbgRead(u32, r15 + 4);
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const page = @truncate(u8, r15 >> 24);
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const page = @truncate(u8, r15 >> 24);
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switch (page) {
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switch (page) {
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@ -167,7 +167,7 @@ pub fn read(self: *Self, comptime T: type, address: u32) T {
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// General Internal Memory
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// General Internal Memory
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0x00 => blk: {
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0x00 => blk: {
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if (address < Bios.size)
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if (address < Bios.size)
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break :blk self.bios.read(T, self.cpu.?.r[15], aligned_addr);
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break :blk self.bios.read(T, self.cpu.r[15], aligned_addr);
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break :blk self.readOpenBus(T, address);
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break :blk self.readOpenBus(T, address);
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},
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},
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