Implement Instruction Pipeline #3
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@ -10,8 +10,6 @@ const sub = @import("../arm/data_processing.zig").sub;
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const cmp = @import("../arm/data_processing.zig").cmp;
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const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
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const log = std.log.scoped(.Thumb1);
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pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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@ -58,37 +56,38 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
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pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
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const src_idx = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
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const dst_idx = @as(u4, h1) << 3 | (opcode & 0x7);
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const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
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const rd = @as(u4, h1) << 3 | (opcode & 0x7);
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const src = if (src_idx == 0xF) (cpu.r[src_idx] + 2) & 0xFFFF_FFFE else cpu.r[src_idx];
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const dst = if (dst_idx == 0xF) (cpu.r[dst_idx] + 2) & 0xFFFF_FFFE else cpu.r[dst_idx];
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const rs_value = if (rs == 0xF) cpu.r[rs] & ~@as(u32, 1) else cpu.r[rs];
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const rd_value = if (rd == 0xF) cpu.r[rd] & ~@as(u32, 1) else cpu.r[rd];
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switch (op) {
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0b00 => {
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// ADD
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const sum = add(false, cpu, dst, src);
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cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFE else sum;
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const sum = add(false, cpu, rd_value, rs_value);
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cpu.r[rd] = if (rd == 0xF) sum & ~@as(u32, 1) else sum;
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},
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0b01 => cmp(cpu, dst, src), // CMP
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0b01 => cmp(cpu, rd_value, rs_value), // CMP
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0b10 => {
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// MOV
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cpu.r[dst_idx] = if (dst_idx == 0xF) src & 0xFFFF_FFFE else src;
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cpu.r[rd] = if (rd == 0xF) rs_value & ~@as(u32, 1) else rs_value;
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},
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0b11 => {
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// BX
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const thumb = src & 1 == 1;
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cpu.r[15] = src & ~@as(u32, 1);
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cpu.cpsr.t.write(thumb);
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const thumb = rs_value & 1 == 1;
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cpu.r[15] = rs_value & ~@as(u32, 1);
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cpu.cpsr.t.write(thumb);
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if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
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// Pipeline alrady flushed
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return; // FIXME: Is this necessary? (Refactor out?)
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// TODO: We shouldn't need to worry about the if statement
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// below, because in BX, rd SBZ (and H1 is guaranteed to be 0)
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return;
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},
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}
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if (dst_idx == 0xF) cpu.pipe.reload(u16, cpu);
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if (rd == 0xF) cpu.pipe.reload(u16, cpu);
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}
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}.inner;
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}
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