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Implement Instruction Pipeline #3

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paoda merged 20 commits from pipeline into main 2022-10-17 19:42:42 +00:00
Conversation 0 Commits 20 Files Changed 18 +20 -17
1 changed files with 20 additions and 17 deletions
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Showing only changes of commit 2799c3f202 - Show all commits

31
src/core/cpu.zig
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@ -490,27 +490,26 @@ pub const Arm7tdmi = struct {
pub fn handleInterrupt(self: *Self) void {
const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
if (should_handle != 0) {
// Return if IME is disabled, CPSR I is set or there is nothing to handle
if (!self.bus.io.ime or self.cpsr.i.read() or should_handle == 0) return;
// If pipeline isn't full, return but reschedule the handling of the event
if (!self.pipe.isFull()) return;
// log.debug("Handling Interrupt!", .{});
self.bus.io.haltcnt = .Execute;
// log.debug("An Interrupt was Fired!", .{});
// Either IME is not true or I in CPSR is true
// Don't handle interrupts
if (!self.bus.io.ime or self.cpsr.i.read()) return;
// log.debug("An interrupt was Handled!", .{});
// FIXME: Is the return address ahead?
const r15 = self.r[15];
const cpsr = self.cpsr.raw;
const ret_addr = self.r[15] - if (self.cpsr.t.read()) 2 else @as(u32, 4);
const new_spsr = self.cpsr.raw;
self.changeMode(.Irq);
self.cpsr.t.write(false);
self.cpsr.i.write(true);
self.r[14] = r15;
self.spsr.raw = cpsr;
self.r[15] = 0x000_0018;
}
self.r[14] = ret_addr;
self.spsr.raw = new_spsr;
self.r[15] = 0x0000_0018;
self.pipe.flush();
}
inline fn fetch(self: *Self, comptime T: type) T {
@ -670,6 +669,10 @@ const Pipline = struct {
self.flushed = true;
}
pub fn isFull(self: *const Self) bool {
return self.stage[0] != null and self.stage[1] != null;
}
pub fn step(self: *Self, cpu: *Arm7tdmi, comptime T: type) ?u32 {
comptime std.debug.assert(T == u32 or T == u16);