fix: implement Ace Lightning (2002) obscure behaviour

.github/workflows/main.yml

@@ -14,13 +14,13 @@ jobs:
   build:
     strategy:
       matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
+        # os: [ubuntu-latest, windows-latest, macos-latest]
-        # os: [ubuntu-latest, windows-latest]
+        os: [ubuntu-latest, windows-latest]
     runs-on: ${{matrix.os}}
     steps:
       - uses: goto-bus-stop/setup-zig@v2
         with:
-          version: 0.11.0-dev.3395+1e7dcaa3a
+          version: master
       - name: prepare-linux
         if: runner.os == 'Linux'
         run: |
@@ -41,9 +41,6 @@ jobs:
           submodules: recursive
       - name: build 
         run: zig build -Doptimize=ReleaseSafe -Dcpu=baseline
-      - name: prepare-executable
-        run: |
-            mv zig-out/lib/* zig-out/bin
       - name: upload
         uses: actions/upload-artifact@v3
         with:
@@ -57,6 +54,6 @@ jobs:
           submodules: recursive
       - uses: goto-bus-stop/setup-zig@v2
         with:
-          version: 0.11.0-dev.3395+1e7dcaa3a
+          version: master
       - run: zig fmt src/**/*.zig
   

.gitmodules

@@ -1,6 +1,27 @@
 [submodule "lib/SDL.zig"]
 	path = lib/SDL.zig
 	url = https://github.com/MasterQ32/SDL.zig
+[submodule "lib/zig-clap"]
+	path = lib/zig-clap
+	url = https://github.com/Hejsil/zig-clap
+[submodule "lib/known-folders"]
+	path = lib/known-folders
+	url = https://github.com/ziglibs/known-folders
+[submodule "lib/zig-datetime"]
+	path = lib/zig-datetime
+	url = https://github.com/frmdstryr/zig-datetime
+[submodule "lib/zig-toml"]
+	path = lib/zig-toml
+	url = https://github.com/aeronavery/zig-toml
+[submodule "lib/zba-gdbstub"]
+	path = lib/zba-gdbstub
+	url = https://git.musuka.dev/paoda/zba-gdbstub
 [submodule "lib/zgui"]
 	path = lib/zgui
 	url = https://git.musuka.dev/paoda/zgui
+[submodule "lib/nfd-zig"]
+	path = lib/nfd-zig
+	url = https://github.com/fabioarnold/nfd-zig
+[submodule "lib/zba-util"]
+	path = lib/zba-util
+	url = https://git.musuka.dev/paoda/zba-util.git

README.md

@@ -19,30 +19,79 @@ This is a simple (read: incomplete) for-fun long-term project. I hope to get "mo
 
 ## Usage
 
-ZBA supports both a CLI and a GUI. If running from the terminal, try using `zba --help` to see what you can do. If you want to use the GUI, feel free to just run `zba` without any arguments.
+As it currently exists, ZBA is run from the terminal. In your console of choice, type `./zba --help` to see what you can do.
 
-ZBA does not feature any BIOS HLE, so providing one will be necessary if a ROM makes use of it. Need one? Why not try using the open-source [Cult-Of-GBA BIOS](https://github.com/Cult-of-GBA/BIOS) written by [fleroviux](https://github.com/fleroviux) and [DenSinH](https://github.com/DenSinH)?
+I typically find myself typing `./zba -b ./bin/bios.bin` and then going to File -> Insert ROM to load the title of my choice.
+
+Need a BIOS? Why not try using the open-source [Cult-Of-GBA BIOS](https://github.com/Cult-of-GBA/BIOS) written by [fleroviux](https://github.com/fleroviux) and [DenSinH](https://github.com/DenSinH)?
 
 Finally it's worth noting that ZBA uses a TOML config file it'll store in your OS's data directory. See `example.toml` to learn about the defaults and what exactly you can mess around with.
 
+## Tests
+
+GBA Tests | [jsmolka](https://github.com/jsmolka/)
+--- | ---
+`arm.gba`,  `thumb.gba` | PASS
+`memory.gba`, `bios.gba` | PASS
+`flash64.gba`, `flash128.gba` | PASS
+`sram.gba` | PASS
+`none.gba` | PASS
+`hello.gba`, `shades.gba`, `stripes.gba` | PASS
+`nes.gba` | PASS
+
+GBARoms | [DenSinH](https://github.com/DenSinH/)
+--- | ---
+`eeprom-test`, `flash-test` | PASS
+`midikey2freq` | PASS
+`swi-tests-random` | FAIL
+
+gba_tests | [destoer](https://github.com/destoer/)
+--- | ---
+`cond_invalid.gba` | PASS
+`dma_priority.gba` | PASS
+`hello_world.gba` | PASS
+`if_ack.gba` | PASS
+`line_timing.gba` | FAIL
+`lyc_midline.gba` | FAIL
+`window_midframe.gba` | FAIL
+
+GBA Test Collection | [ladystarbreeze](https://github.com/ladystarbreeze)
+--- | ---
+`retAddr.gba` | PASS
+`helloWorld.gba` | PASS
+`helloAudio.gba` | PASS
+
+FuzzARM | [DenSinH](https://github.com/DenSinH/)
+--- | ---
+`main.gba` | PASS
+
+arm7wrestler GBA Fixed | [destoer](https://github.com/destoer)
+--- | ---
+`armwrestler-gba-fixed.gba` | PASS
+
+## Resources
+
+- [GBATEK](https://problemkaputt.de/gbatek.htm)
+- [TONC](https://coranac.com/tonc/text/toc.htm)
+- [ARM Architecture Reference Manual](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/third-party/ddi0100e_arm_arm.pdf)
+- [ARM7TDMI Data Sheet](https://www.dca.fee.unicamp.br/cursos/EA871/references/ARM/ARM7TDMIDataSheet.pdf)
+
 ## Compiling
 
-Most recently built on Zig [v0.11.0-dev.3395+1e7dcaa3a](https://github.com/ziglang/zig/tree/1e7dcaa3a)
+Most recently built on Zig [v0.11.0-dev.2168+322ace70f](https://github.com/ziglang/zig/tree/322ace70f)
 
 ### Dependencies
 
 Dependency | Source
 --- | ---
+SDL.zig | <https://github.com/MasterQ32/SDL.zig>
 known-folders | <https://github.com/ziglibs/known-folders>
 nfd-zig | <https://github.com/fabioarnold/nfd-zig>
-SDL.zig | <https://github.com/MasterQ32/SDL.zig>
-tomlz | <https://github.com/mattyhall/tomlz>
-zba-gdbstub | <https://github.com/paoda/zba-gdbstub>
-zba-util | <https://git.musuka.dev/paoda/zba-util>
 zgui | <https://github.com/michal-z/zig-gamedev/tree/main/libs/zgui>
 zig-clap | <https://github.com/Hejsil/zig-clap>
 zig-datetime | <https://github.com/frmdstryr/zig-datetime>
-`bitfield.zig` | [https://github.com/FlorenceOS/Florence](https://github.com/FlorenceOS/Florence/blob/aaa5a9e568/lib/util/bitfields.zig)
+zig-toml | <https://github.com/aeronavery/zig-toml>
+`bitfields.zig` | [https://github.com/FlorenceOS/Florence](https://github.com/FlorenceOS/Florence/blob/aaa5a9e568/lib/util/bitfields.zig)
 `gl.zig` | <https://github.com/MasterQ32/zig-opengl>
 
 Use `git submodule update --init` from the project root to pull the git relevant git submodules
@@ -55,42 +104,16 @@ Be sure to provide SDL2 using:
 
 `SDL.zig` will provide a helpful compile error if the zig compiler is unable to find SDL2.
 
-Once you've got all the dependencies, execute `zig build -Doptimize=ReleaseSafe`. The executable will be under `zig-out/bin` and the shared libraries (if enabled) under `zig-out/lib`. If working with shared libraries on windows, be sure to add all artifacts to the same directory. On Unix, you'll want to make use of `LD_PRELOAD`.
+Once you've got all the dependencies, execute `zig build -Doptimize=ReleaseSafe`. The executable is located at `zig-out/bin/`.
 
 ## Controls
 
-Key | Button | | Key | Button
+Key | Button
---- | --- | --- | --- | ---
+--- | ---
-<kbd>A</kbd> | L | | <kbd>S</kbd> | R
+<kbd>X</kbd> | A
-<kbd>X</kbd> | A | | <kbd>Z</kbd> | B
+<kbd>Z</kbd> | B
-<kbd>Return</kbd> | Start | | <kbd>RShift</kbd> | Select
+<kbd>A</kbd> | L
+<kbd>S</kbd> | R
+<kbd>Return</kbd> | Start
+<kbd>RShift</kbd> | Select
 Arrow Keys | D-Pad
-
-## Tests
-
-GBA Tests | [jsmolka](https://github.com/jsmolka/) | gba_tests | [destoer](https://github.com/destoer/)
---- | --- | --- | ---
-`arm.gba`,  `thumb.gba` | PASS | `cond_invalid.gba` | PASS
-`memory.gba`, `bios.gba` | PASS | `dma_priority.gba` | PASS
-`flash64.gba`, `flash128.gba` | PASS | `hello_world.gba` | PASS
-`sram.gba` | PASS | `if_ack.gba` | PASS
-`none.gba` | PASS | `line_timing.gba` | FAIL
-`hello.gba`, `shades.gba`, `stripes.gba` | PASS | `lyc_midline.gba` | FAIL
-`nes.gba` | PASS | `window_midframe.gba` | FAIL
-
-GBARoms | [DenSinH](https://github.com/DenSinH/) | GBA Test Collection | [ladystarbreeze](https://github.com/ladystarbreeze)
---- | --- | --- | ---
-`eeprom-test`, `flash-test` | PASS | `retAddr.gba` | PASS
-`midikey2freq` | PASS | `helloWorld.gba` | PASS
-`swi-tests-random` | FAIL | `helloAudio.gba` | PASS
-
-FuzzARM | [DenSinH](https://github.com/DenSinH/) |  arm7wrestler GBA Fixed | [destoer](https://github.com/destoer)
---- | --- | --- | ---
-`main.gba` | PASS | `armwrestler-gba-fixed.gba` | PASS
-
-## Resources
-
-- [GBATEK](https://problemkaputt.de/gbatek.htm)
-- [TONC](https://coranac.com/tonc/text/toc.htm)
-- [ARM Architecture Reference Manual](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/third-party/ddi0100e_arm_arm.pdf)
-- [ARM7TDMI Data Sheet](https://www.dca.fee.unicamp.br/cursos/EA871/references/ARM/ARM7TDMIDataSheet.pdf)

build.zig

@@ -2,11 +2,13 @@ const std = @import("std");
 const builtin = @import("builtin");
 
 const Sdk = @import("lib/SDL.zig/Sdk.zig");
+const gdbstub = @import("lib/zba-gdbstub/build.zig");
 const zgui = @import("lib/zgui/build.zig");
+const nfd = @import("lib/nfd-zig/build.zig");
 
 pub fn build(b: *std.Build) void {
     // Minimum Zig Version
-    const min_ver = std.SemanticVersion.parse("0.11.0-dev.3395+1e7dcaa3a") catch return; // https://github.com/ziglang/zig/commit/34865d693
+    const min_ver = std.SemanticVersion.parse("0.11.0-dev.2168+322ace70f") catch return; // https://github.com/ziglang/zig/commit/322ace70f
     if (builtin.zig_version.order(min_ver).compare(.lt)) {
         std.log.err("{s}", .{b.fmt("Zig v{} does not meet the minimum version requirement. (Zig v{})", .{ builtin.zig_version, min_ver })});
         std.os.exit(1);
@@ -24,35 +26,48 @@ pub fn build(b: *std.Build) void {
 
     exe.setMainPkgPath("."); // Necessary so that src/main.zig can embed example.toml
 
-    exe.addModule("known_folders", b.dependency("known-folders", .{}).module("known-folders")); // https://github.com/ziglibs/known-folders
+    // Known Folders (%APPDATA%, XDG, etc.)
-    exe.addModule("datetime", b.dependency("zig-datetime", .{}).module("zig-datetime")); // https://github.com/frmdstryr/zig-datetime
+    exe.addAnonymousModule("known_folders", .{ .source_file = .{ .path = "lib/known-folders/known-folders.zig" } });
-    exe.addModule("clap", b.dependency("zig-clap", .{}).module("clap")); // https://github.com/Hejsil/zig-clap
-    exe.addModule("gdbstub", b.dependency("zba-gdbstub", .{}).module("gdbstub")); // https://git.musuka.dev/paoda/zba-gdbstub
-    exe.addModule("zba-util", b.dependency("zba-util", .{}).module("zba-util")); // https://git.musuka.dev/paoda/zba-util
-    exe.addModule("tomlz", b.dependency("tomlz", .{}).module("tomlz")); // https://github.com/mattyhall/tomlz
-    exe.addModule("arm32", b.dependency("arm32", .{}).module("arm32")); // https://git.musuka.dev/paoda/arm32
 
-    // https://github.com/fabioarnold/nfd-zig
+    // DateTime Library
-    const nfd_dep = b.dependency("nfd", .{ .target = target, .optimize = optimize });
+    exe.addAnonymousModule("datetime", .{ .source_file = .{ .path = "lib/zig-datetime/src/main.zig" } });
-    exe.linkLibrary(nfd_dep.artifact("nfd"));
-    exe.addModule("nfd", nfd_dep.module("nfd"));
 
-    // https://github.com/MasterQ32/SDL.zig
+    // Bitfield type from FlorenceOS: https://github.com/FlorenceOS/
+    exe.addAnonymousModule("bitfield", .{ .source_file = .{ .path = "lib/bitfield.zig" } });
+
+    // Argument Parsing Library
+    exe.addAnonymousModule("clap", .{ .source_file = .{ .path = "lib/zig-clap/clap.zig" } });
+
+    // TOML Library
+    exe.addAnonymousModule("toml", .{ .source_file = .{ .path = "lib/zig-toml/src/toml.zig" } });
+
+    // OpenGL 3.3 Bindings
+    exe.addAnonymousModule("gl", .{ .source_file = .{ .path = "lib/gl.zig" } });
+
+    // ZBA utility code
+    exe.addAnonymousModule("zba-util", .{ .source_file = .{ .path = "lib/zba-util/src/lib.zig" } });
+
+    // gdbstub
+    exe.addModule("gdbstub", gdbstub.getModule(b));
+
+    // NativeFileDialog(ue) Bindings
+    exe.linkLibrary(nfd.makeLib(b, target, optimize));
+    exe.addModule("nfd", nfd.getModule(b));
+
+    // Zig SDL Bindings: https://github.com/MasterQ32/SDL.zig
     const sdk = Sdk.init(b, null);
     sdk.link(exe, .dynamic);
     exe.addModule("sdl2", sdk.getNativeModule());
 
-    // https://git.musuka.dev/paoda/zgui
+    // Dear ImGui bindings
+
     // .shared option should stay in sync with SDL.zig call above where true == .dynamic, and false == .static
     const zgui_pkg = zgui.package(b, target, optimize, .{ .options = .{ .backend = .sdl2_opengl3, .shared = true } });
     zgui_pkg.link(exe);
 
-    exe.addAnonymousModule("bitfield", .{ .source_file = .{ .path = "lib/bitfield.zig" } }); // https://github.com/FlorenceOS/
+    exe.install();
-    exe.addAnonymousModule("gl", .{ .source_file = .{ .path = "lib/gl.zig" } }); // https://github.com/MasterQ32/zig-opengl
 
-    b.installArtifact(exe);
+    const run_cmd = exe.run();
-
-    const run_cmd = b.addRunArtifact(exe);
     run_cmd.step.dependOn(b.getInstallStep());
     if (b.args) |args| {
         run_cmd.addArgs(args);

build.zig.zon

@@ -1,38 +0,0 @@
-.{
-    .name = "zba",
-    .version = "0.1.0",
-    .dependencies = .{
-        .nfd = .{
-            .url = "https://github.com/fabioarnold/nfd-zig/archive/8520a6807f046a23ecf3143e22fc49d2a9d1c189.tar.gz",
-            .hash = "122089e0f5ab5e4729a09aed48d721b98ed2b362923ead797c6af3b54ef9a725203f",
-        },
-        .@"known-folders" = .{
-            .url = "https://github.com/ziglibs/known-folders/archive/d13ba6137084e55f873f6afb67447fe8906cc951.tar.gz",
-            .hash = "122028c00915d9b37296059be8a3883c718dbb5bd174350caedf152fed1f46f99607",
-        },
-        .@"zig-datetime" = .{
-            .url = "https://github.com/frmdstryr/zig-datetime/archive/e4a2bc92b3771a745145c9a6961f0b5277a48335.tar.gz",
-            .hash = "12209fc05ecb5add8f87152f03f99243a419c9dd5a04c6b4a359d6b4f13426fede0c",
-        },
-        .@"zig-clap" = .{
-            .url = "https://github.com/Hejsil/zig-clap/archive/a1b7a7301b0006bb4c8daaaf5ade8a6df8ec13ae.tar.gz",
-            .hash = "12205aeff59f41f96033d280471730c171c9a825d8758743249bed834e1590f593e3",
-        },
-        .@"zba-gdbstub" = .{
-            .url = "https://git.musuka.dev/paoda/zba-gdbstub/archive/39a4260ffd83bae7bb44bb098872c96382fb5ba3.tar.gz",
-            .hash = "1220b87e4c519f28dce7380ed83f936a4aea2d81046209b18a23eb6c0738b156ca16",
-        },
-        .@"zba-util" = .{
-            .url = "https://git.musuka.dev/paoda/zba-util/archive/e616cf09e53f5c402c8f040d14baa211683e70e3.tar.gz",
-            .hash = "1220b80b2c0989dcc47275ab9d7d70da4858ef3c1fe1f934e8d838e65028127f6ef3",
-        },
-        .tomlz = .{
-            .url = "https://github.com/mattyhall/tomlz/archive/4928d38e9bb682a9966ffe7f41230435d0111b1e.tar.gz",
-            .hash = "12202b57d7b46fff8d16a17371c4f9b711a56b866f0cd11844e4243c09343a2c4c6d",
-        },
-        .arm32 = .{
-            .url = "https://git.musuka.dev/paoda/arm32/archive/3c8a87c14dfa2501bd0a7f2236259e2d8d0fbcd9.tar.gz",
-            .hash = "12202a06a5d20d0da9ab6596a04821431d261c9900c7916a87148619dcb77c745044",
-        },
-    },
-}

example.toml

@@ -1,4 +1,4 @@
-[host]
+[Host]
 # Using nearest-neighbour scaling, how many times the native resolution 
 # of the game bow should the screen be?
 win_scale = 3
@@ -7,7 +7,7 @@ vsync = true
 # Mute ZBA
 mute = false
 
-[guest]
+[Guest]
 # Sync Emulation to Audio 
 audio_sync = true
 # Sync Emulation to Video
@@ -17,7 +17,7 @@ force_rtc = false
 # Skip BIOS
 skip_bios = false
 
-[debug]
+[Debug]
 # Enable detailed CPU logs
 cpu_trace = false
 # When false and builtin.mode == .Debug, ZBA will panic

src/config.zig

@@ -1,5 +1,5 @@
 const std = @import("std");
-const tomlz = @import("tomlz");
+const toml = @import("toml");
 
 const Allocator = std.mem.Allocator;
 
@@ -7,7 +7,6 @@ const log = std.log.scoped(.Config);
 var state: Config = .{};
 
 const Config = struct {
-    // FIXME: tomlz expects these to be case sensitive
     host: Host = .{},
     guest: Guest = .{},
     debug: Debug = .{},
@@ -59,5 +58,29 @@ pub fn load(allocator: Allocator, file_path: []const u8) !void {
     const contents = try config_file.readToEndAlloc(allocator, try config_file.getEndPos());
     defer allocator.free(contents);
 
-    state = try tomlz.parser.decode(Config, allocator, contents);
+    var parser = try toml.parseFile(allocator, file_path);
+    defer parser.deinit();
+
+    const table = try parser.parse();
+    defer table.deinit();
+
+    // TODO: Report unknown config options
+
+    if (table.keys.get("Host")) |host| {
+        if (host.Table.keys.get("win_scale")) |scale| state.host.win_scale = scale.Integer;
+        if (host.Table.keys.get("vsync")) |vsync| state.host.vsync = vsync.Boolean;
+        if (host.Table.keys.get("mute")) |mute| state.host.mute = mute.Boolean;
+    }
+
+    if (table.keys.get("Guest")) |guest| {
+        if (guest.Table.keys.get("audio_sync")) |sync| state.guest.audio_sync = sync.Boolean;
+        if (guest.Table.keys.get("video_sync")) |sync| state.guest.video_sync = sync.Boolean;
+        if (guest.Table.keys.get("force_rtc")) |forced| state.guest.force_rtc = forced.Boolean;
+        if (guest.Table.keys.get("skip_bios")) |skip| state.guest.skip_bios = skip.Boolean;
+    }
+
+    if (table.keys.get("Debug")) |debug| {
+        if (debug.Table.keys.get("cpu_trace")) |trace| state.debug.cpu_trace = trace.Boolean;
+        if (debug.Table.keys.get("unhandled_io")) |unhandled| state.debug.unhandled_io = unhandled.Boolean;
+    }
 }

src/core/Bus.zig

@@ -1,6 +1,6 @@
 const std = @import("std");
 
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
 const Bios = @import("bus/Bios.zig");
 const Ewram = @import("bus/Ewram.zig");
 const GamePak = @import("bus/GamePak.zig");

src/core/apu.zig

@@ -3,8 +3,7 @@ const SDL = @import("sdl2");
 const io = @import("bus/io.zig");
 const util = @import("../util.zig");
 
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
-const Bus = @import("Bus.zig");
 const Scheduler = @import("scheduler.zig").Scheduler;
 const ToneSweep = @import("apu/ToneSweep.zig");
 const Tone = @import("apu/Tone.zig");
@@ -521,20 +520,18 @@ pub const Apu = struct {
     pub fn onDmaAudioSampleRequest(self: *Self, cpu: *Arm7tdmi, tim_id: u3) void {
         if (!self.cnt.apu_enable.read()) return;
 
-        const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
         if (@boolToInt(self.dma_cnt.chA_timer.read()) == tim_id) {
             if (!self.chA.enabled) return;
 
             self.chA.updateSample();
-            if (self.chA.len() <= 15) bus_ptr.dma[1].requestAudio(0x0400_00A0);
+            if (self.chA.len() <= 15) cpu.bus.dma[1].requestAudio(0x0400_00A0);
         }
 
         if (@boolToInt(self.dma_cnt.chB_timer.read()) == tim_id) {
             if (!self.chB.enabled) return;
 
             self.chB.updateSample();
-            if (self.chB.len() <= 15) bus_ptr.dma[2].requestAudio(0x0400_00A4);
+            if (self.chB.len() <= 15) cpu.bus.dma[2].requestAudio(0x0400_00A4);
         }
     }
 };

src/core/bus/Bios.zig

@@ -63,23 +63,18 @@ pub fn write(_: *Self, comptime T: type, addr: u32, value: T) void {
 
 pub fn init(allocator: Allocator, maybe_path: ?[]const u8) !Self {
     if (maybe_path == null) return .{ .buf = null, .allocator = allocator };
-    const file_path = maybe_path.?;
+    const path = maybe_path.?;
 
     const buf = try allocator.alloc(u8, Self.size);
     errdefer allocator.free(buf);
 
-    var self: Self = .{ .buf = buf, .allocator = allocator };
+    const file = try std.fs.cwd().openFile(path, .{});
-    try self.load(file_path);
-
-    return self;
-}
-
-pub fn load(self: *Self, file_path: []const u8) !void {
-    const file = try std.fs.cwd().openFile(file_path, .{});
     defer file.close();
 
-    const len = try file.readAll(self.buf orelse return error.UnallocatedBuffer);
+    const file_len = try file.readAll(buf);
-    if (len != Self.size) log.err("Expected BIOS to be {}B, was {}B", .{ Self.size, len });
+    if (file_len != Self.size) log.err("Expected BIOS to be {}B, was {}B", .{ Self.size, file_len });
+
+    return Self{ .buf = buf, .allocator = allocator };
 }
 
 pub fn reset(self: *Self) void {

src/core/bus/Ewram.zig

@@ -27,7 +27,7 @@ pub fn write(self: *const Self, comptime T: type, address: usize, value: T) void
 
 pub fn init(allocator: Allocator) !Self {
     const buf = try allocator.alloc(u8, ewram_size);
-    @memset(buf, 0);
+    std.mem.set(u8, buf, 0);
 
     return Self{
         .buf = buf,
@@ -36,7 +36,7 @@ pub fn init(allocator: Allocator) !Self {
 }
 
 pub fn reset(self: *Self) void {
-    @memset(self.buf, 0);
+    std.mem.set(u8, self.buf, 0);
 }
 
 pub fn deinit(self: *Self) void {

src/core/bus/GamePak.zig

@@ -1,7 +1,7 @@
 const std = @import("std");
 const config = @import("../../config.zig");
 
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
 const Backup = @import("backup.zig").Backup;
 const Gpio = @import("gpio.zig").Gpio;
 const Allocator = std.mem.Allocator;

src/core/bus/Iwram.zig

@@ -27,7 +27,7 @@ pub fn write(self: *const Self, comptime T: type, address: usize, value: T) void
 
 pub fn init(allocator: Allocator) !Self {
     const buf = try allocator.alloc(u8, iwram_size);
-    @memset(buf, 0);
+    std.mem.set(u8, buf, 0);
 
     return Self{
         .buf = buf,
@@ -36,7 +36,7 @@ pub fn init(allocator: Allocator) !Self {
 }
 
 pub fn reset(self: *Self) void {
-    @memset(self.buf, 0);
+    std.mem.set(u8, self.buf, 0);
 }
 
 pub fn deinit(self: *Self) void {

src/core/bus/backup.zig

@@ -110,7 +110,7 @@ pub const Backup = struct {
         };
 
         const buf = try allocator.alloc(u8, buf_size);
-        @memset(buf, 0xFF);
+        std.mem.set(u8, buf, 0xFF);
 
         var backup = Self{
             .buf = buf,
@@ -163,7 +163,7 @@ pub const Backup = struct {
         switch (self.kind) {
             .Sram, .Flash, .Flash1M => {
                 if (self.buf.len == file_buf.len) {
-                    @memcpy(self.buf, file_buf);
+                    std.mem.copy(u8, self.buf, file_buf);
                     return log.info("Loaded Save from {s}", .{file_path});
                 }
 
@@ -174,7 +174,7 @@ pub const Backup = struct {
                     self.eeprom.kind = if (file_buf.len == 0x200) .Small else .Large;
 
                     self.buf = try allocator.alloc(u8, file_buf.len);
-                    @memcpy(self.buf, file_buf);
+                    std.mem.copy(u8, self.buf, file_buf);
                     return log.info("Loaded Save from {s}", .{file_path});
                 }
 
@@ -205,6 +205,10 @@ pub const Backup = struct {
         const file_path = try self.savePath(allocator, path);
         defer allocator.free(file_path);
 
+        // FIXME: communicate edge case to the user?
+        if (std.mem.eql(u8, &self.title, "ACE LIGHTNIN"))
+            return;
+
         switch (self.kind) {
             .Sram, .Flash, .Flash1M, .Eeprom => {
                 const file = try std.fs.createFileAbsolute(file_path, .{});

src/core/bus/backup/Flash.zig

@@ -44,7 +44,7 @@ pub fn handleCommand(self: *Self, buf: []u8, byte: u8) void {
         0xB0 => self.set_bank = true,
         0x80 => self.prep_erase = true,
         0x10 => {
-            @memset(buf, 0xFF);
+            std.mem.set(u8, buf, 0xFF);
             self.prep_erase = false;
         },
         0xA0 => self.prep_write = true,
@@ -61,7 +61,7 @@ pub fn shouldEraseSector(self: *const Self, addr: usize, byte: u8) bool {
 pub fn erase(self: *Self, buf: []u8, sector: usize) void {
     const start = self.address() + (sector & 0xF000);
 
-    @memset(buf[start..][0..0x1000], 0xFF);
+    std.mem.set(u8, buf[start..][0..0x1000], 0xFF);
     self.prep_erase = false;
     self.state = .Ready;
 }

src/core/bus/backup/eeprom.zig

@@ -58,9 +58,7 @@ pub const Eeprom = struct {
                     log.err("Failed to resize EEPROM buf to {} bytes", .{len});
                     std.debug.panic("EEPROM entered irrecoverable state {}", .{e});
                 };
-
+                std.mem.set(u8, buf.*, 0xFF);
-                // FIXME: ptr to a slice?
-                @memset(buf.*, 0xFF);
             }
         }
 

src/core/bus/dma.zig

@@ -3,7 +3,7 @@ const util = @import("../../util.zig");
 
 const DmaControl = @import("io.zig").DmaControl;
 const Bus = @import("../Bus.zig");
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
 
 pub const DmaTuple = struct { DmaController(0), DmaController(1), DmaController(2), DmaController(3) };
 const log = std.log.scoped(.DmaTransfer);
@@ -11,7 +11,6 @@ const log = std.log.scoped(.DmaTransfer);
 const getHalf = util.getHalf;
 const setHalf = util.setHalf;
 const setQuart = util.setQuart;
-const handleInterrupt = @import("../cpu_util.zig").handleInterrupt;
 
 const rotr = @import("zba-util").rotr;
 
@@ -238,8 +237,6 @@ fn DmaController(comptime id: u2) type {
         }
 
         pub fn step(self: *Self, cpu: *Arm7tdmi) void {
-            const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
             const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11;
             const sad_adj = @intToEnum(Adjustment, self.cnt.sad_adj.read());
             const dad_adj = if (is_fifo) .Fixed else @intToEnum(Adjustment, self.cnt.dad_adj.read());
@@ -286,13 +283,13 @@ fn DmaController(comptime id: u2) type {
             if (self._word_count == 0) {
                 if (self.cnt.irq.read()) {
                     switch (id) {
-                        0 => bus_ptr.io.irq.dma0.set(),
+                        0 => cpu.bus.io.irq.dma0.set(),
-                        1 => bus_ptr.io.irq.dma1.set(),
+                        1 => cpu.bus.io.irq.dma1.set(),
-                        2 => bus_ptr.io.irq.dma2.set(),
+                        2 => cpu.bus.io.irq.dma2.set(),
-                        3 => bus_ptr.io.irq.dma3.set(),
+                        3 => cpu.bus.io.irq.dma3.set(),
                     }
 
-                    handleInterrupt(cpu);
+                    cpu.handleInterrupt();
                 }
 
                 // If we're not repeating, Fire the IRQs and disable the DMA

src/core/bus/gpio.zig

@@ -2,13 +2,9 @@ const std = @import("std");
 const Bit = @import("bitfield").Bit;
 const DateTime = @import("datetime").datetime.Datetime;
 
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
-const Bus = @import("../Bus.zig");
-const Scheduler = @import("../scheduler.zig").Scheduler;
 const Allocator = std.mem.Allocator;
 
-const handleInterrupt = @import("../cpu_util.zig").handleInterrupt;
-
 /// GPIO Register Implementation
 pub const Gpio = struct {
     const Self = @This();
@@ -290,13 +286,11 @@ pub const Clock = struct {
             .gpio = gpio, // Can't use Arm7tdmi ptr b/c not initialized yet
         };
 
-        const sched_ptr = @ptrCast(*Scheduler, @alignCast(@alignOf(Scheduler), cpu.sched.ptr));
+        cpu.sched.push(.RealTimeClock, 1 << 24); // Every Second
-        sched_ptr.push(.RealTimeClock, 1 << 24); // Every Second
     }
 
     pub fn onClockUpdate(self: *Self, late: u64) void {
-        const sched_ptr = @ptrCast(*Scheduler, @alignCast(@alignOf(Scheduler), self.cpu.sched.ptr));
+        self.cpu.sched.push(.RealTimeClock, (1 << 24) -| late); // Reschedule
-        sched_ptr.push(.RealTimeClock, (1 << 24) -| late); // Reschedule
 
         const now = DateTime.now();
         self.year = bcd(@intCast(u8, now.date.year - 2000));
@@ -403,13 +397,11 @@ pub const Clock = struct {
     }
 
     fn irq(self: *Self) void {
-        const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), self.cpu.bus.ptr));
-
         // TODO: Confirm that this is the right behaviour
         log.debug("Force GamePak IRQ", .{});
 
-        bus_ptr.io.irq.game_pak.set();
+        self.cpu.bus.io.irq.game_pak.set();
-        handleInterrupt(self.cpu);
+        self.cpu.handleInterrupt();
     }
 
     fn processCommand(self: *Self, raw_command: u8) State {

src/core/bus/io.zig

@@ -96,7 +96,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) ?T {
             0x0400_0128 => util.io.read.todo(log, "Read {} from SIOCNT", .{T}),
 
             // Keypad Input
-            0x0400_0130 => bus.io.keyinput.load(.Monotonic),
+            0x0400_0130 => bus.io.keyinput.load(.Monotonic).raw,
 
             // Serial Communication 2
             0x0400_0134 => util.io.read.todo(log, "Read {} from RCNT", .{T}),
@@ -366,7 +366,7 @@ const InterruptEnable = extern union {
 
 /// Read Only
 /// 0 = Pressed, 1 = Released
-pub const KeyInput = extern union {
+const KeyInput = extern union {
     a: Bit(u16, 0),
     b: Bit(u16, 1),
     select: Bit(u16, 2),
@@ -390,19 +390,18 @@ const AtomicKeyInput = struct {
         return .{ .inner = value };
     }
 
-    pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
+    pub inline fn load(self: *const Self, comptime ordering: Ordering) KeyInput {
-        return switch (ordering) {
+        return .{ .raw = switch (ordering) {
             .AcqRel, .Release => @compileError("not supported for atomic loads"),
             else => @atomicLoad(u16, &self.inner.raw, ordering),
-        };
+        } };
     }
 
-    pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
+    pub inline fn store(self: *Self, value: u16, comptime ordering: Ordering) void {
-        _ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
+        switch (ordering) {
-    }
+            .AcqRel, .Acquire => @compileError("not supported for atomic stores"),
-
+            else => @atomicStore(u16, &self.inner.raw, value, ordering),
-    pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
+        }
-        _ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
     }
 };
 

src/core/bus/timer.zig

@@ -3,10 +3,7 @@ const util = @import("../../util.zig");
 
 const TimerControl = @import("io.zig").TimerControl;
 const Scheduler = @import("../scheduler.zig").Scheduler;
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
-const Bus = @import("../Bus.zig");
-
-const handleInterrupt = @import("../cpu_util.zig").handleInterrupt;
 
 pub const TimerTuple = struct { Timer(0), Timer(1), Timer(2), Timer(3) };
 const log = std.log.scoped(.Timer);
@@ -194,9 +191,7 @@ fn Timer(comptime id: u2) type {
 
         pub fn onTimerExpire(self: *Self, cpu: *Arm7tdmi, late: u64) void {
             // Fire IRQ if enabled
-            const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
+            const io = &cpu.bus.io;
-
-            const io = &bus_ptr.io;
 
             if (self.cnt.irq.read()) {
                 switch (id) {
@@ -206,12 +201,12 @@ fn Timer(comptime id: u2) type {
                     3 => io.irq.tim3.set(),
                 }
 
-                handleInterrupt(cpu);
+                cpu.handleInterrupt();
             }
 
             // DMA Sound Things
             if (id == 0 or id == 1) {
-                bus_ptr.apu.onDmaAudioSampleRequest(cpu, id);
+                cpu.bus.apu.onDmaAudioSampleRequest(cpu, id);
             }
 
             // Perform Cascade Behaviour
@@ -219,9 +214,9 @@ fn Timer(comptime id: u2) type {
                 inline 0, 1, 2 => |idx| {
                     const next = idx + 1;
 
-                    if (bus_ptr.tim[next].cnt.cascade.read()) {
+                    if (cpu.bus.tim[next].cnt.cascade.read()) {
-                        bus_ptr.tim[next]._counter +%= 1;
+                        cpu.bus.tim[next]._counter +%= 1;
-                        if (bus_ptr.tim[next]._counter == 0) bus_ptr.tim[next].onTimerExpire(cpu, late);
+                        if (cpu.bus.tim[next]._counter == 0) cpu.bus.tim[next].onTimerExpire(cpu, late);
                     }
                 },
                 3 => {}, // THere is no timer for TIM3 to cascade to

src/core/cpu.zig

@@ -0,0 +1,681 @@
+const std = @import("std");
+
+const Bus = @import("Bus.zig");
+const Bit = @import("bitfield").Bit;
+const Bitfield = @import("bitfield").Bitfield;
+const Scheduler = @import("scheduler.zig").Scheduler;
+const Logger = @import("../util.zig").Logger;
+
+const File = std.fs.File;
+const log = std.log.scoped(.Arm7Tdmi);
+
+// ARM Instructions
+pub const arm = struct {
+    pub const InstrFn = *const fn (*Arm7tdmi, *Bus, u32) void;
+    const lut: [0x1000]InstrFn = populate();
+
+    const processing = @import("cpu/arm/data_processing.zig").dataProcessing;
+    const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
+    const transfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
+    const halfSignedTransfer = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
+    const blockTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
+    const branch = @import("cpu/arm/branch.zig").branch;
+    const branchExchange = @import("cpu/arm/branch.zig").branchAndExchange;
+    const swi = @import("cpu/arm/software_interrupt.zig").armSoftwareInterrupt;
+    const swap = @import("cpu/arm/single_data_swap.zig").singleDataSwap;
+
+    const multiply = @import("cpu/arm/multiply.zig").multiply;
+    const multiplyLong = @import("cpu/arm/multiply.zig").multiplyLong;
+
+    /// Determine index into ARM InstrFn LUT
+    fn idx(opcode: u32) u12 {
+        return @truncate(u12, opcode >> 20 & 0xFF) << 4 | @truncate(u12, opcode >> 4 & 0xF);
+    }
+
+    // Undefined ARM Instruction handler
+    fn und(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+        const id = idx(opcode);
+        cpu.panic("[CPU/Decode] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
+    }
+
+    fn populate() [0x1000]InstrFn {
+        comptime {
+            @setEvalBranchQuota(0xE000);
+            var table = [_]InstrFn{und} ** 0x1000;
+
+            for (&table, 0..) |*handler, i| {
+                handler.* = switch (@as(u2, i >> 10)) {
+                    0b00 => if (i == 0x121) blk: {
+                        break :blk branchExchange;
+                    } else if (i & 0xFCF == 0x009) blk: {
+                        const A = i >> 5 & 1 == 1;
+                        const S = i >> 4 & 1 == 1;
+                        break :blk multiply(A, S);
+                    } else if (i & 0xFBF == 0x109) blk: {
+                        const B = i >> 6 & 1 == 1;
+                        break :blk swap(B);
+                    } else if (i & 0xF8F == 0x089) blk: {
+                        const U = i >> 6 & 1 == 1;
+                        const A = i >> 5 & 1 == 1;
+                        const S = i >> 4 & 1 == 1;
+                        break :blk multiplyLong(U, A, S);
+                    } else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: {
+                        const P = i >> 8 & 1 == 1;
+                        const U = i >> 7 & 1 == 1;
+                        const I = i >> 6 & 1 == 1;
+                        const W = i >> 5 & 1 == 1;
+                        const L = i >> 4 & 1 == 1;
+                        break :blk halfSignedTransfer(P, U, I, W, L);
+                    } else if (i & 0xD90 == 0x100) blk: {
+                        const I = i >> 9 & 1 == 1;
+                        const R = i >> 6 & 1 == 1;
+                        const kind = i >> 4 & 0x3;
+                        break :blk psrTransfer(I, R, kind);
+                    } else blk: {
+                        const I = i >> 9 & 1 == 1;
+                        const S = i >> 4 & 1 == 1;
+                        const instrKind = i >> 5 & 0xF;
+                        break :blk processing(I, S, instrKind);
+                    },
+                    0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) und else blk: {
+                        const I = i >> 9 & 1 == 1;
+                        const P = i >> 8 & 1 == 1;
+                        const U = i >> 7 & 1 == 1;
+                        const B = i >> 6 & 1 == 1;
+                        const W = i >> 5 & 1 == 1;
+                        const L = i >> 4 & 1 == 1;
+                        break :blk transfer(I, P, U, B, W, L);
+                    },
+                    else => switch (@as(u2, i >> 9 & 0x3)) {
+                        // MSB is guaranteed to be 1
+                        0b00 => blk: {
+                            const P = i >> 8 & 1 == 1;
+                            const U = i >> 7 & 1 == 1;
+                            const S = i >> 6 & 1 == 1;
+                            const W = i >> 5 & 1 == 1;
+                            const L = i >> 4 & 1 == 1;
+                            break :blk blockTransfer(P, U, S, W, L);
+                        },
+                        0b01 => blk: {
+                            const L = i >> 8 & 1 == 1;
+                            break :blk branch(L);
+                        },
+                        0b10 => und, // COP Data Transfer
+                        0b11 => if (i >> 8 & 1 == 1) swi() else und, // COP Data Operation + Register Transfer
+                    },
+                };
+            }
+
+            return table;
+        }
+    }
+};
+
+// THUMB Instructions
+pub const thumb = struct {
+    pub const InstrFn = *const fn (*Arm7tdmi, *Bus, u16) void;
+    const lut: [0x400]InstrFn = populate();
+
+    const processing = @import("cpu/thumb/data_processing.zig");
+    const alu = @import("cpu/thumb/alu.zig").fmt4;
+    const transfer = @import("cpu/thumb/data_transfer.zig");
+    const block_transfer = @import("cpu/thumb/block_data_transfer.zig");
+    const swi = @import("cpu/thumb/software_interrupt.zig").fmt17;
+    const branch = @import("cpu/thumb/branch.zig");
+
+    /// Determine index into THUMB InstrFn LUT
+    fn idx(opcode: u16) u10 {
+        return @truncate(u10, opcode >> 6);
+    }
+
+    /// Undefined THUMB Instruction Handler
+    fn und(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+        const id = idx(opcode);
+        cpu.panic("[CPU/Decode] ID: 0b{b:0>10} 0x{X:0>2} is an illegal opcode", .{ id, opcode });
+    }
+
+    fn populate() [0x400]InstrFn {
+        comptime {
+            @setEvalBranchQuota(5025); // This is exact
+            var table = [_]InstrFn{und} ** 0x400;
+
+            for (&table, 0..) |*handler, i| {
+                handler.* = switch (@as(u3, i >> 7 & 0x7)) {
+                    0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
+                        const I = i >> 4 & 1 == 1;
+                        const is_sub = i >> 3 & 1 == 1;
+                        const rn = i & 0x7;
+                        break :blk processing.fmt2(I, is_sub, rn);
+                    } else blk: {
+                        const op = i >> 5 & 0x3;
+                        const offset = i & 0x1F;
+                        break :blk processing.fmt1(op, offset);
+                    },
+                    0b001 => blk: {
+                        const op = i >> 5 & 0x3;
+                        const rd = i >> 2 & 0x7;
+                        break :blk processing.fmt3(op, rd);
+                    },
+                    0b010 => switch (@as(u2, i >> 5 & 0x3)) {
+                        0b00 => if (i >> 4 & 1 == 1) blk: {
+                            const op = i >> 2 & 0x3;
+                            const h1 = i >> 1 & 1;
+                            const h2 = i & 1;
+                            break :blk processing.fmt5(op, h1, h2);
+                        } else blk: {
+                            const op = i & 0xF;
+                            break :blk alu(op);
+                        },
+                        0b01 => blk: {
+                            const rd = i >> 2 & 0x7;
+                            break :blk transfer.fmt6(rd);
+                        },
+                        else => blk: {
+                            const op = i >> 4 & 0x3;
+                            const T = i >> 3 & 1 == 1;
+                            break :blk transfer.fmt78(op, T);
+                        },
+                    },
+                    0b011 => blk: {
+                        const B = i >> 6 & 1 == 1;
+                        const L = i >> 5 & 1 == 1;
+                        const offset = i & 0x1F;
+                        break :blk transfer.fmt9(B, L, offset);
+                    },
+                    else => switch (@as(u3, i >> 6 & 0x7)) {
+                        // MSB is guaranteed to be 1
+                        0b000 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const offset = i & 0x1F;
+                            break :blk transfer.fmt10(L, offset);
+                        },
+                        0b001 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const rd = i >> 2 & 0x7;
+                            break :blk transfer.fmt11(L, rd);
+                        },
+                        0b010 => blk: {
+                            const isSP = i >> 5 & 1 == 1;
+                            const rd = i >> 2 & 0x7;
+                            break :blk processing.fmt12(isSP, rd);
+                        },
+                        0b011 => if (i >> 4 & 1 == 1) blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const R = i >> 2 & 1 == 1;
+                            break :blk block_transfer.fmt14(L, R);
+                        } else blk: {
+                            const S = i >> 1 & 1 == 1;
+                            break :blk processing.fmt13(S);
+                        },
+                        0b100 => blk: {
+                            const L = i >> 5 & 1 == 1;
+                            const rb = i >> 2 & 0x7;
+
+                            break :blk block_transfer.fmt15(L, rb);
+                        },
+                        0b101 => if (i >> 2 & 0xF == 0b1111) blk: {
+                            break :blk thumb.swi();
+                        } else blk: {
+                            const cond = i >> 2 & 0xF;
+                            break :blk branch.fmt16(cond);
+                        },
+                        0b110 => branch.fmt18(),
+                        0b111 => blk: {
+                            const is_low = i >> 5 & 1 == 1;
+                            break :blk branch.fmt19(is_low);
+                        },
+                    },
+                };
+            }
+
+            return table;
+        }
+    }
+};
+
+pub const Arm7tdmi = struct {
+    const Self = @This();
+
+    r: [16]u32,
+    pipe: Pipeline,
+    sched: *Scheduler,
+    bus: *Bus,
+    cpsr: PSR,
+    spsr: PSR,
+
+    bank: Bank,
+
+    logger: ?Logger,
+
+    /// Bank of Registers from other CPU Modes
+    const Bank = struct {
+        /// Storage for r13_<mode>, r14_<mode>
+        /// e.g. [r13, r14, r13_svc, r14_svc]
+        r: [2 * 6]u32,
+
+        /// Storage  for R8_fiq -> R12_fiq and their normal counterparts
+        /// e.g [r[0 + 8], fiq_r[0 + 8], r[1 + 8], fiq_r[1 + 8]...]
+        fiq: [2 * 5]u32,
+
+        spsr: [5]PSR,
+
+        const Kind = enum(u1) {
+            R13 = 0,
+            R14,
+        };
+
+        pub fn create() Bank {
+            return .{
+                .r = [_]u32{0x00} ** 12,
+                .fiq = [_]u32{0x00} ** 10,
+                .spsr = [_]PSR{.{ .raw = 0x0000_0000 }} ** 5,
+            };
+        }
+
+        inline fn regIdx(mode: Mode, kind: Kind) usize {
+            const idx: usize = switch (mode) {
+                .User, .System => 0,
+                .Supervisor => 1,
+                .Abort => 2,
+                .Undefined => 3,
+                .Irq => 4,
+                .Fiq => 5,
+            };
+
+            return (idx * 2) + if (kind == .R14) @as(usize, 1) else 0;
+        }
+
+        inline fn spsrIdx(mode: Mode) usize {
+            return switch (mode) {
+                .Supervisor => 0,
+                .Abort => 1,
+                .Undefined => 2,
+                .Irq => 3,
+                .Fiq => 4,
+                else => std.debug.panic("[CPU/Mode] {} does not have a SPSR Register", .{mode}),
+            };
+        }
+
+        inline fn fiqIdx(i: usize, mode: Mode) usize {
+            return (i * 2) + if (mode == .Fiq) @as(usize, 1) else 0;
+        }
+    };
+
+    pub fn init(sched: *Scheduler, bus: *Bus, log_file: ?std.fs.File) Self {
+        return Self{
+            .r = [_]u32{0x00} ** 16,
+            .pipe = Pipeline.init(),
+            .sched = sched,
+            .bus = bus,
+            .cpsr = .{ .raw = 0x0000_001F },
+            .spsr = .{ .raw = 0x0000_0000 },
+            .bank = Bank.create(),
+            .logger = if (log_file) |file| Logger.init(file) else null,
+        };
+    }
+
+    // FIXME: Resetting disables logging (if enabled)
+    pub fn reset(self: *Self) void {
+        const bus_ptr = self.bus;
+        const scheduler_ptr = self.sched;
+
+        self.* = Self.init(scheduler_ptr, bus_ptr, null);
+    }
+
+    pub inline fn hasSPSR(self: *const Self) bool {
+        const mode = getModeChecked(self, self.cpsr.mode.read());
+        return switch (mode) {
+            .System, .User => false,
+            else => true,
+        };
+    }
+
+    pub inline fn isPrivileged(self: *const Self) bool {
+        const mode = getModeChecked(self, self.cpsr.mode.read());
+        return switch (mode) {
+            .User => false,
+            else => true,
+        };
+    }
+
+    pub inline fn isHalted(self: *const Self) bool {
+        return self.bus.io.haltcnt == .Halt;
+    }
+
+    pub fn setCpsr(self: *Self, value: u32) void {
+        if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+        self.cpsr.raw = value;
+    }
+
+    fn changeModeFromIdx(self: *Self, next: u5) void {
+        self.changeMode(getModeChecked(self, next));
+    }
+
+    pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
+        const current = getModeChecked(self, self.cpsr.mode.read());
+
+        switch (idx) {
+            8...12 => {
+                if (current == .Fiq) {
+                    self.bank.fiq[Bank.fiqIdx(idx - 8, .User)] = value;
+                } else self.r[idx] = value;
+            },
+            13, 14 => switch (current) {
+                .User, .System => self.r[idx] = value,
+                else => {
+                    const kind = std.meta.intToEnum(Bank.Kind, idx - 13) catch unreachable;
+                    self.bank.r[Bank.regIdx(.User, kind)] = value;
+                },
+            },
+            else => self.r[idx] = value, // R0 -> R7  and R15
+        }
+    }
+
+    pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
+        const current = getModeChecked(self, self.cpsr.mode.read());
+
+        return switch (idx) {
+            8...12 => if (current == .Fiq) self.bank.fiq[Bank.fiqIdx(idx - 8, .User)] else self.r[idx],
+            13, 14 => switch (current) {
+                .User, .System => self.r[idx],
+                else => blk: {
+                    const kind = std.meta.intToEnum(Bank.Kind, idx - 13) catch unreachable;
+                    break :blk self.bank.r[Bank.regIdx(.User, kind)];
+                },
+            },
+            else => self.r[idx], // R0 -> R7  and R15
+        };
+    }
+
+    pub fn changeMode(self: *Self, next: Mode) void {
+        const now = getModeChecked(self, self.cpsr.mode.read());
+
+        // Bank R8 -> r12
+        for (0..5) |i| {
+            self.bank.fiq[Bank.fiqIdx(i, now)] = self.r[8 + i];
+        }
+
+        // Bank r13, r14, SPSR
+        switch (now) {
+            .User, .System => {
+                self.bank.r[Bank.regIdx(now, .R13)] = self.r[13];
+                self.bank.r[Bank.regIdx(now, .R14)] = self.r[14];
+            },
+            else => {
+                self.bank.r[Bank.regIdx(now, .R13)] = self.r[13];
+                self.bank.r[Bank.regIdx(now, .R14)] = self.r[14];
+                self.bank.spsr[Bank.spsrIdx(now)] = self.spsr;
+            },
+        }
+
+        // Grab R8 -> R12
+        for (0..5) |i| {
+            self.r[8 + i] = self.bank.fiq[Bank.fiqIdx(i, next)];
+        }
+
+        // Grab r13, r14, SPSR
+        switch (next) {
+            .User, .System => {
+                self.r[13] = self.bank.r[Bank.regIdx(next, .R13)];
+                self.r[14] = self.bank.r[Bank.regIdx(next, .R14)];
+            },
+            else => {
+                self.r[13] = self.bank.r[Bank.regIdx(next, .R13)];
+                self.r[14] = self.bank.r[Bank.regIdx(next, .R14)];
+                self.spsr = self.bank.spsr[Bank.spsrIdx(next)];
+            },
+        }
+
+        self.cpsr.mode.write(@enumToInt(next));
+    }
+
+    /// Advances state so that the BIOS is skipped
+    ///
+    /// Note: This accesses the CPU's bus ptr so it only may be called
+    /// once the Bus has been properly initialized
+    ///
+    /// TODO: Make above notice impossible to do in code
+    pub fn fastBoot(self: *Self) void {
+        self.r = std.mem.zeroes([16]u32);
+
+        // self.r[0] = 0x08000000;
+        // self.r[1] = 0x000000EA;
+        self.r[13] = 0x0300_7F00;
+        self.r[15] = 0x0800_0000;
+
+        self.bank.r[Bank.regIdx(.Irq, .R13)] = 0x0300_7FA0;
+        self.bank.r[Bank.regIdx(.Supervisor, .R13)] = 0x0300_7FE0;
+
+        // self.cpsr.raw = 0x6000001F;
+        self.cpsr.raw = 0x0000_001F;
+
+        self.bus.bios.addr_latch = 0x0000_00DC + 8;
+    }
+
+    pub fn step(self: *Self) void {
+        defer {
+            if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+            self.pipe.flushed = false;
+        }
+
+        if (self.cpsr.t.read()) {
+            const opcode = @truncate(u16, self.pipe.step(self, u16) orelse return);
+            if (self.logger) |*trace| trace.mgbaLog(self, opcode);
+
+            thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
+        } else {
+            const opcode = self.pipe.step(self, u32) orelse return;
+            if (self.logger) |*trace| trace.mgbaLog(self, opcode);
+
+            if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
+                arm.lut[arm.idx(opcode)](self, self.bus, opcode);
+            }
+        }
+    }
+
+    pub fn stepDmaTransfer(self: *Self) bool {
+        inline for (0..4) |i| {
+            if (self.bus.dma[i].in_progress) {
+                self.bus.dma[i].step(self);
+                return true;
+            }
+        }
+
+        return false;
+    }
+
+    pub fn handleInterrupt(self: *Self) void {
+        const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
+
+        // Return if IME is disabled, CPSR I is set or there is nothing to handle
+        if (!self.bus.io.ime or self.cpsr.i.read() or should_handle == 0) return;
+
+        // If Pipeline isn't full, we have a bug
+        std.debug.assert(self.pipe.isFull());
+
+        // log.debug("Handling Interrupt!", .{});
+        self.bus.io.haltcnt = .Execute;
+
+        // FIXME: This seems weird, but retAddr.gba suggests I need to make these changes
+        const ret_addr = self.r[15] - if (self.cpsr.t.read()) 0 else @as(u32, 4);
+        const new_spsr = self.cpsr.raw;
+
+        self.changeMode(.Irq);
+        self.cpsr.t.write(false);
+        self.cpsr.i.write(true);
+
+        self.r[14] = ret_addr;
+        self.spsr.raw = new_spsr;
+        self.r[15] = 0x0000_0018;
+        self.pipe.reload(self);
+    }
+
+    inline fn fetch(self: *Self, comptime T: type, address: u32) T {
+        comptime std.debug.assert(T == u32 or T == u16); // Opcode may be 32-bit (ARM) or 16-bit (THUMB)
+
+        // Bus.read will advance the scheduler. There are different timings for CPU fetches,
+        // so we want to undo what Bus.read will apply. We can do this by caching the current tick
+        // This is very dumb.
+        //
+        // FIXME: Please rework this
+        const tick_cache = self.sched.tick;
+        defer self.sched.tick = tick_cache + Bus.fetch_timings[@boolToInt(T == u32)][@truncate(u4, address >> 24)];
+
+        return self.bus.read(T, address);
+    }
+
+    pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
+        var i: usize = 0;
+        while (i < 16) : (i += 4) {
+            const i_1 = i + 1;
+            const i_2 = i + 2;
+            const i_3 = i + 3;
+            std.debug.print("R{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\n", .{ i, self.r[i], i_1, self.r[i_1], i_2, self.r[i_2], i_3, self.r[i_3] });
+        }
+        std.debug.print("cpsr: 0x{X:0>8} ", .{self.cpsr.raw});
+        self.cpsr.toString();
+
+        std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
+        self.spsr.toString();
+
+        std.debug.print("pipeline: {??X:0>8}\n", .{self.pipe.stage});
+
+        if (self.cpsr.t.read()) {
+            const opcode = self.bus.dbgRead(u16, self.r[15] - 4);
+            const id = thumb.idx(opcode);
+            std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
+        } else {
+            const opcode = self.bus.dbgRead(u32, self.r[15] - 4);
+            const id = arm.idx(opcode);
+            std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
+        }
+
+        std.debug.print("tick: {}\n\n", .{self.sched.tick});
+
+        std.debug.panic(format, args);
+    }
+};
+
+const condition_lut = [_]u16{
+    0xF0F0, // EQ - Equal
+    0x0F0F, // NE - Not Equal
+    0xCCCC, // CS - Unsigned higher or same
+    0x3333, // CC - Unsigned lower
+    0xFF00, // MI - Negative
+    0x00FF, // PL - Positive or Zero
+    0xAAAA, // VS - Overflow
+    0x5555, // VC - No Overflow
+    0x0C0C, // HI - unsigned hierh
+    0xF3F3, // LS - unsigned lower or same
+    0xAA55, // GE - greater or equal
+    0x55AA, // LT - less than
+    0x0A05, // GT - greater than
+    0xF5FA, // LE - less than or equal
+    0xFFFF, // AL - always
+    0x0000, // NV - never
+};
+
+pub inline fn checkCond(cpsr: PSR, cond: u4) bool {
+    const flags = @truncate(u4, cpsr.raw >> 28);
+
+    return condition_lut[cond] & (@as(u16, 1) << flags) != 0;
+}
+
+const Pipeline = struct {
+    const Self = @This();
+    stage: [2]?u32,
+    flushed: bool,
+
+    fn init() Self {
+        return .{
+            .stage = [_]?u32{null} ** 2,
+            .flushed = false,
+        };
+    }
+
+    pub fn isFull(self: *const Self) bool {
+        return self.stage[0] != null and self.stage[1] != null;
+    }
+
+    pub fn step(self: *Self, cpu: *Arm7tdmi, comptime T: type) ?u32 {
+        comptime std.debug.assert(T == u32 or T == u16);
+
+        const opcode = self.stage[0];
+        self.stage[0] = self.stage[1];
+        self.stage[1] = cpu.fetch(T, cpu.r[15]);
+
+        return opcode;
+    }
+
+    pub fn reload(self: *Self, cpu: *Arm7tdmi) void {
+        if (cpu.cpsr.t.read()) {
+            self.stage[0] = cpu.fetch(u16, cpu.r[15]);
+            self.stage[1] = cpu.fetch(u16, cpu.r[15] + 2);
+            cpu.r[15] += 4;
+        } else {
+            self.stage[0] = cpu.fetch(u32, cpu.r[15]);
+            self.stage[1] = cpu.fetch(u32, cpu.r[15] + 4);
+            cpu.r[15] += 8;
+        }
+
+        self.flushed = true;
+    }
+};
+
+pub const PSR = extern union {
+    mode: Bitfield(u32, 0, 5),
+    t: Bit(u32, 5),
+    f: Bit(u32, 6),
+    i: Bit(u32, 7),
+    v: Bit(u32, 28),
+    c: Bit(u32, 29),
+    z: Bit(u32, 30),
+    n: Bit(u32, 31),
+    raw: u32,
+
+    fn toString(self: PSR) void {
+        std.debug.print("[", .{});
+
+        if (self.n.read()) std.debug.print("N", .{}) else std.debug.print("-", .{});
+        if (self.z.read()) std.debug.print("Z", .{}) else std.debug.print("-", .{});
+        if (self.c.read()) std.debug.print("C", .{}) else std.debug.print("-", .{});
+        if (self.v.read()) std.debug.print("V", .{}) else std.debug.print("-", .{});
+        if (self.i.read()) std.debug.print("I", .{}) else std.debug.print("-", .{});
+        if (self.f.read()) std.debug.print("F", .{}) else std.debug.print("-", .{});
+        if (self.t.read()) std.debug.print("T", .{}) else std.debug.print("-", .{});
+        std.debug.print("|", .{});
+        if (getMode(self.mode.read())) |m| std.debug.print("{s}", .{m.toString()}) else std.debug.print("---", .{});
+
+        std.debug.print("]\n", .{});
+    }
+};
+
+pub const Mode = enum(u5) {
+    User = 0b10000,
+    Fiq = 0b10001,
+    Irq = 0b10010,
+    Supervisor = 0b10011,
+    Abort = 0b10111,
+    Undefined = 0b11011,
+    System = 0b11111,
+
+    pub fn toString(self: Mode) []const u8 {
+        return switch (self) {
+            .User => "usr",
+            .Fiq => "fiq",
+            .Irq => "irq",
+            .Supervisor => "svc",
+            .Abort => "abt",
+            .Undefined => "und",
+            .System => "sys",
+        };
+    }
+};
+
+fn getMode(bits: u5) ?Mode {
+    return std.meta.intToEnum(Mode, bits) catch null;
+}
+
+fn getModeChecked(cpu: *const Arm7tdmi, bits: u5) Mode {
+    return getMode(bits) orelse cpu.panic("[CPU/CPSR] 0b{b:0>5} is an invalid CPU mode", .{bits});
+}

src/core/cpu/arm/block_data_transfer.zig

@@ -0,0 +1,111 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+
+pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+            const rn = @truncate(u4, opcode >> 16 & 0xF);
+            const rlist = opcode & 0xFFFF;
+            const r15 = rlist >> 15 & 1 == 1;
+
+            var count: u32 = 0;
+            var i: u5 = 0;
+            var first: u4 = 0;
+            var write_to_base = true;
+
+            while (i < 16) : (i += 1) {
+                const r = @truncate(u4, 15 - i);
+                if (rlist >> r & 1 == 1) {
+                    first = r;
+                    count += 1;
+                }
+            }
+
+            var start = cpu.r[rn];
+            if (U) {
+                start += if (P) 4 else 0;
+            } else {
+                start = start - (4 * count) + if (!P) 4 else 0;
+            }
+
+            var end = cpu.r[rn];
+            if (U) {
+                end = end + (4 * count) - if (!P) 4 else 0;
+            } else {
+                end -= if (P) 4 else 0;
+            }
+
+            var new_base = cpu.r[rn];
+            if (U) {
+                new_base += 4 * count;
+            } else {
+                new_base -= 4 * count;
+            }
+
+            var address = start;
+
+            if (rlist == 0) {
+                var und_addr = cpu.r[rn];
+                if (U) {
+                    und_addr += if (P) 4 else 0;
+                } else {
+                    und_addr -= 0x40 - if (!P) 4 else 0;
+                }
+
+                if (L) {
+                    cpu.r[15] = bus.read(u32, und_addr);
+                    cpu.pipe.reload(cpu);
+                } else {
+                    bus.write(u32, und_addr, cpu.r[15] + 4);
+                }
+
+                cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
+                return;
+            }
+
+            i = first;
+            while (i < 16) : (i += 1) {
+                if (rlist >> i & 1 == 1) {
+                    transfer(cpu, bus, r15, i, address);
+                    address += 4;
+
+                    if (W and !L and write_to_base) {
+                        cpu.r[rn] = new_base;
+                        write_to_base = false;
+                    }
+                }
+            }
+
+            if (W and L and rlist >> rn & 1 == 0) cpu.r[rn] = new_base;
+        }
+
+        fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void {
+            if (L) {
+                if (S and !r15_present) {
+                    // Always Transfer User mode Registers
+                    cpu.setUserModeRegister(i, bus.read(u32, address));
+                } else {
+                    const value = bus.read(u32, address);
+
+                    cpu.r[i] = value;
+                    if (i == 0xF) {
+                        cpu.r[i] &= ~@as(u32, 3); // Align r15
+                        cpu.pipe.reload(cpu);
+
+                        if (S) cpu.setCpsr(cpu.spsr.raw);
+                    }
+                }
+            } else {
+                if (S) {
+                    // Always Transfer User mode Registers
+                    // This happens regardless if r15 is in the list
+                    const value = cpu.getUserModeRegister(i);
+                    bus.write(u32, address, value + if (i == 0xF) 4 else @as(u32, 0)); // PC is already 8 ahead to make 12
+                } else {
+                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 4 else @as(u32, 0));
+                }
+            }
+        }
+    }.inner;
+}

src/core/cpu/arm/branch.zig

@@ -0,0 +1,26 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+
+const sext = @import("zba-util").sext;
+
+pub fn branch(comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            if (L) cpu.r[14] = cpu.r[15] - 4;
+
+            cpu.r[15] +%= sext(u32, u24, opcode) << 2;
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}
+
+pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+    const rn = opcode & 0xF;
+
+    const thumb = cpu.r[rn] & 1 == 1;
+    cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
+
+    cpu.cpsr.t.write(thumb);
+    cpu.pipe.reload(cpu);
+}

src/core/cpu/arm/data_processing.zig

@@ -0,0 +1,185 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+
+const exec = @import("../barrel_shifter.zig").exec;
+const ror = @import("../barrel_shifter.zig").ror;
+
+pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            const rd = @truncate(u4, opcode >> 12 & 0xF);
+            const rn = opcode >> 16 & 0xF;
+            const old_carry = @boolToInt(cpu.cpsr.c.read());
+
+            // If certain conditions are met, PC is 12 ahead instead of 8
+            // TODO: Why these conditions?
+            if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
+            const op1 = cpu.r[rn];
+
+            const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
+            const op2 = if (I) ror(S, &cpu.cpsr, opcode & 0xFF, amount) else exec(S, cpu, opcode);
+
+            // Undo special condition from above
+            if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
+
+            var result: u32 = undefined;
+            var overflow: u1 = undefined;
+
+            // Perform Data Processing Logic
+            switch (kind) {
+                0x0 => result = op1 & op2, // AND
+                0x1 => result = op1 ^ op2, // EOR
+                0x2 => result = op1 -% op2, // SUB
+                0x3 => result = op2 -% op1, // RSB
+                0x4 => result = add(&overflow, op1, op2), // ADD
+                0x5 => result = adc(&overflow, op1, op2, old_carry), // ADC
+                0x6 => result = sbc(op1, op2, old_carry), // SBC
+                0x7 => result = sbc(op2, op1, old_carry), // RSC
+                0x8 => {
+                    // TST
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    result = op1 & op2;
+                },
+                0x9 => {
+                    // TEQ
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    result = op1 ^ op2;
+                },
+                0xA => {
+                    // CMP
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    result = op1 -% op2;
+                },
+                0xB => {
+                    // CMN
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    const tmp = @addWithOverflow(op1, op2);
+                    result = tmp[0];
+                    overflow = tmp[1];
+                },
+                0xC => result = op1 | op2, // ORR
+                0xD => result = op2, // MOV
+                0xE => result = op1 & ~op2, // BIC
+                0xF => result = ~op2, // MVN
+            }
+
+            // Write to Destination Register
+            switch (kind) {
+                0x8, 0x9, 0xA, 0xB => {}, // Test Operations
+                else => {
+                    cpu.r[rd] = result;
+                    if (rd == 0xF) {
+                        if (S) cpu.setCpsr(cpu.spsr.raw);
+                        cpu.pipe.reload(cpu);
+                    }
+                },
+            }
+
+            // Write Flags
+            switch (kind) {
+                0x0, 0x1, 0xC, 0xD, 0xE, 0xF => if (S and rd != 0xF) {
+                    // Logic Operation Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // C set by Barrel Shifter, V is unaffected
+
+                },
+                0x2, 0x3 => if (S and rd != 0xF) {
+                    // SUB, RSB Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0x2) {
+                        // SUB specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // RSB Specific
+                        cpu.cpsr.c.write(op1 <= op2);
+                        cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
+                0x4, 0x5 => if (S and rd != 0xF) {
+                    // ADD, ADC Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(overflow == 0b1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0x6, 0x7 => if (S and rd != 0xF) {
+                    // SBC, RSC Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0x6) {
+                        // SBC specific
+                        const subtrahend = @as(u64, op2) -% old_carry +% 1;
+                        cpu.cpsr.c.write(subtrahend <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // RSC Specific
+                        const subtrahend = @as(u64, op1) -% old_carry +% 1;
+                        cpu.cpsr.c.write(subtrahend <= op2);
+                        cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
+                0x8, 0x9, 0xA, 0xB => {
+                    // Test Operation Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0xA) {
+                        // CMP specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else if (kind == 0xB) {
+                        // CMN specific
+                        cpu.cpsr.c.write(overflow == 0b1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // TST, TEQ specific
+                        // Barrel Shifter should always calc CPSR C in TST
+                        if (!S) _ = exec(true, cpu, opcode);
+                    }
+                },
+            }
+        }
+    }.inner;
+}
+
+pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
+    // TODO: Make your own version (thanks peach.bot)
+    const subtrahend = @as(u64, right) -% old_carry +% 1;
+    const ret = @truncate(u32, left -% subtrahend);
+
+    return ret;
+}
+
+pub fn add(overflow: *u1, left: u32, right: u32) u32 {
+    const ret = @addWithOverflow(left, right);
+    overflow.* = ret[1];
+
+    return ret[0];
+}
+
+pub fn adc(overflow: *u1, left: u32, right: u32, old_carry: u1) u32 {
+    const tmp = @addWithOverflow(left, right);
+    const ret = @addWithOverflow(tmp[0], old_carry);
+    overflow.* = tmp[1] | ret[1];
+
+    return ret[0];
+}
+
+fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
+    @setCold(true);
+    cpu.setCpsr(cpu.spsr.raw);
+}

src/core/cpu/arm/half_signed_data_transfer.zig

@@ -0,0 +1,53 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+
+const sext = @import("zba-util").sext;
+const rotr = @import("zba-util").rotr;
+
+pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+            const rm = opcode & 0xF;
+            const imm_offset_high = opcode >> 8 & 0xF;
+
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
+            const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
+
+            const modified_base = if (U) base +% offset else base -% offset;
+            var address = if (P) modified_base else base;
+
+            var result: u32 = undefined;
+            if (L) {
+                switch (@truncate(u2, opcode >> 5)) {
+                    0b01 => {
+                        // LDRH
+                        const value = bus.read(u16, address);
+                        result = rotr(u32, value, 8 * (address & 1));
+                    },
+                    0b10 => {
+                        // LDRSB
+                        result = sext(u32, u8, bus.read(u8, address));
+                    },
+                    0b11 => {
+                        // LDRSH
+                        const value = bus.read(u16, address);
+                        result = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value);
+                    },
+                    0b00 => unreachable, // SWP
+                }
+            } else {
+                if (opcode >> 5 & 0x01 == 0x01) {
+                    // STRH
+                    bus.write(u16, address, @truncate(u16, cpu.r[rd]));
+                } else unreachable; // SWP
+            }
+
+            address = modified_base;
+            if (W and P or !P) cpu.r[rn] = address;
+            if (L) cpu.r[rd] = result; // // This emulates the LDR rd == rn behaviour
+        }
+    }.inner;
+}

src/core/cpu/arm/multiply.zig

@@ -0,0 +1,57 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+
+pub fn multiply(comptime A: bool, comptime S: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            const rd = opcode >> 16 & 0xF;
+            const rn = opcode >> 12 & 0xF;
+            const rs = opcode >> 8 & 0xF;
+            const rm = opcode & 0xF;
+
+            const temp: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]) + if (A) cpu.r[rn] else 0;
+            const result = @truncate(u32, temp);
+            cpu.r[rd] = result;
+
+            if (S) {
+                cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                cpu.cpsr.z.write(result == 0);
+                // V is unaffected, C is *actually* undefined in ARMv4
+            }
+        }
+    }.inner;
+}
+
+pub fn multiplyLong(comptime U: bool, comptime A: bool, comptime S: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            const rd_hi = opcode >> 16 & 0xF;
+            const rd_lo = opcode >> 12 & 0xF;
+            const rs = opcode >> 8 & 0xF;
+            const rm = opcode & 0xF;
+
+            if (U) {
+                // Signed (WHY IS IT U THEN?)
+                var result: i64 = @as(i64, @bitCast(i32, cpu.r[rm])) * @as(i64, @bitCast(i32, cpu.r[rs]));
+                if (A) result +%= @bitCast(i64, @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]));
+
+                cpu.r[rd_hi] = @bitCast(u32, @truncate(i32, result >> 32));
+                cpu.r[rd_lo] = @bitCast(u32, @truncate(i32, result));
+            } else {
+                // Unsigned
+                var result: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]);
+                if (A) result +%= @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]);
+
+                cpu.r[rd_hi] = @truncate(u32, result >> 32);
+                cpu.r[rd_lo] = @truncate(u32, result);
+            }
+
+            if (S) {
+                cpu.cpsr.z.write(cpu.r[rd_hi] == 0 and cpu.r[rd_lo] == 0);
+                cpu.cpsr.n.write(cpu.r[rd_hi] >> 31 & 1 == 1);
+                // C and V are set to meaningless values
+            }
+        }
+    }.inner;
+}

src/core/cpu/arm/psr_transfer.zig

@@ -0,0 +1,59 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+const PSR = @import("../../cpu.zig").PSR;
+
+const log = std.log.scoped(.PsrTransfer);
+
+const rotr = @import("zba-util").rotr;
+
+pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            switch (kind) {
+                0b00 => {
+                    // MRS
+                    const rd = opcode >> 12 & 0xF;
+
+                    if (R and !cpu.hasSPSR()) log.err("Tried to read SPSR from User/System Mode", .{});
+                    cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw;
+                },
+                0b10 => {
+                    // MSR
+                    const field_mask = @truncate(u4, opcode >> 16 & 0xF);
+                    const rm_idx = opcode & 0xF;
+                    const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) * 2) else cpu.r[rm_idx];
+
+                    if (R and !cpu.hasSPSR()) log.err("Tried to write to SPSR in User/System Mode", .{});
+
+                    if (R) {
+                        // arm.gba seems to expect the SPSR to do somethign in SYS mode,
+                        // so we just assume that despite writing to the SPSR in USR or SYS mode
+                        // being UNPREDICTABLE, it just magically has a working SPSR somehow
+                        cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);
+                    } else {
+                        if (cpu.isPrivileged()) cpu.setCpsr(fieldMask(&cpu.cpsr, field_mask, right));
+                    }
+                },
+                else => cpu.panic("[CPU/PSR Transfer] Bits 21:220 of {X:0>8} are undefined", .{opcode}),
+            }
+        }
+    }.inner;
+}
+
+fn fieldMask(psr: *const PSR, field_mask: u4, right: u32) u32 {
+    // This bitwise ORs bits 3 and 0 of the field mask into a u2
+    // We do this because we only care about bits 7:0 and 31:28 of the CPSR
+    const bits = @truncate(u2, (field_mask >> 2 & 0x2) | (field_mask & 1));
+
+    const mask: u32 = switch (bits) {
+        0b00 => 0x0000_0000,
+        0b01 => 0x0000_00FF,
+        0b10 => 0xF000_0000,
+        0b11 => 0xF000_00FF,
+    };
+
+    return (psr.raw & ~mask) | (right & mask);
+}

src/core/cpu/arm/single_data_swap.zig

@@ -0,0 +1,29 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+
+const rotr = @import("zba-util").rotr;
+
+pub fn singleDataSwap(comptime B: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+            const rm = opcode & 0xF;
+
+            const address = cpu.r[rn];
+
+            if (B) {
+                // SWPB
+                const value = bus.read(u8, address);
+                bus.write(u8, address, @truncate(u8, cpu.r[rm]));
+                cpu.r[rd] = value;
+            } else {
+                // SWP
+                const value = rotr(u32, bus.read(u32, address), 8 * (address & 0x3));
+                bus.write(u32, address, cpu.r[rm]);
+                cpu.r[rd] = value;
+            }
+        }
+    }.inner;
+}

src/core/cpu/arm/single_data_transfer.zig

@@ -0,0 +1,55 @@
+const shifter = @import("../barrel_shifter.zig");
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+
+const rotr = @import("zba-util").rotr;
+
+pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+
+            const base = cpu.r[rn];
+            const offset = if (I) shifter.immediate(false, cpu, opcode) else opcode & 0xFFF;
+
+            const modified_base = if (U) base +% offset else base -% offset;
+            var address = if (P) modified_base else base;
+
+            var result: u32 = undefined;
+            if (L) {
+                if (B) {
+                    // LDRB
+                    result = bus.read(u8, address);
+                } else {
+                    // LDR
+                    const value = bus.read(u32, address);
+                    result = rotr(u32, value, 8 * (address & 0x3));
+                }
+            } else {
+                if (B) {
+                    // STRB
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
+                    bus.write(u8, address, @truncate(u8, value));
+                } else {
+                    // STR
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);
+                    bus.write(u32, address, value);
+                }
+            }
+
+            address = modified_base;
+            if (W and P or !P) {
+                cpu.r[rn] = address;
+                if (rn == 0xF) cpu.pipe.reload(cpu);
+            }
+
+            if (L) {
+                // This emulates the LDR rd == rn behaviour
+                cpu.r[rd] = result;
+                if (rd == 0xF) cpu.pipe.reload(cpu);
+            }
+        }
+    }.inner;
+}

src/core/cpu/arm/software_interrupt.zig

@@ -0,0 +1,23 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").arm.InstrFn;
+
+pub fn armSoftwareInterrupt() InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
+            // Copy Values from Current Mode
+            const ret_addr = cpu.r[15] - 4;
+            const cpsr = cpu.cpsr.raw;
+
+            // Switch Mode
+            cpu.changeMode(.Supervisor);
+            cpu.cpsr.t.write(false); // Force ARM Mode
+            cpu.cpsr.i.write(true); // Disable normal interrupts
+
+            cpu.r[14] = ret_addr; // Resume Execution
+            cpu.spsr.raw = cpsr; // Previous mode CPSR
+            cpu.r[15] = 0x0000_0008;
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}

src/core/cpu/barrel_shifter.zig

@@ -0,0 +1,147 @@
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const CPSR = @import("../cpu.zig").PSR;
+
+const rotr = @import("zba-util").rotr;
+
+pub fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
+    var result: u32 = undefined;
+    if (opcode >> 4 & 1 == 1) {
+        result = register(S, cpu, opcode);
+    } else {
+        result = immediate(S, cpu, opcode);
+    }
+
+    return result;
+}
+
+fn register(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
+    const rs_idx = opcode >> 8 & 0xF;
+    const rm = cpu.r[opcode & 0xF];
+    const rs = @truncate(u8, cpu.r[rs_idx]);
+
+    return switch (@truncate(u2, opcode >> 5)) {
+        0b00 => lsl(S, &cpu.cpsr, rm, rs),
+        0b01 => lsr(S, &cpu.cpsr, rm, rs),
+        0b10 => asr(S, &cpu.cpsr, rm, rs),
+        0b11 => ror(S, &cpu.cpsr, rm, rs),
+    };
+}
+
+pub fn immediate(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
+    const amount = @truncate(u8, opcode >> 7 & 0x1F);
+    const rm = cpu.r[opcode & 0xF];
+
+    var result: u32 = undefined;
+    if (amount == 0) {
+        switch (@truncate(u2, opcode >> 5)) {
+            0b00 => {
+                // LSL #0
+                result = rm;
+            },
+            0b01 => {
+                // LSR #0 aka LSR #32
+                if (S) cpu.cpsr.c.write(rm >> 31 & 1 == 1);
+                result = 0x0000_0000;
+            },
+            0b10 => {
+                // ASR #0 aka ASR #32
+                result = @bitCast(u32, @bitCast(i32, rm) >> 31);
+                if (S) cpu.cpsr.c.write(result >> 31 & 1 == 1);
+            },
+            0b11 => {
+                // ROR #0 aka RRX
+                const carry: u32 = @boolToInt(cpu.cpsr.c.read());
+                if (S) cpu.cpsr.c.write(rm & 1 == 1);
+
+                result = (carry << 31) | (rm >> 1);
+            },
+        }
+    } else {
+        switch (@truncate(u2, opcode >> 5)) {
+            0b00 => result = lsl(S, &cpu.cpsr, rm, amount),
+            0b01 => result = lsr(S, &cpu.cpsr, rm, amount),
+            0b10 => result = asr(S, &cpu.cpsr, rm, amount),
+            0b11 => result = ror(S, &cpu.cpsr, rm, amount),
+        }
+    }
+
+    return result;
+}
+
+pub fn lsl(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
+    const amount = @truncate(u5, total_amount);
+    const bit_count: u8 = @typeInfo(u32).Int.bits;
+
+    var result: u32 = 0x0000_0000;
+    if (total_amount < bit_count) {
+        // We can perform a well-defined shift here
+        result = rm << amount;
+
+        if (S and total_amount != 0) {
+            const carry_bit = @truncate(u5, bit_count - amount);
+            cpsr.c.write(rm >> carry_bit & 1 == 1);
+        }
+    } else {
+        if (S) {
+            if (total_amount == bit_count) {
+                // Shifted all bits out, carry bit is bit 0 of rm
+                cpsr.c.write(rm & 1 == 1);
+            } else {
+                cpsr.c.write(false);
+            }
+        }
+    }
+
+    return result;
+}
+
+pub fn lsr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 {
+    const amount = @truncate(u5, total_amount);
+    const bit_count: u8 = @typeInfo(u32).Int.bits;
+
+    var result: u32 = 0x0000_0000;
+    if (total_amount < bit_count) {
+        // We can perform a well-defined shift
+        result = rm >> amount;
+        if (S and total_amount != 0) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
+    } else {
+        if (S) {
+            if (total_amount == bit_count) {
+                // LSR #32
+                cpsr.c.write(rm >> 31 & 1 == 1);
+            } else {
+                // All bits have been shifted out, including carry bit
+                cpsr.c.write(false);
+            }
+        }
+    }
+
+    return result;
+}
+
+pub fn asr(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
+    const amount = @truncate(u5, total_amount);
+    const bit_count: u8 = @typeInfo(u32).Int.bits;
+
+    var result: u32 = 0x0000_0000;
+    if (total_amount < bit_count) {
+        result = @bitCast(u32, @bitCast(i32, rm) >> amount);
+        if (S and total_amount != 0) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
+    } else {
+        // ASR #32 and ASR #>32 have the same result
+        result = @bitCast(u32, @bitCast(i32, rm) >> 31);
+        if (S) cpsr.c.write(result >> 31 & 1 == 1);
+    }
+
+    return result;
+}
+
+pub fn ror(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
+    const result = rotr(u32, rm, total_amount);
+
+    if (S and total_amount != 0) {
+        cpsr.c.write(result >> 31 & 1 == 1);
+    }
+
+    return result;
+}

src/core/cpu/thumb/alu.zig

@@ -0,0 +1,108 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
+
+const adc = @import("../arm/data_processing.zig").adc;
+const sbc = @import("../arm/data_processing.zig").sbc;
+
+const lsl = @import("../barrel_shifter.zig").lsl;
+const lsr = @import("../barrel_shifter.zig").lsr;
+const asr = @import("../barrel_shifter.zig").asr;
+const ror = @import("../barrel_shifter.zig").ror;
+
+pub fn fmt4(comptime op: u4) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            const rs = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+            const carry = @boolToInt(cpu.cpsr.c.read());
+
+            const op1 = cpu.r[rd];
+            const op2 = cpu.r[rs];
+
+            var result: u32 = undefined;
+            var overflow: u1 = undefined;
+
+            switch (op) {
+                0x0 => result = op1 & op2, // AND
+                0x1 => result = op1 ^ op2, // EOR
+                0x2 => result = lsl(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSL
+                0x3 => result = lsr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // LSR
+                0x4 => result = asr(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ASR
+                0x5 => result = adc(&overflow, op1, op2, carry), // ADC
+                0x6 => result = sbc(op1, op2, carry), // SBC
+                0x7 => result = ror(true, &cpu.cpsr, op1, @truncate(u8, op2)), // ROR
+                0x8 => result = op1 & op2, // TST
+                0x9 => result = 0 -% op2, // NEG
+                0xA => result = op1 -% op2, // CMP
+                0xB => {
+                    // CMN
+                    const tmp = @addWithOverflow(op1, op2);
+                    result = tmp[0];
+                    overflow = tmp[1];
+                },
+                0xC => result = op1 | op2, // ORR
+                0xD => result = @truncate(u32, @as(u64, op2) * @as(u64, op1)),
+                0xE => result = op1 & ~op2,
+                0xF => result = ~op2,
+            }
+
+            // Write to Destination Register
+            switch (op) {
+                0x8, 0xA, 0xB => {},
+                else => cpu.r[rd] = result,
+            }
+
+            // Write Flags
+            switch (op) {
+                0x0, 0x1, 0x2, 0x3, 0x4, 0x7, 0xC, 0xE, 0xF => {
+                    // Logic Operations
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // C set by Barrel Shifter, V is unaffected
+                },
+                0x8, 0xA => {
+                    // Test Flags
+                    // CMN (0xB) is handled with ADC
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (op == 0xA) {
+                        // CMP specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
+                0x5, 0xB => {
+                    // ADC, CMN
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(overflow == 0b1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0x6 => {
+                    // SBC
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    const subtrahend = @as(u64, op2) -% carry +% 1;
+                    cpu.cpsr.c.write(subtrahend <= op1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0x9 => {
+                    // NEG
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(op2 <= 0);
+                    cpu.cpsr.v.write(((0 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0xD => {
+                    // Multiplication
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // V is unaffected, assuming similar behaviour to ARMv4 MUL C is undefined
+                },
+            }
+        }
+    }.inner;
+}

src/core/cpu/thumb/block_data_transfer.zig

@@ -0,0 +1,100 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
+
+pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            const count = @boolToInt(R) + countRlist(opcode);
+            const start = cpu.r[13] - if (!L) count * 4 else 0;
+
+            var end = cpu.r[13];
+            if (L) {
+                end += count * 4;
+            } else {
+                end -= 4;
+            }
+
+            var address = start;
+
+            var i: u4 = 0;
+            while (i < 8) : (i += 1) {
+                if (opcode >> i & 1 == 1) {
+                    if (L) {
+                        cpu.r[i] = bus.read(u32, address);
+                    } else {
+                        bus.write(u32, address, cpu.r[i]);
+                    }
+
+                    address += 4;
+                }
+            }
+
+            if (R) {
+                if (L) {
+                    const value = bus.read(u32, address);
+                    cpu.r[15] = value & ~@as(u32, 1);
+                    cpu.pipe.reload(cpu);
+                } else {
+                    bus.write(u32, address, cpu.r[14]);
+                }
+                address += 4;
+            }
+
+            cpu.r[13] = if (L) end else start;
+        }
+    }.inner;
+}
+
+pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            var address = cpu.r[rb];
+            const end_address = cpu.r[rb] + 4 * countRlist(opcode);
+
+            if (opcode & 0xFF == 0) {
+                if (L) {
+                    cpu.r[15] = bus.read(u32, address);
+                    cpu.pipe.reload(cpu);
+                } else {
+                    bus.write(u32, address, cpu.r[15] + 2);
+                }
+
+                cpu.r[rb] += 0x40;
+                return;
+            }
+
+            var i: u4 = 0;
+            var first_write = true;
+
+            while (i < 8) : (i += 1) {
+                if (opcode >> i & 1 == 1) {
+                    if (L) {
+                        cpu.r[i] = bus.read(u32, address);
+                    } else {
+                        bus.write(u32, address, cpu.r[i]);
+                    }
+
+                    if (!L and first_write) {
+                        cpu.r[rb] = end_address;
+                        first_write = false;
+                    }
+
+                    address += 4;
+                }
+            }
+
+            if (L and opcode >> rb & 1 != 1) cpu.r[rb] = address;
+        }
+    }.inner;
+}
+
+inline fn countRlist(opcode: u16) u32 {
+    var count: u32 = 0;
+
+    inline for (0..8) |i| {
+        if (opcode >> (7 - i) & 1 == 1) count += 1;
+    }
+
+    return count;
+}

src/core/cpu/thumb/branch.zig

@@ -0,0 +1,54 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
+
+const checkCond = @import("../../cpu.zig").checkCond;
+const sext = @import("zba-util").sext;
+
+pub fn fmt16(comptime cond: u4) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            // B
+            if (cond == 0xE or cond == 0xF)
+                cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
+
+            if (!checkCond(cpu.cpsr, cond)) return;
+
+            cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}
+
+pub fn fmt18() InstrFn {
+    return struct {
+        // B but conditional
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}
+
+pub fn fmt19(comptime is_low: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            // BL
+            const offset = opcode & 0x7FF;
+
+            if (is_low) {
+                // Instruction 2
+                const next_opcode = cpu.r[15] - 2;
+
+                cpu.r[15] = cpu.r[14] +% (offset << 1);
+                cpu.r[14] = next_opcode | 1;
+
+                cpu.pipe.reload(cpu);
+            } else {
+                // Instruction 1
+                const lr_offset = sext(u32, u11, offset) << 12;
+                cpu.r[14] = (cpu.r[15] +% lr_offset) & ~@as(u32, 1);
+            }
+        }
+    }.inner;
+}

src/core/cpu/thumb/data_processing.zig

@@ -0,0 +1,199 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
+
+const add = @import("../arm/data_processing.zig").add;
+
+const lsl = @import("../barrel_shifter.zig").lsl;
+const lsr = @import("../barrel_shifter.zig").lsr;
+const asr = @import("../barrel_shifter.zig").asr;
+
+pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            const rs = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            const result = switch (op) {
+                0b00 => blk: {
+                    // LSL
+                    if (offset == 0) {
+                        break :blk cpu.r[rs];
+                    } else {
+                        break :blk lsl(true, &cpu.cpsr, cpu.r[rs], offset);
+                    }
+                },
+                0b01 => blk: {
+                    // LSR
+                    if (offset == 0) {
+                        cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
+                        break :blk @as(u32, 0);
+                    } else {
+                        break :blk lsr(true, &cpu.cpsr, cpu.r[rs], offset);
+                    }
+                },
+                0b10 => blk: {
+                    // ASR
+                    if (offset == 0) {
+                        cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
+                        break :blk @bitCast(u32, @bitCast(i32, cpu.r[rs]) >> 31);
+                    } else {
+                        break :blk asr(true, &cpu.cpsr, cpu.r[rs], offset);
+                    }
+                },
+                else => cpu.panic("[CPU/THUMB.1] 0b{b:0>2} is not a valid op", .{op}),
+            };
+
+            // Equivalent to an ARM MOVS
+            cpu.r[rd] = result;
+
+            // Write Flags
+            cpu.cpsr.n.write(result >> 31 & 1 == 1);
+            cpu.cpsr.z.write(result == 0);
+        }
+    }.inner;
+}
+
+pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
+            const rd = @as(u4, h1) << 3 | (opcode & 0x7);
+
+            const op1 = cpu.r[rd];
+            const op2 = cpu.r[rs];
+
+            var result: u32 = undefined;
+            var overflow: u1 = undefined;
+            switch (op) {
+                0b00 => result = add(&overflow, op1, op2), // ADD
+                0b01 => result = op1 -% op2, // CMP
+                0b10 => result = op2, // MOV
+                0b11 => {},
+            }
+
+            // Write to Destination Register
+            switch (op) {
+                0b01 => {}, // Test Instruction
+                0b11 => {
+                    // BX
+                    const is_thumb = op2 & 1 == 1;
+                    cpu.r[15] = op2 & ~@as(u32, 1);
+
+                    cpu.cpsr.t.write(is_thumb);
+                    cpu.pipe.reload(cpu);
+                },
+                else => {
+                    cpu.r[rd] = result;
+                    if (rd == 0xF) {
+                        cpu.r[15] &= ~@as(u32, 1);
+                        cpu.pipe.reload(cpu);
+                    }
+                },
+            }
+
+            // Write Flags
+            switch (op) {
+                0b01 => {
+                    // CMP
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(op2 <= op1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0b00, 0b10, 0b11 => {}, // MOV and Branch Instruction
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            const rs = opcode >> 3 & 0x7;
+            const rd = @truncate(u3, opcode);
+            const op1 = cpu.r[rs];
+            const op2: u32 = if (I) rn else cpu.r[rn];
+
+            if (is_sub) {
+                // SUB
+                const result = op1 -% op2;
+                cpu.r[rd] = result;
+
+                cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                cpu.cpsr.z.write(result == 0);
+                cpu.cpsr.c.write(op2 <= op1);
+                cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+            } else {
+                // ADD
+                var overflow: u1 = undefined;
+                const result = add(&overflow, op1, op2);
+                cpu.r[rd] = result;
+
+                cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                cpu.cpsr.z.write(result == 0);
+                cpu.cpsr.c.write(overflow == 0b1);
+                cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt3(comptime op: u2, comptime rd: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            const op1 = cpu.r[rd];
+            const op2: u32 = opcode & 0xFF; // Offset
+
+            var overflow: u1 = undefined;
+            const result: u32 = switch (op) {
+                0b00 => op2, // MOV
+                0b01 => op1 -% op2, // CMP
+                0b10 => add(&overflow, op1, op2), // ADD
+                0b11 => op1 -% op2, // SUB
+            };
+
+            // Write to Register
+            if (op != 0b01) cpu.r[rd] = result;
+
+            // Write Flags
+            cpu.cpsr.n.write(result >> 31 & 1 == 1);
+            cpu.cpsr.z.write(result == 0);
+
+            switch (op) {
+                0b00 => {}, // MOV | C set by Barrel Shifter, V is unaffected
+                0b01, 0b11 => {
+                    // SUB, CMP
+                    cpu.cpsr.c.write(op2 <= op1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0b10 => {
+                    // ADD
+                    cpu.cpsr.c.write(overflow == 0b1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                },
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt12(comptime isSP: bool, comptime rd: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            // ADD
+            const left = if (isSP) cpu.r[13] else cpu.r[15] & ~@as(u32, 2);
+            const right = (opcode & 0xFF) << 2;
+            cpu.r[rd] = left + right;
+        }
+    }.inner;
+}
+
+pub fn fmt13(comptime S: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            // ADD
+            const offset = (opcode & 0x7F) << 2;
+            cpu.r[13] = if (S) cpu.r[13] - offset else cpu.r[13] + offset;
+        }
+    }.inner;
+}

src/core/cpu/thumb/data_transfer.zig

@@ -0,0 +1,145 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
+
+const rotr = @import("zba-util").rotr;
+const sext = @import("zba-util").sext;
+
+pub fn fmt6(comptime rd: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            // LDR
+            const offset = (opcode & 0xFF) << 2;
+
+            // Bit 1 of the PC intentionally ignored
+            cpu.r[rd] = bus.read(u32, (cpu.r[15] & ~@as(u32, 2)) + offset);
+        }
+    }.inner;
+}
+
+pub fn fmt78(comptime op: u2, comptime T: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            const ro = opcode >> 6 & 0x7;
+            const rb = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            const address = cpu.r[rb] +% cpu.r[ro];
+
+            if (T) {
+                // Format 8
+                switch (op) {
+                    0b00 => {
+                        // STRH
+                        bus.write(u16, address, @truncate(u16, cpu.r[rd]));
+                    },
+                    0b01 => {
+                        // LDSB
+                        cpu.r[rd] = sext(u32, u8, bus.read(u8, address));
+                    },
+                    0b10 => {
+                        // LDRH
+                        const value = bus.read(u16, address);
+                        cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
+                    },
+                    0b11 => {
+                        // LDRSH
+                        const value = bus.read(u16, address);
+                        cpu.r[rd] = if (address & 1 == 1) sext(u32, u8, @truncate(u8, value >> 8)) else sext(u32, u16, value);
+                    },
+                }
+            } else {
+                // Format 7
+                switch (op) {
+                    0b00 => {
+                        // STR
+                        bus.write(u32, address, cpu.r[rd]);
+                    },
+                    0b01 => {
+                        // STRB
+                        bus.write(u8, address, @truncate(u8, cpu.r[rd]));
+                    },
+                    0b10 => {
+                        // LDR
+                        const value = bus.read(u32, address);
+                        cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
+                    },
+                    0b11 => {
+                        // LDRB
+                        cpu.r[rd] = bus.read(u8, address);
+                    },
+                }
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            const rb = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            if (L) {
+                if (B) {
+                    // LDRB
+                    const address = cpu.r[rb] + offset;
+                    cpu.r[rd] = bus.read(u8, address);
+                } else {
+                    // LDR
+                    const address = cpu.r[rb] + (@as(u32, offset) << 2);
+                    const value = bus.read(u32, address);
+                    cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
+                }
+            } else {
+                if (B) {
+                    // STRB
+                    const address = cpu.r[rb] + offset;
+                    bus.write(u8, address, @truncate(u8, cpu.r[rd]));
+                } else {
+                    // STR
+                    const address = cpu.r[rb] + (@as(u32, offset) << 2);
+                    bus.write(u32, address, cpu.r[rd]);
+                }
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt10(comptime L: bool, comptime offset: u5) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            const rb = opcode >> 3 & 0x7;
+            const rd = opcode & 0x7;
+
+            const address = cpu.r[rb] + (@as(u6, offset) << 1);
+
+            if (L) {
+                // LDRH
+                const value = bus.read(u16, address);
+                cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
+            } else {
+                // STRH
+                bus.write(u16, address, @truncate(u16, cpu.r[rd]));
+            }
+        }
+    }.inner;
+}
+
+pub fn fmt11(comptime L: bool, comptime rd: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            const offset = (opcode & 0xFF) << 2;
+            const address = cpu.r[13] + offset;
+
+            if (L) {
+                // LDR
+                const value = bus.read(u32, address);
+                cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
+            } else {
+                // STR
+                bus.write(u32, address, cpu.r[rd]);
+            }
+        }
+    }.inner;
+}

src/core/cpu/thumb/software_interrupt.zig

@@ -0,0 +1,23 @@
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").thumb.InstrFn;
+
+pub fn fmt17() InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
+            // Copy Values from Current Mode
+            const ret_addr = cpu.r[15] - 2;
+            const cpsr = cpu.cpsr.raw;
+
+            // Switch Mode
+            cpu.changeMode(.Supervisor);
+            cpu.cpsr.t.write(false); // Force ARM Mode
+            cpu.cpsr.i.write(true); // Disable normal interrupts
+
+            cpu.r[14] = ret_addr; // Resume Execution
+            cpu.spsr.raw = cpsr; // Previous mode CPSR
+            cpu.r[15] = 0x0000_0008;
+            cpu.pipe.reload(cpu);
+        }
+    }.inner;
+}

src/core/cpu_util.zig

@@ -1,75 +0,0 @@
-const std = @import("std");
-
-const Arm7tdmi = @import("arm32").Arm7tdmi;
-const Bank = @import("arm32").Arm7tdmi.Bank;
-const Bus = @import("Bus.zig");
-
-pub inline fn isHalted(cpu: *const Arm7tdmi) bool {
-    const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
-    return bus_ptr.io.haltcnt == .Halt;
-}
-
-pub fn stepDmaTransfer(cpu: *Arm7tdmi) bool {
-    const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
-    inline for (0..4) |i| {
-        if (bus_ptr.dma[i].in_progress) {
-            bus_ptr.dma[i].step(cpu);
-            return true;
-        }
-    }
-
-    return false;
-}
-
-pub fn handleInterrupt(cpu: *Arm7tdmi) void {
-    const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-    const should_handle = bus_ptr.io.ie.raw & bus_ptr.io.irq.raw;
-
-    // Return if IME is disabled, CPSR I is set or there is nothing to handle
-    if (!bus_ptr.io.ime or cpu.cpsr.i.read() or should_handle == 0) return;
-
-    // If Pipeline isn't full, we have a bug
-    std.debug.assert(cpu.pipe.isFull());
-
-    // log.debug("Handling Interrupt!", .{});
-    bus_ptr.io.haltcnt = .Execute;
-
-    // FIXME: This seems weird, but retAddr.gba suggests I need to make these changes
-    const ret_addr = cpu.r[15] - if (cpu.cpsr.t.read()) 0 else @as(u32, 4);
-    const new_spsr = cpu.cpsr.raw;
-
-    cpu.changeMode(.Irq);
-    cpu.cpsr.t.write(false);
-    cpu.cpsr.i.write(true);
-
-    cpu.r[14] = ret_addr;
-    cpu.spsr.raw = new_spsr;
-    cpu.r[15] = 0x0000_0018;
-    cpu.pipe.reload(cpu);
-}
-
-/// Advances state so that the BIOS is skipped
-///
-/// Note: This accesses the CPU's bus ptr so it only may be called
-/// once the Bus has been properly initialized
-///
-/// TODO: Make above notice impossible to do in code
-pub fn fastBoot(cpu: *Arm7tdmi) void {
-    const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-    cpu.r = std.mem.zeroes([16]u32);
-
-    // cpu.r[0] = 0x08000000;
-    // cpu.r[1] = 0x000000EA;
-    cpu.r[13] = 0x0300_7F00;
-    cpu.r[15] = 0x0800_0000;
-
-    cpu.bank.r[Bank.regIdx(.Irq, .R13)] = 0x0300_7FA0;
-    cpu.bank.r[Bank.regIdx(.Supervisor, .R13)] = 0x0300_7FE0;
-
-    // cpu.cpsr.raw = 0x6000001F;
-    cpu.cpsr.raw = 0x0000_001F;
-
-    bus_ptr.bios.addr_latch = 0x0000_00DC + 8;
-}

src/core/emu.zig

@@ -3,15 +3,9 @@ const SDL = @import("sdl2");
 const config = @import("../config.zig");
 
 const Scheduler = @import("scheduler.zig").Scheduler;
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
-const Bus = @import("Bus.zig");
 const Tracker = @import("../util.zig").FpsTracker;
-const Channel = @import("zba-util").Channel(Message, 0x100);
+const TwoWayChannel = @import("zba-util").TwoWayChannel;
-
-pub const Message = enum { Pause, Resume, Quit };
-
-const stepDmaTransfer = @import("cpu_util.zig").stepDmaTransfer;
-const isHalted = @import("cpu_util.zig").isHalted;
 
 const Timer = std.time.Timer;
 
@@ -41,25 +35,23 @@ const RunKind = enum {
     LimitedFPS,
 };
 
-pub fn run(cpu: *Arm7tdmi, scheduler: *Scheduler, tracker: *Tracker, rx: Channel.Receiver) void {
+pub fn run(cpu: *Arm7tdmi, scheduler: *Scheduler, tracker: *Tracker, channel: *TwoWayChannel) void {
     const audio_sync = config.config().guest.audio_sync and !config.config().host.mute;
     if (audio_sync) log.info("Audio sync enabled", .{});
 
     if (config.config().guest.video_sync) {
-        inner(.LimitedFPS, audio_sync, cpu, scheduler, tracker, rx);
+        inner(.LimitedFPS, audio_sync, cpu, scheduler, tracker, channel);
     } else {
-        inner(.UnlimitedFPS, audio_sync, cpu, scheduler, tracker, rx);
+        inner(.UnlimitedFPS, audio_sync, cpu, scheduler, tracker, channel);
     }
 }
 
-fn inner(comptime kind: RunKind, audio_sync: bool, cpu: *Arm7tdmi, scheduler: *Scheduler, tracker: ?*Tracker, rx: Channel.Receiver) void {
+fn inner(comptime kind: RunKind, audio_sync: bool, cpu: *Arm7tdmi, scheduler: *Scheduler, tracker: ?*Tracker, channel: *TwoWayChannel) void {
     if (kind == .UnlimitedFPS or kind == .LimitedFPS) {
         std.debug.assert(tracker != null);
         log.info("FPS tracking enabled", .{});
     }
 
-    const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
     var paused: bool = false;
 
     switch (kind) {
@@ -67,15 +59,19 @@ fn inner(comptime kind: RunKind, audio_sync: bool, cpu: *Arm7tdmi, scheduler: *S
             log.info("Emulation w/out video sync", .{});
 
             while (true) {
-                if (rx.recv()) |m| switch (m) {
+                if (channel.emu.pop()) |e| switch (e) {
                     .Quit => break,
-                    .Resume, .Pause => paused = m == .Pause,
+                    .Resume => paused = false,
+                    .Pause => {
+                        paused = true;
+                        channel.gui.push(.Paused);
+                    },
                 };
 
                 if (paused) continue;
 
                 runFrame(scheduler, cpu);
-                audioSync(audio_sync, bus_ptr.apu.stream, &bus_ptr.apu.is_buffer_full);
+                audioSync(audio_sync, cpu.bus.apu.stream, &cpu.bus.apu.is_buffer_full);
 
                 if (kind == .UnlimitedFPS) tracker.?.tick();
             }
@@ -86,9 +82,13 @@ fn inner(comptime kind: RunKind, audio_sync: bool, cpu: *Arm7tdmi, scheduler: *S
             var wake_time: u64 = frame_period;
 
             while (true) {
-                if (rx.recv()) |m| switch (m) {
+                if (channel.emu.pop()) |e| switch (e) {
                     .Quit => break,
-                    .Resume, .Pause => paused = m == .Pause,
+                    .Resume => paused = false,
+                    .Pause => {
+                        paused = true;
+                        channel.gui.push(.Paused);
+                    },
                 };
 
                 if (paused) continue;
@@ -101,7 +101,7 @@ fn inner(comptime kind: RunKind, audio_sync: bool, cpu: *Arm7tdmi, scheduler: *S
                 // the amount of time needed for audio to catch up rather than
                 // our expected wake-up time
 
-                audioSync(audio_sync, bus_ptr.apu.stream, &bus_ptr.apu.is_buffer_full);
+                audioSync(audio_sync, cpu.bus.apu.stream, &cpu.bus.apu.is_buffer_full);
                 if (!audio_sync) spinLoop(&timer, wake_time);
                 wake_time = new_wake_time;
 
@@ -115,8 +115,8 @@ pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi) void {
     const frame_end = sched.tick + cycles_per_frame;
 
     while (sched.tick < frame_end) {
-        if (!stepDmaTransfer(cpu)) {
+        if (!cpu.stepDmaTransfer()) {
-            if (isHalted(cpu)) {
+            if (cpu.isHalted()) {
                 // Fast-forward to next Event
                 sched.tick = sched.nextTimestamp();
             } else {
@@ -140,10 +140,6 @@ fn audioSync(audio_sync: bool, stream: *SDL.SDL_AudioStream, is_buffer_full: *bo
     // If Busy is false, there's no need to sync here
     if (!still_full) return;
 
-    // TODO: Refactor!!!!
-    // while (SDL.SDL_AudioStreamAvailable(stream) > sample_size * max_buf_size >> 1)
-    //     std.atomic.spinLoopHint();
-
     while (true) {
         still_full = SDL.SDL_AudioStreamAvailable(stream) > sample_size * max_buf_size >> 1;
         if (!audio_sync or !still_full) break;
@@ -188,8 +184,7 @@ fn sleep(timer: *Timer, wake_time: u64) ?u64 {
 }
 
 fn spinLoop(timer: *Timer, wake_time: u64) void {
-    while (timer.read() < wake_time)
+    while (true) if (timer.read() > wake_time) break;
-        std.atomic.spinLoopHint();
 }
 
 pub const EmuThing = struct {
@@ -233,8 +228,8 @@ pub const EmuThing = struct {
 
         // TODO: How can I make it easier to keep this in lock-step with runFrame?
         while (!did_step) {
-            if (!stepDmaTransfer(cpu)) {
+            if (!cpu.stepDmaTransfer()) {
-                if (isHalted(cpu)) {
+                if (cpu.isHalted()) {
                     // Fast-forward to next Event
                     sched.tick = sched.queue.peek().?.tick;
                 } else {
@@ -256,18 +251,6 @@ pub fn reset(cpu: *Arm7tdmi) void {
 }
 
 pub fn replaceGamepak(cpu: *Arm7tdmi, file_path: []const u8) !void {
-    const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
+    try cpu.bus.replaceGamepak(file_path);
-
-    try bus_ptr.replaceGamepak(file_path);
     reset(cpu);
 }
-
-pub fn replaceBios(cpu: *Arm7tdmi, file_path: []const u8) !void {
-    const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
-    const allocator = bus_ptr.bios.allocator;
-    const bios_len = 0x4000;
-
-    bus_ptr.bios.buf = try allocator.alloc(u8, bios_len);
-    try bus_ptr.bios.load(file_path);
-}

src/core/ppu.zig

@@ -10,8 +10,7 @@ const Oam = @import("ppu/Oam.zig");
 const Palette = @import("ppu/Palette.zig");
 const Vram = @import("ppu/Vram.zig");
 const Scheduler = @import("scheduler.zig").Scheduler;
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
-const Bus = @import("Bus.zig");
 const FrameBuffer = @import("../util.zig").FrameBuffer;
 
 const Allocator = std.mem.Allocator;
@@ -21,8 +20,6 @@ const getHalf = util.getHalf;
 const setHalf = util.setHalf;
 const setQuart = util.setQuart;
 
-const handleInterrupt = @import("cpu_util.zig").handleInterrupt;
-
 pub const width = 240;
 pub const height = 160;
 pub const framebuf_pitch = width * @sizeOf(u32);
@@ -269,7 +266,7 @@ pub const Ppu = struct {
         sched.push(.Draw, 240 * 4); // Add first PPU Event to Scheduler
 
         const sprites = try allocator.create([128]?Sprite);
-        @memset(sprites, null);
+        std.mem.set(?Sprite, sprites, null);
 
         return Self{
             .vram = try Vram.init(allocator),
@@ -310,7 +307,7 @@ pub const Ppu = struct {
         self.vcount = .{ .raw = 0x0000 };
 
         self.scanline.reset();
-        @memset(self.scanline_sprites, null);
+        std.mem.set(?Sprite, self.scanline_sprites, null);
     }
 
     pub fn deinit(self: *Self) void {
@@ -747,7 +744,7 @@ pub const Ppu = struct {
         // Reset Current Scanline Pixel Buffer and list of fetched sprites
         // in prep for next scanline
         self.scanline.reset();
-        @memset(self.scanline_sprites, null);
+        std.mem.set(?Sprite, self.scanline_sprites, null);
     }
 
     fn getBgr555(self: *Self, maybe_top: Scanline.Pixel, maybe_btm: Scanline.Pixel) u16 {
@@ -1003,25 +1000,21 @@ pub const Ppu = struct {
     }
 
     pub fn onHdrawEnd(self: *Self, cpu: *Arm7tdmi, late: u64) void {
-        const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
         // Transitioning to a Hblank
         if (self.dispstat.hblank_irq.read()) {
-            bus_ptr.io.irq.hblank.set();
+            cpu.bus.io.irq.hblank.set();
-            handleInterrupt(cpu);
+            cpu.handleInterrupt();
         }
 
         // If we're not also in VBlank, attempt to run any pending DMA Reqs
         if (!self.dispstat.vblank.read())
-            dma.onBlanking(bus_ptr, .HBlank);
+            dma.onBlanking(cpu.bus, .HBlank);
 
         self.dispstat.hblank.set();
         self.sched.push(.HBlank, 68 * 4 -| late);
     }
 
     pub fn onHblankEnd(self: *Self, cpu: *Arm7tdmi, late: u64) void {
-        const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
         // The End of a Hblank (During Draw or Vblank)
         const old_scanline = self.vcount.scanline.read();
         const scanline = (old_scanline + 1) % 228;
@@ -1034,8 +1027,8 @@ pub const Ppu = struct {
         self.dispstat.coincidence.write(coincidence);
 
         if (coincidence and self.dispstat.vcount_irq.read()) {
-            bus_ptr.io.irq.coincidence.set();
+            cpu.bus.io.irq.coincidence.set();
-            handleInterrupt(cpu);
+            cpu.handleInterrupt();
         }
 
         if (scanline < 160) {
@@ -1049,15 +1042,15 @@ pub const Ppu = struct {
                 self.dispstat.vblank.set();
 
                 if (self.dispstat.vblank_irq.read()) {
-                    bus_ptr.io.irq.vblank.set();
+                    cpu.bus.io.irq.vblank.set();
-                    handleInterrupt(cpu);
+                    cpu.handleInterrupt();
                 }
 
                 self.aff_bg[0].latchRefPoints();
                 self.aff_bg[1].latchRefPoints();
 
                 // See if Vblank DMA is present and not enabled
-                dma.onBlanking(bus_ptr, .VBlank);
+                dma.onBlanking(cpu.bus, .VBlank);
             }
 
             if (scanline == 227) self.dispstat.vblank.unset();
@@ -1561,7 +1554,7 @@ const Scanline = struct {
 
     fn init(allocator: Allocator) !Self {
         const buf = try allocator.alloc(Pixel, width * 2); // Top & Bottom Scanline
-        @memset(buf, .unset);
+        std.mem.set(Pixel, buf, .unset);
 
         return .{
             // Top & Bototm Layers
@@ -1572,7 +1565,7 @@ const Scanline = struct {
     }
 
     fn reset(self: *Self) void {
-        @memset(self.buf, .unset);
+        std.mem.set(Pixel, self.buf, .unset);
     }
 
     fn deinit(self: *Self) void {

src/core/ppu/Oam.zig

@@ -29,13 +29,13 @@ pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
 
 pub fn init(allocator: Allocator) !Self {
     const buf = try allocator.alloc(u8, buf_len);
-    @memset(buf, 0);
+    std.mem.set(u8, buf, 0);
 
     return Self{ .buf = buf, .allocator = allocator };
 }
 
 pub fn reset(self: *Self) void {
-    @memset(self.buf, 0);
+    std.mem.set(u8, self.buf, 0);
 }
 
 pub fn deinit(self: *Self) void {

src/core/ppu/Palette.zig

@@ -32,13 +32,13 @@ pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
 
 pub fn init(allocator: Allocator) !Self {
     const buf = try allocator.alloc(u8, buf_len);
-    @memset(buf, 0);
+    std.mem.set(u8, buf, 0);
 
     return Self{ .buf = buf, .allocator = allocator };
 }
 
 pub fn reset(self: *Self) void {
-    @memset(self.buf, 0);
+    std.mem.set(u8, self.buf, 0);
 }
 
 pub fn deinit(self: *Self) void {

src/core/ppu/Vram.zig

@@ -40,13 +40,13 @@ pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address:
 
 pub fn init(allocator: Allocator) !Self {
     const buf = try allocator.alloc(u8, buf_len);
-    @memset(buf, 0);
+    std.mem.set(u8, buf, 0);
 
     return Self{ .buf = buf, .allocator = allocator };
 }
 
 pub fn reset(self: *Self) void {
-    @memset(self.buf, 0);
+    std.mem.set(u8, self.buf, 0);
 }
 
 pub fn deinit(self: *Self) void {

src/core/scheduler.zig

@@ -1,7 +1,6 @@
 const std = @import("std");
 
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
-const Bus = @import("Bus.zig");
 const Clock = @import("bus/gpio.zig").Clock;
 
 const Order = std.math.Order;
@@ -46,8 +45,6 @@ pub const Scheduler = struct {
         const event = self.queue.remove();
         const late = self.tick - event.tick;
 
-        const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
         switch (event.kind) {
             .HeatDeath => {
                 log.err("u64 overflow. This *actually* should never happen.", .{});
@@ -55,33 +52,33 @@ pub const Scheduler = struct {
             },
             .Draw => {
                 // The end of a VDraw
-                bus_ptr.ppu.drawScanline();
+                cpu.bus.ppu.drawScanline();
-                bus_ptr.ppu.onHdrawEnd(cpu, late);
+                cpu.bus.ppu.onHdrawEnd(cpu, late);
             },
             .TimerOverflow => |id| {
                 switch (id) {
-                    inline 0...3 => |idx| bus_ptr.tim[idx].onTimerExpire(cpu, late),
+                    inline 0...3 => |idx| cpu.bus.tim[idx].onTimerExpire(cpu, late),
                 }
             },
             .ApuChannel => |id| {
                 switch (id) {
-                    0 => bus_ptr.apu.ch1.onToneSweepEvent(late),
+                    0 => cpu.bus.apu.ch1.onToneSweepEvent(late),
-                    1 => bus_ptr.apu.ch2.onToneEvent(late),
+                    1 => cpu.bus.apu.ch2.onToneEvent(late),
-                    2 => bus_ptr.apu.ch3.onWaveEvent(late),
+                    2 => cpu.bus.apu.ch3.onWaveEvent(late),
-                    3 => bus_ptr.apu.ch4.onNoiseEvent(late),
+                    3 => cpu.bus.apu.ch4.onNoiseEvent(late),
                 }
             },
             .RealTimeClock => {
-                const device = &bus_ptr.pak.gpio.device;
+                const device = &cpu.bus.pak.gpio.device;
                 if (device.kind != .Rtc or device.ptr == null) return;
 
                 const clock = @ptrCast(*Clock, @alignCast(@alignOf(*Clock), device.ptr.?));
                 clock.onClockUpdate(late);
             },
-            .FrameSequencer => bus_ptr.apu.onSequencerTick(late),
+            .FrameSequencer => cpu.bus.apu.onSequencerTick(late),
-            .SampleAudio => bus_ptr.apu.sampleAudio(late),
+            .SampleAudio => cpu.bus.apu.sampleAudio(late),
-            .HBlank => bus_ptr.ppu.onHblankEnd(cpu, late), // The end of a HBlank
+            .HBlank => cpu.bus.ppu.onHblankEnd(cpu, late), // The end of a HBlank
-            .VBlank => bus_ptr.ppu.onHdrawEnd(cpu, late), // The end of a VBlank
+            .VBlank => cpu.bus.ppu.onHdrawEnd(cpu, late), // The end of a VBlank
         }
     }
 

src/imgui.zig

@@ -10,12 +10,8 @@ const config = @import("config.zig");
 const emu = @import("core/emu.zig");
 
 const Gui = @import("platform.zig").Gui;
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
-const Scheduler = @import("core/scheduler.zig").Scheduler;
-const Bus = @import("core/Bus.zig");
-
 const RingBuffer = @import("zba-util").RingBuffer;
-const Dimensions = @import("platform.zig").Dimensions;
 
 const Allocator = std.mem.Allocator;
 const GLuint = gl.GLuint;
@@ -34,34 +30,14 @@ pub const State = struct {
 
     fps_hist: RingBuffer(u32),
     should_quit: bool = false,
-    emulation: Emulation,
-
-    win_stat: WindowStatus = .{},
-
-    const WindowStatus = struct {
-        show_deps: bool = false,
-        show_regs: bool = false,
-        show_schedule: bool = false,
-        show_perf: bool = false,
-        show_palette: bool = false,
-    };
-
-    const Emulation = union(enum) {
-        Active,
-        Inactive,
-        Transition: enum { Active, Inactive },
-    };
 
     /// if zba is initialized with a ROM already provided, this initializer should be called
     /// with `title_opt` being non-null
     pub fn init(allocator: Allocator, title_opt: ?*const [12]u8) !@This() {
         const history = try allocator.alloc(u32, histogram_len);
 
-        return .{
+        const title: [12:0]u8 = if (title_opt) |t| t.* ++ [_:0]u8{} else "[No Title]\x00\x00".*;
-            .title = handleTitle(title_opt),
+        return .{ .title = title, .fps_hist = RingBuffer(u32).init(history) };
-            .emulation = if (title_opt == null) .Inactive else .{ .Transition = .Active },
-            .fps_hist = RingBuffer(u32).init(history),
-        };
     }
 
     pub fn deinit(self: *@This(), allocator: Allocator) void {
@@ -70,11 +46,8 @@ pub const State = struct {
     }
 };
 
-pub fn draw(state: *State, win_dim: Dimensions, tex_id: GLuint, cpu: *Arm7tdmi) bool {
+pub fn draw(state: *State, tex_id: GLuint, cpu: *Arm7tdmi) void {
-    const scn_scale = config.config().host.win_scale;
+    const win_scale = config.config().host.win_scale;
-    const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
-    zgui.backend.newFrame(@intToFloat(f32, win_dim.width), @intToFloat(f32, win_dim.height));
 
     {
         _ = zgui.beginMainMenuBar();
@@ -83,8 +56,7 @@ pub fn draw(state: *State, win_dim: Dimensions, tex_id: GLuint, cpu: *Arm7tdmi)
         if (zgui.beginMenu("File", true)) {
             defer zgui.endMenu();
 
-            if (zgui.menuItem("Quit", .{}))
+            if (zgui.menuItem("Quit", .{})) state.should_quit = true;
-                state.should_quit = true;
 
             if (zgui.menuItem("Insert ROM", .{})) blk: {
                 const maybe_path = nfd.openFileDialog("gba", null) catch |e| {
@@ -104,72 +76,22 @@ pub fn draw(state: *State, win_dim: Dimensions, tex_id: GLuint, cpu: *Arm7tdmi)
                     break :blk;
                 };
 
-                state.title = handleTitle(&bus_ptr.pak.title);
+                state.title = cpu.bus.pak.title ++ [_:0]u8{};
-                state.emulation = .{ .Transition = .Active };
-            }
-
-            if (zgui.menuItem("Load BIOS", .{})) blk: {
-                const maybe_path = nfd.openFileDialog("bin", null) catch |e| {
-                    log.err("failed to open file dialog: {}", .{e});
-                    break :blk;
-                };
-
-                const file_path = maybe_path orelse {
-                    log.warn("did not receive a file path", .{});
-                    break :blk;
-                };
-                defer nfd.freePath(file_path);
-
-                log.info("user chose: \"{s}\"", .{file_path});
-                emu.replaceBios(cpu, file_path) catch |e| {
-                    log.err("failed to replace BIOS: {}", .{e});
-                    break :blk;
-                };
             }
         }
 
         if (zgui.beginMenu("Emulation", true)) {
             defer zgui.endMenu();
 
-            if (zgui.menuItem("Registers", .{ .selected = state.win_stat.show_regs }))
+            if (zgui.menuItem("Restart", .{})) {
-                state.win_stat.show_regs = true;
-
-            if (zgui.menuItem("Palette", .{ .selected = state.win_stat.show_palette }))
-                state.win_stat.show_palette = true;
-
-            if (zgui.menuItem("Schedule", .{ .selected = state.win_stat.show_schedule }))
-                state.win_stat.show_schedule = true;
-
-            if (zgui.menuItem("Paused", .{ .selected = state.emulation == .Inactive })) {
-                state.emulation = switch (state.emulation) {
-                    .Active => .{ .Transition = .Inactive },
-                    .Inactive => .{ .Transition = .Active },
-                    else => state.emulation,
-                };
-            }
-
-            if (zgui.menuItem("Restart", .{}))
                 emu.reset(cpu);
-        }
+            }
-
-        if (zgui.beginMenu("Stats", true)) {
-            defer zgui.endMenu();
-
-            if (zgui.menuItem("Performance", .{ .selected = state.win_stat.show_perf }))
-                state.win_stat.show_perf = true;
-        }
-
-        if (zgui.beginMenu("Help", true)) {
-            defer zgui.endMenu();
-
-            if (zgui.menuItem("Dependencies", .{ .selected = state.win_stat.show_deps }))
-                state.win_stat.show_deps = true;
         }
     }
 
     {
-        const w = @intToFloat(f32, gba_width * scn_scale);
+        const w = @intToFloat(f32, gba_width * win_scale);
-        const h = @intToFloat(f32, gba_height * scn_scale);
+        const h = @intToFloat(f32, gba_height * win_scale);
 
         const window_title = std.mem.sliceTo(&state.title, 0);
         _ = zgui.begin(window_title, .{ .flags = .{ .no_resize = true, .always_auto_resize = true } });
@@ -178,54 +100,8 @@ pub fn draw(state: *State, win_dim: Dimensions, tex_id: GLuint, cpu: *Arm7tdmi)
         zgui.image(@intToPtr(*anyopaque, tex_id), .{ .w = w, .h = h, .uv0 = .{ 0, 1 }, .uv1 = .{ 1, 0 } });
     }
 
-    // TODO: Any other steps to respect the copyright of the libraries I use?
+    {
-    if (state.win_stat.show_deps) {
+        _ = zgui.begin("Information", .{});
-        _ = zgui.begin("Dependencies", .{ .popen = &state.win_stat.show_deps });
-        defer zgui.end();
-
-        zgui.bulletText("known-folders by ziglibs", .{});
-        zgui.bulletText("nfd-zig by Fabio Arnold", .{});
-        {
-            zgui.indent(.{});
-            defer zgui.unindent(.{});
-
-            zgui.bulletText("nativefiledialog by Michael Labbe", .{});
-        }
-
-        zgui.bulletText("SDL.zig by Felix Queißner", .{});
-        {
-            zgui.indent(.{});
-            defer zgui.unindent(.{});
-
-            zgui.bulletText("SDL by Sam Lantinga", .{});
-        }
-
-        zgui.bulletText("tomlz by Matthew Hall", .{});
-        zgui.bulletText("zba-gdbstub by Rekai Musuka", .{});
-        zgui.bulletText("zba-util by Rekai Musuka", .{});
-        zgui.bulletText("zgui by Michal Ziulek", .{});
-        {
-            zgui.indent(.{});
-            defer zgui.unindent(.{});
-
-            zgui.bulletText("DearImGui by Omar Cornut", .{});
-        }
-        zgui.bulletText("zig-clap by Jimmi Holst Christensen", .{});
-        zgui.bulletText("zig-datetime by Jairus Martin", .{});
-
-        zgui.newLine();
-        zgui.bulletText("bitfield.zig by Hannes Bredberg and FlorenceOS contributors", .{});
-        zgui.bulletText("zig-opengl by Felix Queißner", .{});
-        {
-            zgui.indent(.{});
-            defer zgui.unindent(.{});
-
-            zgui.bulletText("OpenGL-Registry by The Khronos Group", .{});
-        }
-    }
-
-    if (state.win_stat.show_regs) {
-        _ = zgui.begin("Guest Registers", .{ .popen = &state.win_stat.show_regs });
         defer zgui.end();
 
         for (0..8) |i| {
@@ -244,12 +120,12 @@ pub fn draw(state: *State, win_dim: Dimensions, tex_id: GLuint, cpu: *Arm7tdmi)
 
         zgui.separator();
 
-        widgets.interrupts(" IE", bus_ptr.io.ie);
+        widgets.interrupts(" IE", cpu.bus.io.ie);
-        widgets.interrupts("IRQ", bus_ptr.io.irq);
+        widgets.interrupts("IRQ", cpu.bus.io.irq);
     }
 
-    if (state.win_stat.show_perf) {
+    {
-        _ = zgui.begin("Performance", .{ .popen = &state.win_stat.show_perf });
+        _ = zgui.begin("Performance", .{});
         defer zgui.end();
 
         const tmp = blk: {
@@ -266,8 +142,8 @@ pub fn draw(state: *State, win_dim: Dimensions, tex_id: GLuint, cpu: *Arm7tdmi)
         const sorted = blk: {
             var buf: @TypeOf(values) = undefined;
 
-            @memcpy(buf[0..len], values[0..len]);
+            std.mem.copy(u32, buf[0..len], values[0..len]);
-            std.mem.sort(u32, buf[0..len], {}, std.sort.asc(u32));
+            std.sort.sort(u32, buf[0..len], {}, std.sort.asc(u32));
 
             break :blk buf;
         };
@@ -311,84 +187,34 @@ pub fn draw(state: *State, win_dim: Dimensions, tex_id: GLuint, cpu: *Arm7tdmi)
         zgui.text(" 1% Low: {:0>3} fps", .{stats[2]});
     }
 
-    if (state.win_stat.show_schedule) {
+    {
-        _ = zgui.begin("Schedule", .{ .popen = &state.win_stat.show_schedule });
+        _ = zgui.begin("Scheduler", .{});
         defer zgui.end();
 
         const scheduler = cpu.sched;
 
-        zgui.text("tick: {X:0>16}", .{scheduler.now()});
+        zgui.text("tick: {X:0>16}", .{scheduler.tick});
         zgui.separator();
 
-        const sched_ptr = @ptrCast(*Scheduler, @alignCast(@alignOf(Scheduler), cpu.sched.ptr));
+        const Event = std.meta.Child(@TypeOf(scheduler.queue.items));
-        const Event = std.meta.Child(@TypeOf(sched_ptr.queue.items));
 
         var items: [20]Event = undefined;
-        const len = sched_ptr.queue.len;
+        const len = scheduler.queue.len;
 
-        @memcpy(&items, sched_ptr.queue.items);
+        std.mem.copy(Event, &items, scheduler.queue.items);
-        std.mem.sort(Event, items[0..len], {}, widgets.eventDesc(Event));
+        std.sort.sort(Event, items[0..len], {}, widgets.eventDesc(Event));
 
         for (items[0..len]) |event| {
             zgui.text("{X:0>16} | {?}", .{ event.tick, event.kind });
         }
     }
 
-    if (state.win_stat.show_palette) {
+    // {
-        _ = zgui.begin("Palette", .{ .popen = &state.win_stat.show_palette });
+    //     zgui.showDemoWindow(null);
-        defer zgui.end();
+    // }
-
-        widgets.paletteGrid(.Background, cpu);
-
-        zgui.sameLine(.{ .spacing = 20.0 });
-
-        widgets.paletteGrid(.Object, cpu);
-    }
-
-    {
-        zgui.showDemoWindow(null);
-    }
-
-    return true; // request redraw
 }
 
 const widgets = struct {
-    const PaletteKind = enum { Background, Object };
-
-    fn paletteGrid(comptime kind: PaletteKind, cpu: *const Arm7tdmi) void {
-        _ = zgui.beginGroup();
-        defer zgui.endGroup();
-
-        const address: u32 = switch (kind) {
-            .Background => 0x0500_0000,
-            .Object => 0x0500_0200,
-        };
-
-        for (0..0x100) |i| {
-            const offset = @truncate(u32, i);
-            const bgr555 = cpu.bus.dbgRead(u16, address + offset * @sizeOf(u16));
-            widgets.colourSquare(bgr555);
-
-            if ((i + 1) % 0x10 != 0) zgui.sameLine(.{});
-        }
-        zgui.text(@tagName(kind), .{});
-    }
-
-    fn colourSquare(bgr555: u16) void {
-        // FIXME: working with the packed struct enum is currently broken :pensive:
-        const ImguiColorEditFlags_NoInputs: u32 = 1 << 5;
-        const ImguiColorEditFlags_NoPicker: u32 = 1 << 2;
-        const flags = @bitCast(zgui.ColorEditFlags, ImguiColorEditFlags_NoInputs | ImguiColorEditFlags_NoPicker);
-
-        const b = @intToFloat(f32, bgr555 >> 10 & 0x1f);
-        const g = @intToFloat(f32, bgr555 >> 5 & 0x1F);
-        const r = @intToFloat(f32, bgr555 & 0x1F);
-
-        var col = [_]f32{ r / 31.0, g / 31.0, b / 31.0 };
-
-        _ = zgui.colorEdit3("", .{ .col = &col, .flags = flags });
-    }
-
     fn interrupts(comptime label: []const u8, int: anytype) void {
         const h = 15.0;
         const w = 9.0 * 2 + 3.5;
@@ -446,7 +272,7 @@ const widgets = struct {
     }
 
     fn psr(comptime label: []const u8, register: anytype) void {
-        const Mode = @import("arm32").arm.Mode;
+        const Mode = @import("core/cpu.zig").Mode;
 
         const maybe_mode = std.meta.intToEnum(Mode, register.mode.read()) catch null;
         const mode = if (maybe_mode) |mode| mode.toString() else "???";
@@ -479,13 +305,3 @@ const widgets = struct {
         }.inner;
     }
 };
-
-fn handleTitle(title_opt: ?*const [12]u8) [12:0]u8 {
-    if (title_opt == null) return "[N/A Title]\x00".*; // No ROM present
-    const title = title_opt.?;
-
-    // ROM Title is an empty string (ImGui hates these)
-    if (title[0] == '\x00') return "[No Title]\x00\x00".*;
-
-    return title.* ++ [_:0]u8{};
-}

src/main.zig

@@ -6,18 +6,15 @@ const clap = @import("clap");
 const config = @import("config.zig");
 const emu = @import("core/emu.zig");
 
-const Channel = @import("zba-util").Channel(emu.Message, 0x100);
+const TwoWayChannel = @import("zba-util").TwoWayChannel;
 const Gui = @import("platform.zig").Gui;
 const Bus = @import("core/Bus.zig");
+const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
 const Scheduler = @import("core/scheduler.zig").Scheduler;
 const FilePaths = @import("util.zig").FilePaths;
 const FpsTracker = @import("util.zig").FpsTracker;
 const Allocator = std.mem.Allocator;
 
-const Arm7tdmi = @import("arm32").Arm7tdmi;
-const IBus = @import("arm32").Bus;
-const IScheduler = @import("arm32").Scheduler;
-
 const log = std.log.scoped(.Cli);
 pub const log_level = if (builtin.mode != .Debug) .info else std.log.default_level;
 
@@ -34,7 +31,7 @@ const params = clap.parseParamsComptime(
 pub fn main() void {
     // Main Allocator for ZBA
     var gpa = std.heap.GeneralPurposeAllocator(.{}){};
-    defer std.debug.assert(gpa.deinit() == .ok);
+    defer std.debug.assert(!gpa.deinit());
 
     const allocator = gpa.allocator();
 
@@ -84,17 +81,13 @@ pub fn main() void {
     defer scheduler.deinit();
 
     var bus: Bus = undefined;
-
+    var cpu = Arm7tdmi.init(&scheduler, &bus, log_file);
-    var ischeduler = IScheduler.init(&scheduler);
-    var ibus = IBus.init(&bus);
-
-    var cpu = Arm7tdmi.init(ischeduler, ibus);
 
     bus.init(allocator, &scheduler, &cpu, paths) catch |e| exitln("failed to init zba bus: {}", .{e});
     defer bus.deinit();
 
-    if (config.config().guest.skip_bios or result.args.skip != 0 or paths.bios == null) {
+    if (config.config().guest.skip_bios or result.args.skip or paths.bios == null) {
-        @import("core/cpu_util.zig").fastBoot(&cpu);
+        cpu.fastBoot();
     }
 
     const title_ptr = if (paths.rom != null) &bus.pak.title else null;
@@ -105,10 +98,10 @@ pub fn main() void {
 
     var quit = std.atomic.Atomic(bool).init(false);
 
-    var ch = Channel.init(allocator) catch |e| exitln("failed to initialize ui -> emu thread message channel: {}", .{e});
+    var items: [0x100]u8 = undefined;
-    defer ch.deinit(allocator);
+    var channel = TwoWayChannel.init(&items);
 
-    if (result.args.gdb != 0) {
+    if (result.args.gdb) {
         const Server = @import("gdbstub").Server;
         const EmuThing = @import("core/emu.zig").EmuThing;
 
@@ -126,25 +119,21 @@ pub fn main() void {
         const thread = std.Thread.spawn(.{}, Server.run, .{ &server, allocator, &quit }) catch |e| exitln("gdb server thread crashed: {}", .{e});
         defer thread.join();
 
-        gui.run(.Debug, .{
+        gui.run(.{
             .cpu = &cpu,
             .scheduler = &scheduler,
-            .ch = ch.tx,
+            .channel = &channel,
         }) catch |e| exitln("main thread panicked: {}", .{e});
     } else {
         var tracker = FpsTracker.init();
 
-        // emu should start paused if there's no ROM to run
+        const thread = std.Thread.spawn(.{}, emu.run, .{ &cpu, &scheduler, &tracker, &channel }) catch |e| exitln("emu thread panicked: {}", .{e});
-        if (paths.rom == null)
-            ch.tx.send(.Pause);
-
-        const thread = std.Thread.spawn(.{}, emu.run, .{ &cpu, &scheduler, &tracker, ch.rx }) catch |e| exitln("emu thread panicked: {}", .{e});
         defer thread.join();
 
-        gui.run(.Standard, .{
+        gui.run(.{
             .cpu = &cpu,
             .scheduler = &scheduler,
-            .ch = ch.tx,
+            .channel = &channel,
             .tracker = &tracker,
         }) catch |e| exitln("main thread panicked: {}", .{e});
     }

src/platform.zig

@@ -8,12 +8,10 @@ const config = @import("config.zig");
 const imgui = @import("imgui.zig");
 
 const Apu = @import("core/apu.zig").Apu;
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
-const Bus = @import("core/Bus.zig");
 const Scheduler = @import("core/scheduler.zig").Scheduler;
 const FpsTracker = @import("util.zig").FpsTracker;
-const Channel = @import("zba-util").Channel(emu.Message, 0x100);
+const TwoWayChannel = @import("zba-util").TwoWayChannel;
-const KeyInput = @import("core/bus/io.zig").KeyInput;
 
 const gba_width = @import("core/ppu.zig").width;
 const gba_height = @import("core/ppu.zig").height;
@@ -23,8 +21,8 @@ const GLsizei = gl.GLsizei;
 const SDL_GLContext = *anyopaque;
 const Allocator = std.mem.Allocator;
 
-pub const Dimensions = struct { width: u32, height: u32 };
+const width = 1280;
-const default_dim: Dimensions = .{ .width = 1280, .height = 720 };
+const height = 720;
 
 pub const sample_rate = 1 << 15;
 pub const sample_format = SDL.AUDIO_U16;
@@ -35,12 +33,29 @@ pub const Gui = struct {
     const Self = @This();
     const log = std.log.scoped(.Gui);
 
+    // zig fmt: off
+    const vertices: [32]f32 = [_]f32{
+        // Positions        // Colours      // Texture Coords
+         1.0, -1.0, 0.0,    1.0, 0.0, 0.0,  1.0, 1.0, // Top Right
+         1.0,  1.0, 0.0,    0.0, 1.0, 0.0,  1.0, 0.0, // Bottom Right
+        -1.0,  1.0, 0.0,    0.0, 0.0, 1.0,  0.0, 0.0, // Bottom Left
+        -1.0, -1.0, 0.0,    1.0, 1.0, 0.0,  0.0, 1.0, // Top Left
+    };
+
+    const indices: [6]u32 = [_]u32{
+        0, 1, 3, // First Triangle
+        1, 2, 3, // Second Triangle
+    };
+    // zig fmt: on
+
     window: *SDL.SDL_Window,
     ctx: SDL_GLContext,
     audio: Audio,
 
     state: imgui.State,
+
     allocator: Allocator,
+    program_id: gl.GLuint,
 
     pub fn init(allocator: Allocator, apu: *Apu, title_opt: ?*const [12]u8) !Self {
         if (SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO) < 0) panic();
@@ -52,9 +67,9 @@ pub const Gui = struct {
             window_title,
             SDL.SDL_WINDOWPOS_CENTERED,
             SDL.SDL_WINDOWPOS_CENTERED,
-            default_dim.width,
+            width,
-            default_dim.height,
+            height,
-            SDL.SDL_WINDOW_OPENGL | SDL.SDL_WINDOW_SHOWN | SDL.SDL_WINDOW_RESIZABLE,
+            SDL.SDL_WINDOW_OPENGL | SDL.SDL_WINDOW_SHOWN,
         ) orelse panic();
 
         const ctx = SDL.SDL_GL_CreateContext(window) orelse panic();
@@ -72,6 +87,7 @@ pub const Gui = struct {
         return Self{
             .window = window,
             .ctx = ctx,
+            .program_id = try compileShaders(),
             .audio = Audio.init(apu),
 
             .allocator = allocator,
@@ -87,6 +103,7 @@ pub const Gui = struct {
         zgui.plot.deinit();
         zgui.deinit();
 
+        gl.deleteProgram(self.program_id);
         SDL.SDL_GL_DeleteContext(self.ctx);
         SDL.SDL_DestroyWindow(self.window);
         SDL.SDL_Quit();
@@ -94,275 +111,21 @@ pub const Gui = struct {
         self.* = undefined;
     }
 
-    const RunOptions = struct {
+    fn drawGbaTexture(self: *const Self, obj_ids: struct { GLuint, GLuint, GLuint }, tex_id: GLuint, buf: []const u8) void {
-        ch: Channel.Sender,
-        tracker: ?*FpsTracker = null,
-        cpu: *Arm7tdmi,
-        scheduler: *Scheduler,
-    };
-
-    const RunMode = enum { Standard, Debug };
-
-    pub fn run(self: *Self, comptime mode: RunMode, opt: RunOptions) !void {
-        const cpu = opt.cpu;
-        const tracker = opt.tracker;
-        const ch = opt.ch;
-
-        const bus_ptr = @ptrCast(*Bus, @alignCast(@alignOf(Bus), cpu.bus.ptr));
-
-        const objects = opengl_impl.createObjects();
-        defer gl.deleteBuffers(3, @as(*const [3]GLuint, &.{ objects.vao, objects.vbo, objects.ebo }));
-
-        const emu_tex = opengl_impl.createScreenTexture(bus_ptr.ppu.framebuf.get(.Renderer));
-        const out_tex = opengl_impl.createOutputTexture();
-        defer gl.deleteTextures(2, &[_]GLuint{ emu_tex, out_tex });
-
-        const fbo_id = try opengl_impl.createFrameBuffer(out_tex);
-        defer gl.deleteFramebuffers(1, &fbo_id);
-
-        // TODO: Support dynamically switching shaders?
-        const prog_id = try opengl_impl.compileShaders();
-        defer gl.deleteProgram(prog_id);
-
-        var win_dim: Dimensions = default_dim;
-
-        emu_loop: while (true) {
-            // Outside of `SDL.SDL_QUIT` below, the DearImgui UI might signal that the program
-            // should exit, in which case we should also handle this
-            if (self.state.should_quit) break :emu_loop;
-
-            var event: SDL.SDL_Event = undefined;
-            while (SDL.SDL_PollEvent(&event) != 0) {
-                _ = zgui.backend.processEvent(&event);
-
-                switch (event.type) {
-                    SDL.SDL_QUIT => break :emu_loop,
-                    SDL.SDL_KEYDOWN => {
-                        // TODO: Make use of compare_and_xor?
-                        const key_code = event.key.keysym.sym;
-                        var keyinput: KeyInput = .{ .raw = 0x0000 };
-
-                        switch (key_code) {
-                            SDL.SDLK_UP => keyinput.up.set(),
-                            SDL.SDLK_DOWN => keyinput.down.set(),
-                            SDL.SDLK_LEFT => keyinput.left.set(),
-                            SDL.SDLK_RIGHT => keyinput.right.set(),
-                            SDL.SDLK_x => keyinput.a.set(),
-                            SDL.SDLK_z => keyinput.b.set(),
-                            SDL.SDLK_a => keyinput.shoulder_l.set(),
-                            SDL.SDLK_s => keyinput.shoulder_r.set(),
-                            SDL.SDLK_RETURN => keyinput.start.set(),
-                            SDL.SDLK_RSHIFT => keyinput.select.set(),
-                            else => {},
-                        }
-
-                        bus_ptr.io.keyinput.fetchAnd(~keyinput.raw, .Monotonic);
-                    },
-                    SDL.SDL_KEYUP => {
-                        // TODO: Make use of compare_and_xor?
-                        const key_code = event.key.keysym.sym;
-                        var keyinput: KeyInput = .{ .raw = 0x0000 };
-
-                        switch (key_code) {
-                            SDL.SDLK_UP => keyinput.up.set(),
-                            SDL.SDLK_DOWN => keyinput.down.set(),
-                            SDL.SDLK_LEFT => keyinput.left.set(),
-                            SDL.SDLK_RIGHT => keyinput.right.set(),
-                            SDL.SDLK_x => keyinput.a.set(),
-                            SDL.SDLK_z => keyinput.b.set(),
-                            SDL.SDLK_a => keyinput.shoulder_l.set(),
-                            SDL.SDLK_s => keyinput.shoulder_r.set(),
-                            SDL.SDLK_RETURN => keyinput.start.set(),
-                            SDL.SDLK_RSHIFT => keyinput.select.set(),
-                            else => {},
-                        }
-
-                        bus_ptr.io.keyinput.fetchOr(keyinput.raw, .Monotonic);
-                    },
-                    SDL.SDL_WINDOWEVENT => {
-                        if (event.window.event == SDL.SDL_WINDOWEVENT_RESIZED) {
-                            log.debug("window resized to: {}x{}", .{ event.window.data1, event.window.data2 });
-
-                            win_dim.width = @intCast(u32, event.window.data1);
-                            win_dim.height = @intCast(u32, event.window.data2);
-                        }
-                    },
-                    else => {},
-                }
-            }
-
-            var zgui_redraw: bool = false;
-
-            switch (self.state.emulation) {
-                .Transition => |inner| switch (inner) {
-                    .Active => {
-                        ch.send(.Resume);
-                        if (!config.config().host.mute) SDL.SDL_PauseAudioDevice(self.audio.device, 0);
-
-                        self.state.emulation = .Active;
-                    },
-                    .Inactive => {
-                        // Assert that double pausing is impossible
-
-                        SDL.SDL_PauseAudioDevice(self.audio.device, 1);
-                        ch.send(.Pause);
-
-                        self.state.emulation = .Inactive;
-                    },
-                },
-                .Active => {
-                    const is_std = mode == .Standard;
-
-                    if (is_std) ch.send(.Pause);
-                    defer if (is_std) ch.send(.Resume);
-
-                    // switch (mode) {
-                    //     .Standard => blk: {
-                    //         const limit = 15; // TODO: What should this be?
-
-                    //         // TODO: learn more about std.atomic.spinLoopHint();
-                    //         for (0..limit) |_| {
-                    //             const message = channel.gui.pop() orelse continue;
-
-                    //             switch (message) {
-                    //                 .Paused => break :blk,
-                    //                 .Quit => unreachable,
-                    //             }
-                    //         }
-
-                    //         log.info("timed out waiting for emu thread to pause (limit: {})", .{limit});
-                    //         break :skip_draw;
-                    //     },
-                    //     .Debug => blk: {
-                    //         switch (channel.gui.pop() orelse break :blk) {
-                    //             .Paused => unreachable, // only in standard mode
-                    //             .Quit => break :emu_loop, // FIXME: gdb side of emu is seriously out-of-date...
-                    //         }
-                    //     },
-                    // }
-
-                    // Add FPS count to the histogram
-                    if (tracker) |t| self.state.fps_hist.push(t.value()) catch {};
-
-                    // Draw GBA Screen to Texture
-                    {
-                        gl.bindFramebuffer(gl.FRAMEBUFFER, fbo_id);
-                        defer gl.bindFramebuffer(gl.FRAMEBUFFER, 0);
-
-                        const buf = bus_ptr.ppu.framebuf.get(.Renderer);
-                        gl.viewport(0, 0, gba_width, gba_height);
-                        opengl_impl.drawScreenTexture(emu_tex, prog_id, objects, buf);
-                    }
-
-                    // FIXME: We only really care about locking the audio device (and therefore writing silence)
-                    // since if nfd-zig is used the emu may be paused for way too long. Perhaps we should try and limit
-                    // spurious calls to SDL_LockAudioDevice?
-                    SDL.SDL_LockAudioDevice(self.audio.device);
-                    defer SDL.SDL_UnlockAudioDevice(self.audio.device);
-
-                    zgui_redraw = imgui.draw(&self.state, win_dim, out_tex, cpu);
-                },
-                .Inactive => zgui_redraw = imgui.draw(&self.state, win_dim, out_tex, cpu),
-            }
-
-            if (zgui_redraw) {
-                // Background Colour
-                const size = zgui.io.getDisplaySize();
-                gl.viewport(0, 0, @floatToInt(GLsizei, size[0]), @floatToInt(GLsizei, size[1]));
-                gl.clearColor(0, 0, 0, 1.0);
-                gl.clear(gl.COLOR_BUFFER_BIT);
-
-                zgui.backend.draw();
-            }
-
-            SDL.SDL_GL_SwapWindow(self.window);
-        }
-
-        ch.send(.Quit);
-    }
-
-    fn glGetProcAddress(ctx: SDL.SDL_GLContext, proc: [:0]const u8) ?*anyopaque {
-        _ = ctx;
-        return SDL.SDL_GL_GetProcAddress(proc.ptr);
-    }
-};
-
-const Audio = struct {
-    const Self = @This();
-    const log = std.log.scoped(.PlatformAudio);
-
-    device: SDL.SDL_AudioDeviceID,
-
-    fn init(apu: *Apu) Self {
-        var have: SDL.SDL_AudioSpec = undefined;
-        var want: SDL.SDL_AudioSpec = std.mem.zeroes(SDL.SDL_AudioSpec);
-        want.freq = sample_rate;
-        want.format = sample_format;
-        want.channels = 2;
-        want.samples = 0x100;
-        want.callback = Self.callback;
-        want.userdata = apu;
-
-        std.debug.assert(sample_format == SDL.AUDIO_U16);
-        log.info("Host Sample Rate: {}Hz, Host Format: SDL.AUDIO_U16", .{sample_rate});
-
-        const device = SDL.SDL_OpenAudioDevice(null, 0, &want, &have, 0);
-        if (device == 0) panic();
-
-        return .{ .device = device };
-    }
-
-    fn deinit(self: *Self) void {
-        SDL.SDL_CloseAudioDevice(self.device);
-        self.* = undefined;
-    }
-
-    export fn callback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void {
-        const T = *Apu;
-        const apu = @ptrCast(T, @alignCast(@alignOf(T), userdata));
-
-        _ = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
-    }
-};
-
-fn panic() noreturn {
-    const str = @as(?[*:0]const u8, SDL.SDL_GetError()) orelse "unknown error";
-    @panic(std.mem.sliceTo(str, 0));
-}
-
-const opengl_impl = struct {
-    // zig fmt: off
-    const vertices: [32]f32 = [_]f32{
-        // Positions        // Colours      // Texture Coords
-         1.0, -1.0, 0.0,    1.0, 0.0, 0.0,  1.0, 1.0, // Top Right
-         1.0,  1.0, 0.0,    0.0, 1.0, 0.0,  1.0, 0.0, // Bottom Right
-        -1.0,  1.0, 0.0,    0.0, 0.0, 1.0,  0.0, 0.0, // Bottom Left
-        -1.0, -1.0, 0.0,    1.0, 1.0, 0.0,  0.0, 1.0, // Top Left
-    };
-
-    const indices: [6]u32 = [_]u32{
-        0, 1, 3, // First Triangle
-        1, 2, 3, // Second Triangle
-    };
-    // zig fmt: on
-
-    const Objects = struct { vao: GLuint, vbo: GLuint, ebo: GLuint };
-
-    fn drawScreenTexture(tex_id: GLuint, prog_id: GLuint, ids: Objects, buf: []const u8) void {
         gl.bindTexture(gl.TEXTURE_2D, tex_id);
         defer gl.bindTexture(gl.TEXTURE_2D, 0);
 
         gl.texSubImage2D(gl.TEXTURE_2D, 0, 0, 0, gba_width, gba_height, gl.RGBA, gl.UNSIGNED_INT_8_8_8_8, buf.ptr);
 
         // Bind VAO, EBO. VBO not bound
-        gl.bindVertexArray(ids.vao); // VAO
+        gl.bindVertexArray(obj_ids[0]); // VAO
         defer gl.bindVertexArray(0);
 
-        gl.bindBuffer(gl.ELEMENT_ARRAY_BUFFER, ids.ebo); // EBO
+        gl.bindBuffer(gl.ELEMENT_ARRAY_BUFFER, obj_ids[2]); // EBO
         defer gl.bindBuffer(gl.ELEMENT_ARRAY_BUFFER, 0);
 
         // Use compiled frag + vertex shader
-        gl.useProgram(prog_id);
+        gl.useProgram(self.program_id);
         defer gl.useProgram(0);
 
         gl.drawElements(gl.TRIANGLES, 6, gl.UNSIGNED_INT, null);
@@ -397,7 +160,7 @@ const opengl_impl = struct {
     }
 
     // Returns the VAO ID since it's used in run()
-    fn createObjects() Objects {
+    fn genBufferObjects() struct { GLuint, GLuint, GLuint } {
         var vao_id: GLuint = undefined;
         var vbo_id: GLuint = undefined;
         var ebo_id: GLuint = undefined;
@@ -428,10 +191,10 @@ const opengl_impl = struct {
         gl.vertexAttribPointer(2, 2, gl.FLOAT, gl.FALSE, 8 * @sizeOf(f32), @intToPtr(?*anyopaque, (6 * @sizeOf(f32))));
         gl.enableVertexAttribArray(2);
 
-        return .{ .vao = vao_id, .vbo = vbo_id, .ebo = ebo_id };
+        return .{ vao_id, vbo_id, ebo_id };
     }
 
-    fn createScreenTexture(buf: []const u8) GLuint {
+    fn genGbaTexture(buf: []const u8) GLuint {
         var tex_id: GLuint = undefined;
         gl.genTextures(1, &tex_id);
 
@@ -446,7 +209,7 @@ const opengl_impl = struct {
         return tex_id;
     }
 
-    fn createOutputTexture() GLuint {
+    fn genOutTexture() GLuint {
         var tex_id: GLuint = undefined;
         gl.genTextures(1, &tex_id);
 
@@ -461,7 +224,7 @@ const opengl_impl = struct {
         return tex_id;
     }
 
-    fn createFrameBuffer(tex_id: GLuint) !GLuint {
+    fn genFrameBufObject(tex_id: c_uint) !GLuint {
         var fbo_id: GLuint = undefined;
         gl.genFramebuffers(1, &fbo_id);
 
@@ -479,25 +242,202 @@ const opengl_impl = struct {
         return fbo_id;
     }
 
-    const shader = struct {
+    const RunOptions = struct {
-        const Kind = enum { vertex, fragment };
+        channel: *TwoWayChannel,
-        const log = std.log.scoped(.Shader);
+        tracker: ?*FpsTracker = null,
-
+        cpu: *Arm7tdmi,
-        fn didCompile(id: gl.GLuint) bool {
+        scheduler: *Scheduler,
-            var success: gl.GLint = undefined;
-            gl.getShaderiv(id, gl.COMPILE_STATUS, &success);
-
-            if (success == 0) err(id);
-
-            return success == 1;
-        }
-
-        fn err(id: gl.GLuint) void {
-            const buf_len = 512;
-            var error_msg: [buf_len]u8 = undefined;
-
-            gl.getShaderInfoLog(id, buf_len, 0, &error_msg);
-            log.err("{s}", .{std.mem.sliceTo(&error_msg, 0)});
-        }
     };
+
+    pub fn run(self: *Self, opt: RunOptions) !void {
+        const cpu = opt.cpu;
+        const tracker = opt.tracker;
+        const channel = opt.channel;
+
+        const obj_ids = Self.genBufferObjects();
+        defer gl.deleteBuffers(3, @as(*const [3]c_uint, &obj_ids));
+
+        const emu_tex = Self.genGbaTexture(cpu.bus.ppu.framebuf.get(.Renderer));
+        const out_tex = Self.genOutTexture();
+        defer gl.deleteTextures(2, &[_]c_uint{ emu_tex, out_tex });
+
+        const fbo_id = try Self.genFrameBufObject(out_tex);
+        defer gl.deleteFramebuffers(1, &fbo_id);
+
+        emu_loop: while (true) {
+            // `quit` from RunOptions may be modified by the GDBSTUB thread,
+            // so we want to recognize that it may change to `true` and exit the GUI thread
+            if (channel.gui.pop()) |event| switch (event) {
+                .Quit => break :emu_loop,
+                .Paused => @panic("TODO: We want to peek (and then pop if it's .Quit), not always pop"),
+            };
+
+            // Outside of `SDL.SDL_QUIT` below, the DearImgui UI might signal that the program
+            // should exit, in which case we should also handle this
+            if (self.state.should_quit) break :emu_loop;
+
+            var event: SDL.SDL_Event = undefined;
+            while (SDL.SDL_PollEvent(&event) != 0) {
+                _ = zgui.backend.processEvent(&event);
+
+                switch (event.type) {
+                    SDL.SDL_QUIT => break :emu_loop,
+                    SDL.SDL_KEYDOWN => {
+                        const key_code = event.key.keysym.sym;
+                        var keyinput = cpu.bus.io.keyinput.load(.Monotonic);
+
+                        switch (key_code) {
+                            SDL.SDLK_UP => keyinput.up.unset(),
+                            SDL.SDLK_DOWN => keyinput.down.unset(),
+                            SDL.SDLK_LEFT => keyinput.left.unset(),
+                            SDL.SDLK_RIGHT => keyinput.right.unset(),
+                            SDL.SDLK_x => keyinput.a.unset(),
+                            SDL.SDLK_z => keyinput.b.unset(),
+                            SDL.SDLK_a => keyinput.shoulder_l.unset(),
+                            SDL.SDLK_s => keyinput.shoulder_r.unset(),
+                            SDL.SDLK_RETURN => keyinput.start.unset(),
+                            SDL.SDLK_RSHIFT => keyinput.select.unset(),
+                            else => {},
+                        }
+
+                        cpu.bus.io.keyinput.store(keyinput.raw, .Monotonic);
+                    },
+                    SDL.SDL_KEYUP => {
+                        const key_code = event.key.keysym.sym;
+                        var keyinput = cpu.bus.io.keyinput.load(.Monotonic);
+
+                        switch (key_code) {
+                            SDL.SDLK_UP => keyinput.up.set(),
+                            SDL.SDLK_DOWN => keyinput.down.set(),
+                            SDL.SDLK_LEFT => keyinput.left.set(),
+                            SDL.SDLK_RIGHT => keyinput.right.set(),
+                            SDL.SDLK_x => keyinput.a.set(),
+                            SDL.SDLK_z => keyinput.b.set(),
+                            SDL.SDLK_a => keyinput.shoulder_l.set(),
+                            SDL.SDLK_s => keyinput.shoulder_r.set(),
+                            SDL.SDLK_RETURN => keyinput.start.set(),
+                            SDL.SDLK_RSHIFT => keyinput.select.set(),
+                            else => {},
+                        }
+
+                        cpu.bus.io.keyinput.store(keyinput.raw, .Monotonic);
+                    },
+                    else => {},
+                }
+            }
+
+            {
+                channel.emu.push(.Pause);
+                defer channel.emu.push(.Resume);
+
+                // Spin Loop until we know that the emu is paused
+                wait: while (true) switch (channel.gui.pop() orelse continue) {
+                    .Paused => break :wait,
+                    else => |any| std.debug.panic("[Gui/Channel]: Unhandled Event: {}", .{any}),
+                };
+
+                // Add FPS count to the histogram
+                if (tracker) |t| self.state.fps_hist.push(t.value()) catch {};
+
+                // Draw GBA Screen to Texture
+                {
+                    gl.bindFramebuffer(gl.FRAMEBUFFER, fbo_id);
+                    defer gl.bindFramebuffer(gl.FRAMEBUFFER, 0);
+
+                    const buf = cpu.bus.ppu.framebuf.get(.Renderer);
+                    gl.viewport(0, 0, gba_width, gba_height);
+                    self.drawGbaTexture(obj_ids, emu_tex, buf);
+                }
+
+                // Background Colour
+                const size = zgui.io.getDisplaySize();
+                gl.viewport(0, 0, @floatToInt(c_int, size[0]), @floatToInt(c_int, size[1]));
+                gl.clearColor(0, 0, 0, 1.0);
+                gl.clear(gl.COLOR_BUFFER_BIT);
+
+                zgui.backend.newFrame(width, height);
+                imgui.draw(&self.state, out_tex, cpu);
+                zgui.backend.draw();
+            }
+
+            SDL.SDL_GL_SwapWindow(self.window);
+        }
+
+        channel.emu.push(.Quit);
+    }
+
+    fn glGetProcAddress(ctx: SDL.SDL_GLContext, proc: [:0]const u8) ?*anyopaque {
+        _ = ctx;
+        return SDL.SDL_GL_GetProcAddress(proc.ptr);
+    }
 };
+
+const Audio = struct {
+    const Self = @This();
+    const log = std.log.scoped(.PlatformAudio);
+
+    device: SDL.SDL_AudioDeviceID,
+
+    fn init(apu: *Apu) Self {
+        var have: SDL.SDL_AudioSpec = undefined;
+        var want: SDL.SDL_AudioSpec = std.mem.zeroes(SDL.SDL_AudioSpec);
+        want.freq = sample_rate;
+        want.format = sample_format;
+        want.channels = 2;
+        want.samples = 0x100;
+        want.callback = Self.callback;
+        want.userdata = apu;
+
+        std.debug.assert(sample_format == SDL.AUDIO_U16);
+        log.info("Host Sample Rate: {}Hz, Host Format: SDL.AUDIO_U16", .{sample_rate});
+
+        const device = SDL.SDL_OpenAudioDevice(null, 0, &want, &have, 0);
+        if (device == 0) panic();
+
+        if (!config.config().host.mute) {
+            SDL.SDL_PauseAudioDevice(device, 0); // Unpause Audio
+            log.info("Unpaused Device", .{});
+        }
+
+        return .{ .device = device };
+    }
+
+    fn deinit(self: *Self) void {
+        SDL.SDL_CloseAudioDevice(self.device);
+        self.* = undefined;
+    }
+
+    export fn callback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void {
+        const T = *Apu;
+        const apu = @ptrCast(T, @alignCast(@alignOf(T), userdata));
+
+        _ = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
+    }
+};
+
+const shader = struct {
+    const Kind = enum { vertex, fragment };
+    const log = std.log.scoped(.Shader);
+
+    fn didCompile(id: gl.GLuint) bool {
+        var success: gl.GLint = undefined;
+        gl.getShaderiv(id, gl.COMPILE_STATUS, &success);
+
+        if (success == 0) err(id);
+
+        return success == 1;
+    }
+
+    fn err(id: gl.GLuint) void {
+        const buf_len = 512;
+        var error_msg: [buf_len]u8 = undefined;
+
+        gl.getShaderInfoLog(id, buf_len, 0, &error_msg);
+        log.err("{s}", .{std.mem.sliceTo(&error_msg, 0)});
+    }
+};
+
+fn panic() noreturn {
+    const str = @as(?[*:0]const u8, SDL.SDL_GetError()) orelse "unknown error";
+    @panic(std.mem.sliceTo(str, 0));
+}

src/util.zig

@@ -3,7 +3,7 @@ const builtin = @import("builtin");
 const config = @import("config.zig");
 
 const Log2Int = std.math.Log2Int;
-const Arm7tdmi = @import("arm32").Arm7tdmi;
+const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
 
 const Allocator = std.mem.Allocator;
 
@@ -260,7 +260,7 @@ pub const FrameBuffer = struct {
 
     pub fn init(allocator: Allocator, comptime len: comptime_int) !Self {
         const buf = try allocator.alloc(u8, len * 2);
-        @memset(buf, 0);
+        std.mem.set(u8, buf, 0);
 
         return .{
             // Front and Back Framebuffers
@@ -272,7 +272,7 @@ pub const FrameBuffer = struct {
     }
 
     pub fn reset(self: *Self) void {
-        @memset(self.buf, 0);
+        std.mem.set(u8, self.buf, 0);
         self.current = 0;
     }