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paoda:april-fools
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compare: paoda:d798aea6eaa0523e8a96051b844e3e83f3be9572
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paoda:main
paoda:april-fools
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paoda:apu-things

2 Commits
887bd89668 ... d798aea6ea

Author SHA1 Message Date
Rekai Nyangadzayi Musuka d798aea6ea fix: force align DMA transfers 2022-06-29 04:31:02 -03:00
Rekai Nyangadzayi Musuka 5d37c212e2 fix: resolve bugs in VRAM unpredictable read/writes 2022-06-29 03:59:14 -03:00
2 changed files with 13 additions and 16 deletions
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6
src/bus/dma.zig
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@ -182,10 +182,12 @@ fn DmaController(comptime id: u2) type {
const transfer_type = is_fifo or self.cnt.transfer_type.read();
const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
if (transfer_type) {
cpu.bus.write(u32, self._dad, cpu.bus.read(u32, self._sad));
cpu.bus.write(u32, self._dad & mask, cpu.bus.read(u32, self._sad & mask));
} else {
cpu.bus.write(u16, self._dad, cpu.bus.read(u16, self._sad));
cpu.bus.write(u16, self._dad & mask, cpu.bus.read(u16, self._sad & mask));
}
switch (sad_adj) {

23
src/ppu.zig
View File

@ -658,11 +658,8 @@ const Palette = struct {
switch (T) {
u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
u8 => {
const halfword: u16 = @as(u16, value) * 0x0101;
// FIXME: I don't think my comment here makes sense?
const weird_addr = addr & ~@as(u32, 1); // *was* 8-bit read so address won't be aligned
std.mem.writeIntSliceLittle(u16, self.buf[weird_addr..(weird_addr + @sizeOf(u16))], halfword);
const align_addr = addr & ~@as(u32, 1); // Aligned to Halfword boundary
std.mem.writeIntSliceLittle(u16, self.buf[align_addr..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
},
else => @compileError("PALRAM: Unsupported write width"),
}
@ -705,21 +702,19 @@ const Vram = struct {
pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address: usize, value: T) void {
const mode: u3 = dispcnt.bg_mode.read();
const addr = Self.mirror(address);
const idx = Self.mirror(address);
switch (T) {
u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[idx..][0..@sizeOf(T)], value),
u8 => {
// Ignore if write is in OBJ
// Ignore write if it falls within the boundaries of OBJ VRAM
switch (mode) {
0, 1, 2 => if (0x0601_0000 <= address and address < 0x0601_8000) return,
else => if (0x0601_4000 <= address and address < 0x0601_8000) return,
0, 1, 2 => if (0x0001_0000 <= idx) return,
else => if (0x0001_4000 <= idx) return,
}
const halfword: u16 = @as(u16, value) * 0x0101;
const weird_addr = addr & ~@as(u32, 1);
std.mem.writeIntSliceLittle(u16, self.buf[weird_addr..(weird_addr + @sizeOf(u16))], halfword);
const align_idx = idx & ~@as(u32, 1); // Aligned to a halfword boundary
std.mem.writeIntSliceLittle(u16, self.buf[align_idx..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
},
else => @compileError("VRAM: Unsupported write width"),
}