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fix: force align DMA transfers

This commit is contained in:
Rekai Nyangadzayi Musuka 2022-06-29 04:31:02 -03:00
parent 5d37c212e2
commit d798aea6ea
1 changed files with 4 additions and 2 deletions
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6
src/bus/dma.zig
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@ -182,10 +182,12 @@ fn DmaController(comptime id: u2) type {
const transfer_type = is_fifo or self.cnt.transfer_type.read();
const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
if (transfer_type) {
cpu.bus.write(u32, self._dad, cpu.bus.read(u32, self._sad));
cpu.bus.write(u32, self._dad & mask, cpu.bus.read(u32, self._sad & mask));
} else {
cpu.bus.write(u16, self._dad, cpu.bus.read(u16, self._sad));
cpu.bus.write(u16, self._dad & mask, cpu.bus.read(u16, self._sad & mask));
}
switch (sad_adj) {