|  | efc7d817db | feat: Mode 0 MVP | 2022-10-21 05:12:20 -03:00 |  | 
			
				
					|  | 1b17b1eb0c | chore: use zig slices for fun | 2022-10-21 05:12:20 -03:00 |  | 
			
				
					|  | fab6d4c2a2 | chore: give DISPCNT DISPSTAT and VCOUNT to PPU struct | 2022-10-21 05:12:20 -03:00 |  | 
			
				
					|  | 223a3403c0 | chore: give io read/write functions access to the entire Bus | 2022-10-21 05:12:20 -03:00 |  | 
			
				
					|  | dfd0d064de | feat: implement BG Scrolling Registers | 2022-10-21 05:12:19 -03:00 |  | 
			
				
					|  | 0c4882e658 | feat: impelemnt BG0,1,2CNT and IF | 2022-10-21 05:12:19 -03:00 |  | 
			
				
					|  | bfdad9fa32 | feat: implement OAM | 2022-10-21 05:12:19 -03:00 |  | 
			
				
					|  | 37fd8dab84 | chore: squash bugs preventing swi_demo.gba from working | 2022-10-21 05:12:19 -03:00 |  | 
			
				
					|  | c143aefb01 | chore(cpu): reimplement bank switching logic | 2022-10-21 05:12:19 -03:00 |  | 
			
				
					|  | 05bf245b5a | fix: don't mask away MSB in THUMB.5 add | 2022-10-21 05:12:19 -03:00 |  | 
			
				
					|  | f9e7128061 | fix: properly decode format 11 instructions | 2022-10-21 05:12:18 -03:00 |  | 
			
				
					|  | 603e4b6fdf | chore: make use of scoped logging | 2022-10-21 05:12:18 -03:00 |  | 
			
				
					|  | 599a1f2973 | chore: remove TODOs and some useless imports | 2022-10-21 05:12:18 -03:00 |  | 
			
				
					|  | 22424ca69c | fix: improper condition check and initialization of register | 2022-10-21 05:12:18 -03:00 |  | 
			
				
					|  | 67a785cc22 | fix(cpu): force align thumb and arm block data transfers | 2022-10-21 05:12:18 -03:00 |  | 
			
				
					|  | 4eb3842606 | feat: pass arm.gba | 2022-10-21 05:12:17 -03:00 |  | 
			
				
					|  | 1ee8b51b2b | chore: reimplement ARM LDM/STM | 2022-10-21 05:12:17 -03:00 |  | 
			
				
					|  | 130310e5cc | chore: improve arm ldm/stm | 2022-10-21 05:12:17 -03:00 |  | 
			
				
					|  | e933d7e5c7 | fix(cpu): force-align SWP reads and writes | 2022-10-21 05:12:17 -03:00 |  | 
			
				
					|  | 44e8b5b882 | fix: force-align ARM STRH reads | 2022-10-21 05:12:17 -03:00 |  | 
			
				
					|  | 28361e8b7d | fix: implement the same LDRSH logic as THUMB LDRSH | 2022-10-21 05:12:16 -03:00 |  | 
			
				
					|  | 75921d6413 | fix: PC is 12 ahead when it is rd in str and strb | 2022-10-21 05:12:16 -03:00 |  | 
			
				
					|  | 17226d8f75 | fix: listen to my past self By deleting this line I go from test 234 to test 355 in arm.gba | 2022-10-21 05:12:16 -03:00 |  | 
			
				
					|  | 2cb1bf834a | chore: dont use std.mem.bytesToValue the stdlib accounts for endianness, which isn't something we want. | 2022-10-21 05:12:16 -03:00 |  | 
			
				
					|  | 8006ca31e6 | chore: remove unnecessary @as calls | 2022-10-21 05:12:16 -03:00 |  | 
			
				
					|  | 82b92b4733 | feat: pass thumb.gba | 2022-10-21 05:12:15 -03:00 |  | 
			
				
					|  | bf42d3ae2f | chore: account for empty rlist in THUMB LDM/STM | 2022-10-21 05:12:15 -03:00 |  | 
			
				
					|  | f63ae76931 | fix(cpu): handle edge case in LDRSH | 2022-10-21 05:12:15 -03:00 |  | 
			
				
					|  | f046787523 | chore: reorganize util.zig | 2022-10-21 05:12:15 -03:00 |  | 
			
				
					|  | bbd73550e8 | fix: zero initialize all allocated memory | 2022-10-21 05:12:15 -03:00 |  | 
			
				
					|  | 4776dc0788 | Revert "fix: allow for 32-bit reads to KEYINPUT" This reverts commit 3a51707280. | 2022-10-21 05:12:14 -03:00 |  | 
			
				
					|  | d8bd6da563 | fix: resolve decoding mixup in THUMB format 8 instructions | 2022-10-21 05:12:14 -03:00 |  | 
			
				
					|  | b569a32170 | fix: allow for 32-bit reads to KEYINPUT | 2022-10-21 05:12:14 -03:00 |  | 
			
				
					|  | 06e20666bd | chore: refactor ARMv4 decoding | 2022-10-21 05:12:14 -03:00 |  | 
			
				
					|  | 36687c5c67 | chore: add more debug information to CPU panic method | 2022-10-21 05:12:14 -03:00 |  | 
			
				
					|  | dd9b20030a | chore: give more descriptive panic messages when changing mode fails | 2022-10-21 05:12:13 -03:00 |  | 
			
				
					|  | c0db2a987b | chore: clean up THUMB instruction decoding | 2022-10-21 05:12:13 -03:00 |  | 
			
				
					|  | c3ff2ed6c1 | feat: parse cartridge header | 2022-10-21 05:12:13 -03:00 |  | 
			
				
					|  | 271f42cf0e | feat: rename ARM and THUMB SWI functions | 2022-10-21 05:12:13 -03:00 |  | 
			
				
					|  | 01e15584da | chore: group THUMB and select ARM instructions together (same file) | 2022-10-21 05:12:13 -03:00 |  | 
			
				
					|  | 17b91db2ef | feat: integrate zig-clap with ZBA | 2022-10-21 05:12:13 -03:00 |  | 
			
				
					|  | 3e786d02ac | fix(cpu): properly decode format 7 and 8 | 2022-10-21 05:12:12 -03:00 |  | 
			
				
					|  | c8f2db69df | fix(cpu): resolve edge cases in THUMB Format 5 | 2022-10-21 05:12:12 -03:00 |  | 
			
				
					|  | b4e0682801 | fix(cpu): allow for select values to overflow FuzzARM found these operations which panicked, when they should
have overflowed. These are now fixed
n = 8000 | 2022-10-21 05:12:12 -03:00 |  | 
			
				
					|  | af10c1b076 | feat(cpu): implement format 13 While bugs do exist, at this point all THUMB and ARMv4 instructions
have been implemented! Yay! | 2022-10-21 05:12:12 -03:00 |  | 
			
				
					|  | e6a0eab667 | feat(cpu): implement THUMB format 17 | 2022-10-21 05:12:12 -03:00 |  | 
			
				
					|  | 523b9d2736 | feat(cpu): implement THUMB format11 | 2022-10-21 05:12:12 -03:00 |  | 
			
				
					|  | 011d2f2f2a | chore: update to latest zig nightly | 2022-10-21 05:12:11 -03:00 |  | 
			
				
					|  | c37546d273 | chore: progress towards passing ldr/str thumb in armwrestler | 2022-10-21 05:12:11 -03:00 |  | 
			
				
					|  | fbedebb938 | fix(cpu): properly negate in NEG | 2022-10-21 05:12:11 -03:00 |  |