chore: refactor ARMv4 decoding
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36687c5c67
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06e20666bd
146
src/cpu.zig
146
src/cpu.zig
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@ -545,92 +545,66 @@ fn armPopulate() [0x1000]ArmInstrFn {
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var i: usize = 0;
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while (i < lut.len) : (i += 1) {
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// Instructions with Opcode[27] == 0
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if (i == 0x121) {
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// Bits 27:20 and 7:4
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lut[i] = branchAndExchange;
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} else if (i >> 6 & 0x3F == 0b000000 and i & 0xF == 0b1001) {
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// Bits 27:22 and 7:4
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const A = i >> 5 & 1 == 1;
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const S = i >> 4 & 1 == 1;
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lut[i] = multiply(A, S);
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} else if (i >> 7 & 0x1F == 0b00010 and i >> 4 & 0x3 == 0b00 and i & 0xF == 0b1001) {
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// Bits 27:23, 21:20 and 7:4
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const B = i >> 6 & 1 == 1;
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lut[i] = singleDataSwap(B);
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} else if (i >> 7 & 0x1F == 0b00001 and i & 0xF == 0b1001) {
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// Bits 27:23 and bits 7:4
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const U = i >> 6 & 1 == 1;
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const A = i >> 5 & 1 == 1;
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const S = i >> 4 & 1 == 1;
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lut[i] = multiplyLong(U, A, S);
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} else if (i >> 9 & 0x7 == 0b000 and i >> 3 & 1 == 1 and i & 1 == 1) {
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// Bits 27:25, 7 and 4
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const I = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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lut[i] = halfAndSignedDataTransfer(P, U, I, W, L);
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} else if (i >> 9 & 0x7 == 0b011 and i & 1 == 1) {
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// Bits 27:25 and 4
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lut[i] = armUndefined;
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} else if (i >> 10 & 0x3 == 0b00 and i >> 7 & 0x3 == 0b10 and i >> 4 & 1 == 0) {
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// Bits 27:26, 24:23 and 20
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const I = i >> 9 & 1 == 1;
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const R = i >> 6 & 1 == 1;
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const kind = i >> 4 & 0x3;
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lut[i] = psrTransfer(I, R, kind);
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} else if (i >> 10 & 0x3 == 0b01) {
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// Bits 27:26
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const I = i >> 9 & 1 == 1;
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const B = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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lut[i] = singleDataTransfer(I, P, U, B, W, L);
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} else if (i >> 10 & 0x3 == 0b00) {
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// Bits 27:26
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const I = i >> 9 & 1 == 1;
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const S = i >> 4 & 1 == 1;
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const instrKind = i >> 5 & 0xF;
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lut[i] = dataProcessing(I, S, instrKind);
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}
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// Instructions with Opcode[27] == 1
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if (i >> 8 & 0xF == 0b1110) {
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// bits 27:24
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// Coprocessor Data Opertation + Register Transfer
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lut[i] = armUndefined;
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} else if (i >> 9 & 0x7 == 0b100) {
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// Bits 27:25
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const S = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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lut[i] = blockDataTransfer(P, U, S, W, L);
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} else if (i >> 9 & 0x7 == 0b101) {
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// Bits 27:25
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const L = i >> 8 & 1 == 1;
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lut[i] = branch(L);
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} else if (i >> 9 & 0x7 == 0b110) {
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// Bits 27:25
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// Coprocessor Data Transfer
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lut[i] = armUndefined;
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} else if (i >> 8 & 0xF == 0b1111) {
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// Bits 27:24
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lut[i] = armSoftwareInterrupt();
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}
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lut[i] = switch (@as(u2, i >> 10)) {
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0b00 => if (i == 0x121) blk: {
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break :blk branchAndExchange;
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} else if (i & 0xFCF == 0x009) blk: {
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const A = i >> 5 & 1 == 1;
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const S = i >> 4 & 1 == 1;
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break :blk multiply(A, S);
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} else if (i & 0xFBF == 0x109) blk: {
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const B = i >> 6 & 1 == 1;
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break :blk singleDataSwap(B);
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} else if (i & 0xF8F == 0x089) blk: {
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const U = i >> 6 & 1 == 1;
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const A = i >> 5 & 1 == 1;
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const S = i >> 4 & 1 == 1;
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break :blk multiplyLong(U, A, S);
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} else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: {
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const I = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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break :blk halfAndSignedDataTransfer(P, U, I, W, L);
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} else if (i & 0xD90 == 0x100) blk: {
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const I = i >> 9 & 1 == 1;
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const R = i >> 6 & 1 == 1;
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const kind = i >> 4 & 0x3;
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break :blk psrTransfer(I, R, kind);
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} else blk: {
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const I = i >> 9 & 1 == 1;
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const S = i >> 4 & 1 == 1;
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const instrKind = i >> 5 & 0xF;
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break :blk dataProcessing(I, S, instrKind);
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},
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0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) armUndefined else blk: {
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const I = i >> 9 & 1 == 1;
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const B = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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break :blk singleDataTransfer(I, P, U, B, W, L);
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},
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else => switch (@as(u2, i >> 9 & 0x3)) {
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// MSB is guaranteed to be 1
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0b00 => blk: {
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const P = i >> 8 & 1 == 1;
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const U = i >> 7 & 1 == 1;
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const S = i >> 6 & 1 == 1;
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const W = i >> 5 & 1 == 1;
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const L = i >> 4 & 1 == 1;
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break :blk blockDataTransfer(P, U, S, W, L);
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},
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0b01 => blk: {
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const L = i >> 8 & 1 == 1;
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break :blk branch(L);
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},
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0b10 => armUndefined, // COP Data Transfer
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0b11 => if (i >> 8 & 1 == 1) armSoftwareInterrupt() else armUndefined, // COP Data Operation + Register Transfer
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},
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};
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}
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return lut;
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