2851c140ea
fix(cpu): use LUT for ARM condition codes
2022-11-01 08:29:42 -03:00
637d81ce44
chore(bus): only perform one allocation for fastmem tables
2022-11-01 07:04:42 -03:00
bc52461f0f
fix(bus): replace write table with two tables for u32/u8 and u8 writes
2022-11-01 07:00:07 -03:00
c395c04a6e
feat(bus): implement fastmem
...
+100 fps in Pokemon Emerald lol
2022-11-01 06:18:12 -03:00
af8ec4db5b
chore: go through TODOs and FIXMEs
...
mainly deleting / rewording those that no longer apply
2022-10-31 06:17:09 -03:00
5d47e5d167
fix(io): force-align all i/o reads
...
Of course, backups being the exception due to flash or sram quirks,
I don't remember lol
2022-10-31 05:50:27 -03:00
5101fbd809
feat(io): pass all suite.gba i/o read tests
2022-10-31 05:22:11 -03:00
472457b9f3
chore: make use of comptime control flow when working with tuples
2022-10-31 05:14:20 -03:00
2ef4bb7dcc
revert(apu): switch from f32 44.1kHz to u16 32.768kHz
2022-10-31 05:14:20 -03:00
9a732ea6f8
chore(i/o): ensure interrupt i/o exists
2022-10-31 05:14:20 -03:00
ca67ca3183
fix(apu): only enable dma sound fifo after manual write
2022-10-30 03:48:12 -03:00
47fc49deb6
fix(audio): add asserts where I assume audio format
2022-10-30 03:25:49 -03:00
472215b4c2
feat(ppu): implement all i/o writes
2022-10-30 03:11:04 -03:00
c9a423d094
fix(ppu): resolve mistakes in ppu i/o reads
2022-10-30 02:15:26 -03:00
1d163fa56f
feat(apu): implement all apu i/o writes
2022-10-30 02:02:23 -03:00
13710a3236
feat(timer): implement all timer i/o writes
2022-10-30 01:18:46 -03:00
6154585e77
feat(dma): implement all dma i/o writes
2022-10-30 01:04:22 -03:00
7debdc490d
fix(io): resovle off-by-one errors in i/o register ranges
2022-10-29 05:23:05 -03:00
58375795bf
fix(ppu): apply proper masks to ppu i/o
...
Refactor Window, and bldcnt, bldalpha, bldy
2022-10-29 05:18:53 -03:00
f0dca29836
fix(dma): apply proper masks to dma i/o
2022-10-29 04:53:21 -03:00
c75682dbd4
fix(apu): some invalid i/o registers should read 0x0000
2022-10-29 04:29:44 -03:00
36832ba1fb
feat(apu): impelement all apu i/o reads
2022-10-29 04:24:06 -03:00
647bd83224
chore(io): rewrite certain error messages
...
We can do this now that we know that it won't be because of any
unimplemented feature in some circumstances
2022-10-29 02:37:54 -03:00
c831f67d1a
feat(timer): implemeant all timer i/o reads
2022-10-29 01:37:28 -03:00
268961262d
feat(dma): implement all dma i/o reads
2022-10-29 01:30:12 -03:00
3e62feacba
feat(ppu): implement all ppu i/o reads
2022-10-29 01:29:27 -03:00
371cf4cc12
style(i/o, ppu): refactor ppu i/o
2022-10-28 23:45:54 -03:00
10aec67ee0
emu: implement thread sleep in granular steps
2022-10-28 21:58:55 -03:00
4eb715a138
doc(emu): properly document + simply constants
2022-10-28 21:57:30 -03:00
14b24787ab
style: remove unnecessary imports
2022-10-28 21:56:55 -03:00
eb7ffa29f4
fix(apu): pause device on mute instead of writing silence
2022-10-27 09:11:08 -03:00
4b8ed3cebb
fix(io): resolve embarrasingly simple regression
...
introduced in 21eddac31ec6839ea51f23b3101282c423a21142
2022-10-23 04:39:31 -03:00
928ce674d9
fix(cpu): fix obscure LDRSH behaviour
2022-10-22 22:12:41 -03:00
945dbec013
fix(open-bus): don't rotate result
...
Rotating misaligned reads is the responsibility of the CPU
2022-10-22 21:32:36 -03:00
a2868dfe9e
feat(dma): Implement DMA Latch
2022-10-22 20:52:02 -03:00
22979d9450
fix(bios): fix regression
...
was reading addr_latch + 8, which is a remnant from when I was faking
the pipeline
2022-10-22 15:33:36 -03:00
e60b556f72
chore(ppu): remove BGR555 -> RGBA888 LUT
...
LUT probably couldn't fit in CPU cache anyways.
TODO: Consider whether LUTs for separate channels (size 32 * 3 * 3
instead of std.math.maxInt(u15))
2022-10-17 20:31:42 -03:00
26dba16789
chore(gpio): add missing errdefer
2022-10-17 20:01:50 -03:00
7b146ad7ca
fix(bios): set addr_latch even if bios is skipped
2022-10-13 00:35:22 -03:00
822eed1f3a
fix(bus): make open bus impl aware of CPU pipeline
2022-10-13 00:35:22 -03:00
b37a14900c
style(bus): cpu ptr doesn't need to be optional
2022-10-13 00:35:22 -03:00
f5bd20bc2a
style: code cleanup
2022-10-13 00:35:22 -03:00
d3514b14f3
fix: resolve timing regressions
...
make sure to use fetch timings when fetching instructions
2022-10-13 00:35:20 -03:00
06c60dad74
fix: rename Pipline to Pipeline
2022-10-13 00:34:18 -03:00
870e991862
feat: working pipeline implementation
2022-10-13 00:34:18 -03:00
5bb5bdf389
chore: refactor ARM/THUMB data processing instructions
2022-10-13 00:34:18 -03:00
a3996cbc58
fix: don't flush pipeline when reloading CPSR in ARM Data Processing
2022-10-13 00:34:18 -03:00
a948c6f900
chore: don't write to CPSR + swap with SPSR at the same time
2022-10-13 00:34:18 -03:00
e4451738b5
fix: advance r15, even when the pipeline is reloaded from the scheduler
...
The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code
Now, the PC is always incremented when the pipeline is reloaded
2022-10-13 00:33:13 -03:00
48b81c8e7a
chore: dump pipeline state on cpu panic
2022-10-13 00:33:13 -03:00
