chore(cpu): refactor ARM functions to make room for THUMB

src/cpu/arm/barrel_shifter.zig

@@ -0,0 +1,98 @@
+const std = @import("std");
+
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const CPSR = @import("../../cpu.zig").PSR;
+
+pub fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
+    var shift_amt: u8 = undefined;
+    if (opcode >> 4 & 1 == 1) {
+        shift_amt = @truncate(u8, cpu.r[opcode >> 8 & 0xF]);
+    } else {
+        shift_amt = @truncate(u8, opcode >> 7 & 0x1F);
+    }
+
+    const rm = cpu.r[opcode & 0xF];
+    var value: u32 = undefined;
+    if (rm == 0xF) {
+        value = cpu.fakePC() + 4; // 12 ahead
+    } else {
+        value = cpu.r[opcode & 0xF];
+    }
+
+    if (S) {
+        return switch (@truncate(u2, opcode >> 5)) {
+            0b00 => logical_left(&cpu.cpsr, value, shift_amt),
+            0b01 => logical_right(&cpu.cpsr, value, shift_amt),
+            0b10 => arithmetic_right(&cpu.cpsr, value, shift_amt),
+            0b11 => rotate_right(&cpu.cpsr, value, shift_amt),
+        };
+    } else {
+        var dummy = CPSR{ .raw = 0x0000_0000 };
+        return switch (@truncate(u2, opcode >> 5)) {
+            0b00 => logical_left(&dummy, value, shift_amt),
+            0b01 => logical_right(&dummy, value, shift_amt),
+            0b10 => arithmetic_right(&dummy, value, shift_amt),
+            0b11 => rotate_right(&dummy, value, shift_amt),
+        };
+    }
+}
+
+pub fn logical_left(cpsr: *CPSR, rm: u32, shift_byte: u8) u32 {
+    const shift_amt = @truncate(u5, shift_byte);
+    const bit_count: u8 = @typeInfo(u32).Int.bits;
+
+    var result: u32 = 0x0000_0000;
+
+    if (shift_byte < bit_count) {
+        // We can perform a well-defined shift here
+
+        // FIXME: We assume cpu.r[rs] == 0 and imm_shift == 0 are equivalent
+        if (shift_amt != 0) {
+            const carry_bit = @truncate(u5, bit_count - shift_amt);
+            cpsr.c.write(rm >> carry_bit & 1 == 1);
+        }
+
+        result = rm << shift_amt;
+    } else if (shift_byte == bit_count) {
+        // Shifted all bits out, carry bit is bit 0 of rm
+        cpsr.c.write(rm & 1 == 1);
+    } else {
+        // Shifted all bits out, carry bit has also been shifted out
+        cpsr.c.write(false);
+    }
+
+    return result;
+}
+
+pub fn logical_right(cpsr: *CPSR, rm: u32, shift_byte: u8) u32 {
+    const shift_amt = @truncate(u5, shift_byte);
+    const bit_count: u8 = @typeInfo(u32).Int.bits;
+
+    var result: u32 = 0x0000_0000;
+
+    if (shift_byte == 0 or shift_byte == bit_count) {
+        // Actualy LSR #32
+        cpsr.c.write(rm >> 31 & 1 == 1);
+    } else if (shift_byte < bit_count) {
+        // We can perform a well-defined shift
+        const carry_bit = shift_amt - 1;
+        cpsr.c.write(rm >> carry_bit & 1 == 1);
+
+        result = rm >> shift_amt;
+    } else {
+        // All bits have been shifted out, including carry bit
+        cpsr.c.write(false);
+    }
+
+    return result;
+}
+
+pub fn arithmetic_right(_: *CPSR, _: u32, _: u8) u32 {
+    // @bitCast(u32, @bitCast(i32, r_val) >> @truncate(u5, amount))
+    std.debug.panic("[BarrelShifter] implement arithmetic shift right", .{});
+}
+
+pub fn rotate_right(_: *CPSR, _: u32, _: u8) u32 {
+    // std.math.rotr(u32, r_val, amount)
+    std.debug.panic("[BarrelShifter] implement rotate right", .{});
+}

src/cpu/arm/block_data_transfer.zig

@@ -0,0 +1,63 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").InstrFn;
+
+pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const base = cpu.r[rn];
+
+            if (S and opcode >> 15 & 1 == 0) std.debug.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
+
+            var address: u32 = undefined;
+            if (U) {
+                // Increment
+                address = if (P) base + 4 else base;
+
+                var i: u5 = 0;
+                while (i < 0x10) : (i += 1) {
+                    if (opcode >> i & 1 == 1) {
+                        transfer(cpu, bus, i, address);
+                        address += 4;
+                    }
+                }
+            } else {
+                // Decrement
+                address = if (P) base - 4 else base;
+
+                var i: u5 = 0x10;
+                while (i > 0) : (i -= 1) {
+                    const j = i - 1;
+
+                    if (opcode >> j & 1 == 1) {
+                        transfer(cpu, bus, j, address);
+                        address -= 4;
+                    }
+                }
+            }
+
+            if (W and P or !P) cpu.r[rn] = if (U) address else address + 4;
+        }
+
+        fn transfer(cpu: *Arm7tdmi, bus: *Bus, i: u5, address: u32) void {
+            if (L) {
+                cpu.r[i] = bus.read32(address);
+                if (S and i == 0xF) std.debug.panic("[CPU] TODO: SPSR_<mode> is transferred to CPSR", .{});
+            } else {
+                if (i == 0xF) {
+                    if (!S) {
+                        // TODO: Assure that this is Address of STM instruction + 12
+                        bus.write32(address, cpu.r[i] + (12 - 4));
+                    } else {
+                        std.debug.panic("[CPU] TODO: STM with S set and R15 in transfer list", .{});
+                    }
+                } else {
+                    bus.write32(address, cpu.r[i]);
+                }
+            }
+        }
+    }.inner;
+}

src/cpu/arm/branch.zig

@@ -0,0 +1,27 @@
+const std = @import("std");
+const util = @import("../../util.zig");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").InstrFn;
+
+pub fn branch(comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            if (L) {
+                // TODO: Debugging beeg.gba w/ MGBA seems to suggest that I don't do anything here
+                cpu.r[14] = cpu.r[15];
+            }
+
+            cpu.r[15] = cpu.fakePC() +% util.u32SignExtend(24, opcode << 2);
+        }
+    }.inner;
+}
+
+pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+    const rn = opcode & 0xF;
+    cpu.cpsr.t.write(cpu.r[rn] & 1 == 1);
+
+    // TODO: Is this how I should do it?
+    cpu.r[15] = cpu.r[rn] & 0xFFFF_FFFE;
+}

src/cpu/arm/data_processing.zig

@@ -0,0 +1,96 @@
+const std = @import("std");
+
+const BarrelShifter = @import("barrel_shifter.zig");
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").InstrFn;
+
+pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            const rd = opcode >> 12 & 0xF;
+            const rn = opcode >> 16 & 0xF;
+
+            if (S and rd == 0xF) std.debug.panic("[CPU] Data Processing Instruction w/ S set and Rd == 15", .{});
+
+            var op1: u32 = undefined;
+            if (rn == 0xF) {
+                op1 = cpu.fakePC();
+            } else {
+                op1 = cpu.r[rn];
+            }
+
+            var op2: u32 = undefined;
+            if (I) {
+                op2 = std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1);
+            } else {
+                op2 = BarrelShifter.exec(S, cpu, opcode);
+            }
+
+            switch (instrKind) {
+                0x4 => {
+                    // ADD
+                    var result: u32 = undefined;
+                    const didOverflow = @addWithOverflow(u32, op1, op2, &result);
+                    cpu.r[rd] = result;
+
+                    if (S and rd != 0xF) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+                        cpu.cpsr.c.write(didOverflow);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
+                0x8 => {
+                    // TST
+                    const result = op1 & op2;
+
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // Barrel Shifter should always calc CPSR C in TST
+                    if (!S) _ = BarrelShifter.exec(true, cpu, opcode);
+                },
+                0x9 => {
+                    // TEQ
+                    const result = op1 ^ op2;
+
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // Barrel Shifter should always calc CPSR C in TEQ
+                    if (!S) _ = BarrelShifter.exec(true, cpu, opcode);
+                },
+                0xD => {
+                    // MOV
+                    cpu.r[rd] = op2;
+
+                    if (S and rd != 0xF) {
+                        cpu.cpsr.n.write(op2 >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(op2 == 0);
+                        // C set by Barr0x15el Shifter, V is unnafected
+                    }
+                },
+                0xA => {
+                    // CMP
+                    const result = op1 -% op2;
+
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    cpu.cpsr.c.write(op2 <= op1);
+                    cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                },
+                0xC => {
+                    // ORR
+                    const result = op1 | op2;
+                    cpu.r[rd] = result;
+
+                    if (S and rd != 0xF) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+                        // C set by Barr0x15el Shifter, V is unnafected
+                    }
+                },
+                else => std.debug.panic("[CPU] TODO: implement data processing type {}", .{instrKind}),
+            }
+        }
+    }.inner;
+}

src/cpu/arm/half_signed_data_transfer.zig

@@ -0,0 +1,69 @@
+const std = @import("std");
+const util = @import("../../util.zig");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").InstrFn;
+
+pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+            const rm = opcode & 0xF;
+            const imm_offset_high = opcode >> 8 & 0xF;
+
+            var base: u32 = undefined;
+            if (rn == 0xF) {
+                base = cpu.fakePC();
+                if (!L) base += 4;
+            } else {
+                base = cpu.r[rn];
+            }
+
+            var offset: u32 = undefined;
+            if (I) {
+                offset = imm_offset_high << 4 | rm;
+            } else {
+                offset = cpu.r[rm];
+            }
+
+            const modified_base = if (U) base + offset else base - offset;
+            var address = if (P) modified_base else base;
+
+            if (L) {
+                switch (@truncate(u2, opcode >> 5)) {
+                    0b00 => {
+                        // SWP
+                        std.debug.panic("[CPU] TODO: Implement SWP", .{});
+                    },
+                    0b01 => {
+                        // LDRH
+                        const value = bus.read16(address & 0xFFFF_FFFE);
+                        cpu.r[rd] = std.math.rotr(u32, @as(u32, value), 8 * (address & 1));
+                    },
+                    0b10 => {
+                        // LDRSB
+                        cpu.r[rd] = util.u32SignExtend(8, @as(u32, bus.read8(address)));
+                        std.debug.panic("TODO: Affect the CPSR", .{});
+                    },
+                    0b11 => {
+                        // LDRSH
+                        cpu.r[rd] = util.u32SignExtend(16, @as(u32, bus.read16(address)));
+                        std.debug.panic("TODO: Affect the CPSR", .{});
+                    },
+                }
+            } else {
+                if (opcode >> 5 & 0x01 == 0x01) {
+                    // STRH
+                    bus.write16(address, @truncate(u16, cpu.r[rd]));
+                } else {
+                    std.debug.panic("[CPU] TODO: Figure out if this is also SWP", .{});
+                }
+            }
+
+            address = modified_base;
+            if (W and P or !P) cpu.r[rn] = address;
+        }
+    }.inner;
+}

src/cpu/arm/psr_transfer.zig

@@ -0,0 +1,51 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").InstrFn;
+
+pub fn psrTransfer(comptime I: bool, comptime isSpsr: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+            switch (@truncate(u3, opcode >> 19)) {
+                0b001 => {
+                    // MRS
+                    const rn = opcode >> 12 & 0xF;
+
+                    if (isSpsr) {
+                        std.debug.panic("[CPU] TODO: MRS on SPSR_<current_mode> is unimplemented", .{});
+                    } else {
+                        cpu.r[rn] = cpu.cpsr.raw;
+                    }
+                },
+                0b101 => {
+                    // MSR
+                    const rm = opcode & 0xF;
+
+                    switch (@truncate(u3, opcode >> 16)) {
+                        0b000 => {
+                            const right = if (I) std.math.rotr(u32, opcode & 0xFF, opcode >> 7 & 0xF) else cpu.r[rm];
+
+                            if (isSpsr) {
+                                std.debug.panic("[CPU] TODO: MSR (flags only) on SPSR_<current_mode> is unimplemented", .{});
+                            } else {
+                                const mask: u32 = 0xF000_0000;
+                                cpu.cpsr.raw = (cpu.cpsr.raw & ~mask) | (right & mask);
+                            }
+                        },
+                        0b001 => {
+                            if (isSpsr) {
+                                std.debug.panic("[CPU] TODO: MSR on SPSR_<current_mode> is unimplemented", .{});
+                            } else {
+                                cpu.cpsr = .{ .raw = cpu.r[rm] };
+                            }
+                        },
+
+                        else => unreachable,
+                    }
+                },
+                else => unreachable,
+            }
+        }
+    }.inner;
+}

src/cpu/arm/single_data_transfer.zig

@@ -0,0 +1,70 @@
+const std = @import("std");
+const util = @import("../../util.zig");
+
+const BarrelShifter = @import("barrel_shifter.zig");
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const CPSR = @import("../../cpu.zig").PSR;
+const InstrFn = @import("../../cpu.zig").InstrFn;
+
+pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
+            const rn = opcode >> 16 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+
+            var base: u32 = undefined;
+            if (rn == 0xF) {
+                base = cpu.fakePC();
+                if (!L) base += 4; // Offset of 12
+            } else {
+                base = cpu.r[rn];
+            }
+
+            const offset = if (I) registerOffset(cpu, opcode) else opcode & 0xFFF;
+
+            const modified_base = if (U) base + offset else base - offset;
+            var address = if (P) modified_base else base;
+
+            if (L) {
+                if (B) {
+                    // LDRB
+                    cpu.r[rd] = bus.read8(address);
+                } else {
+                    // LDR
+                    const value = bus.read32(address & 0xFFFF_FFFC);
+                    cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 0x3));
+                }
+            } else {
+                if (B) {
+                    // STRB
+                    bus.write8(address, @truncate(u8, cpu.r[rd]));
+                } else {
+                    // STR
+                    const force_aligned = address & 0xFFFF_FFFC;
+                    bus.write32(force_aligned, cpu.r[rd]);
+                }
+            }
+
+            address = modified_base;
+            if (W and P or !P) cpu.r[rn] = address;
+
+            // TODO: W-bit forces non-privledged mode for the transfer
+        }
+    }.inner;
+}
+
+fn registerOffset(cpu: *Arm7tdmi, opcode: u32) u32 {
+    const shift_byte = @truncate(u8, opcode >> 7 & 0x1F);
+
+    const rm = cpu.r[opcode & 0xF];
+
+    var dummy = CPSR{ .raw = 0x0000_0000 };
+
+    return switch (@truncate(u2, opcode >> 5)) {
+        0b00 => BarrelShifter.logical_left(&dummy, rm, shift_byte),
+        0b01 => BarrelShifter.logical_right(&dummy, rm, shift_byte),
+        0b10 => BarrelShifter.arithmetic_right(&dummy, rm, shift_byte),
+        0b11 => BarrelShifter.rotate_right(&dummy, rm, shift_byte),
+    };
+}