2022-10-21 08:11:49 +00:00
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const std = @import("std");
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2022-10-21 08:12:05 +00:00
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const CPSR = @import("../cpu.zig").PSR;
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2022-10-21 08:11:49 +00:00
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2022-10-21 08:12:28 +00:00
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const rotr = @import("../util.zig").rotr;
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2022-10-21 08:11:59 +00:00
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pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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var result: u32 = undefined;
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if (opcode >> 4 & 1 == 1) {
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result = registerShift(S, cpu, opcode);
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2022-10-21 08:11:49 +00:00
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} else {
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result = immShift(S, cpu, opcode);
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2022-10-21 08:11:49 +00:00
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}
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2022-10-21 08:11:59 +00:00
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return result;
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}
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fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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const rs_idx = opcode >> 8 & 0xF;
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const rs = @truncate(u8, cpu.r[rs_idx]);
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const rm_idx = opcode & 0xF;
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2022-10-21 08:12:01 +00:00
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const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
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2022-10-21 08:11:58 +00:00
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return switch (@truncate(u2, opcode >> 5)) {
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2022-10-21 08:11:59 +00:00
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0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
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0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
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0b10 => arithmeticRight(S, &cpu.cpsr, rm, rs),
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0b11 => rotateRight(S, &cpu.cpsr, rm, rs),
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2022-10-21 08:11:58 +00:00
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};
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2022-10-21 08:11:49 +00:00
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}
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2022-10-21 08:12:10 +00:00
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pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
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const amount = @truncate(u8, opcode >> 7 & 0x1F);
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const rm_idx = opcode & 0xF;
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2022-10-21 08:12:00 +00:00
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const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
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2022-10-21 08:11:59 +00:00
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var result: u32 = undefined;
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if (amount == 0) {
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switch (@truncate(u2, opcode >> 5)) {
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0b00 => {
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// LSL #0
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result = rm;
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},
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0b01 => {
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// LSR #0 aka LSR #32
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if (S) cpu.cpsr.c.write(rm >> 31 & 1 == 1);
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result = 0x0000_0000;
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},
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0b10 => {
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// ASR #0 aka ASR #32
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result = @bitCast(u32, @bitCast(i32, rm) >> 31);
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if (S) cpu.cpsr.c.write(result >> 31 & 1 == 1);
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},
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0b11 => {
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// ROR #0 aka RRX
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const carry: u32 = @boolToInt(cpu.cpsr.c.read());
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if (S) cpu.cpsr.c.write(rm & 1 == 1);
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result = (carry << 31) | (rm >> 1);
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},
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}
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} else {
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switch (@truncate(u2, opcode >> 5)) {
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0b00 => result = logicalLeft(S, &cpu.cpsr, rm, amount),
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0b01 => result = logicalRight(S, &cpu.cpsr, rm, amount),
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0b10 => result = arithmeticRight(S, &cpu.cpsr, rm, amount),
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0b11 => result = rotateRight(S, &cpu.cpsr, rm, amount),
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}
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}
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return result;
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}
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pub fn logicalLeft(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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const amount = @truncate(u5, total_amount);
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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var result: u32 = 0x0000_0000;
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if (total_amount < bit_count) {
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// We can perform a well-defined shift here
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result = rm << amount;
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if (S and total_amount != 0) {
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const carry_bit = @truncate(u5, bit_count - amount);
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cpsr.c.write(rm >> carry_bit & 1 == 1);
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}
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} else {
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2022-10-21 08:11:59 +00:00
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if (S) {
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if (total_amount == bit_count) {
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// Shifted all bits out, carry bit is bit 0 of rm
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cpsr.c.write(rm & 1 == 1);
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} else {
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cpsr.c.write(false);
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}
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}
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2022-10-21 08:11:49 +00:00
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}
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return result;
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}
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2022-10-21 08:11:59 +00:00
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pub fn logicalRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 {
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const amount = @truncate(u5, total_amount);
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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var result: u32 = 0x0000_0000;
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if (total_amount < bit_count) {
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2022-10-21 08:11:49 +00:00
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// We can perform a well-defined shift
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2022-10-21 08:11:59 +00:00
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result = rm >> amount;
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if (S and total_amount != 0) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
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2022-10-21 08:11:49 +00:00
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} else {
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if (S) {
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if (total_amount == bit_count) {
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// LSR #32
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cpsr.c.write(rm >> 31 & 1 == 1);
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} else {
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// All bits have been shifted out, including carry bit
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cpsr.c.write(false);
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}
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}
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2022-10-21 08:11:49 +00:00
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}
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return result;
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}
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2022-10-21 08:11:59 +00:00
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pub fn arithmeticRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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const amount = @truncate(u5, total_amount);
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const bit_count: u8 = @typeInfo(u32).Int.bits;
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var result: u32 = 0x0000_0000;
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if (total_amount < bit_count) {
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result = @bitCast(u32, @bitCast(i32, rm) >> amount);
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2022-10-21 08:11:59 +00:00
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if (S and total_amount != 0) cpsr.c.write(rm >> (amount - 1) & 1 == 1);
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2022-10-21 08:11:59 +00:00
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} else {
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2022-10-21 08:12:10 +00:00
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// ASR #32 and ASR #>32 have the same result
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result = @bitCast(u32, @bitCast(i32, rm) >> 31);
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if (S) cpsr.c.write(result >> 31 & 1 == 1);
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2022-10-21 08:11:59 +00:00
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}
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2022-10-21 08:11:59 +00:00
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return result;
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2022-10-21 08:11:49 +00:00
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}
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2022-10-21 08:11:59 +00:00
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pub fn rotateRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 {
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const result = rotr(u32, rm, total_amount);
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2022-10-21 08:11:58 +00:00
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2022-10-21 08:11:59 +00:00
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if (S and total_amount != 0) {
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2022-10-21 08:11:58 +00:00
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cpsr.c.write(result >> 31 & 1 == 1);
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}
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return result;
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2022-10-21 08:11:49 +00:00
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}
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