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8d2a3f1b67
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feat(v5te): let cp15 affect more tcm behaviours
cp15 can now enable/disable ITCM/DTCM. cp15 can also now enable/disable load mode.
TODO: load mode doesn't effect SWP/SWPB for some reason?
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2023-09-29 23:34:46 -05:00 |
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1bd96304ba
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fix: off-by-one when handling TCM addresses
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2023-09-29 02:35:21 -05:00 |
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481271ba2a
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fix(v4t/v5te): resolve critical error in ldm/stm obscure behaviour
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2023-09-26 20:46:30 -05:00 |
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2c5d474c56
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fix(v5te): fix off by one in DTCM handler
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2023-09-20 00:29:49 -05:00 |
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4d3814db36
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fix(v5te): set T on select load instrs when rd == 15
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2023-09-20 00:29:47 -05:00 |
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502647806c
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feat(v5te): stub THUMB BKPT
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2023-09-20 00:29:44 -05:00 |
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3c5d4acc5f
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feat(v5te): implement THUMB BLX(1), BLX(2), and ARM BLX
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2023-09-20 00:29:42 -05:00 |
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37b3fe3d10
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fix(v5te): properly implement SMLAL<x><y>
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2023-09-20 00:29:38 -05:00 |
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106820b444
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fix(v5te): properly implement qadd/qsub qdadd/qdsub
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2023-09-19 21:24:31 -05:00 |
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a3eefa6432
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chore: panic TODO on Unconditional address space
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2023-09-15 14:50:29 -05:00 |
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30cf951d2a
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feat: integrate cp15 and TCM code
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2023-09-15 14:20:24 -05:00 |
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71541c312c
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chore: semi-pass more rockwrestler tests
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2023-09-15 14:20:21 -05:00 |
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514e4d6014
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feat: implement Coprocessor Interface
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2023-09-15 14:20:17 -05:00 |
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5d70e4bd1d
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chore(v4t,v5te): don't give SWP/SWPB its own separate handler
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2023-09-09 03:39:21 -05:00 |
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253cbbcdff
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feat(v5te): impl BLX, QDADD/QDSUB, SMLAL<x><y>, SMLAW<y>, SMULW<y>, SMUL<x><y>
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2023-09-09 03:04:44 -05:00 |
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c94912887e
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feat(v5te): implement SMLA<x><y>
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2023-09-07 20:00:19 -05:00 |
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819eace2a7
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feat: implement QADD/QSUB
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2023-09-07 03:39:51 -05:00 |
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177f9b55a9
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fix(v5te): rework MSR/MRS handling to account for v5TE extension space
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2023-09-07 01:26:51 -05:00 |
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6dde25bd0f
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fix(arm): group multiply instructions together
- implement clz in ARMv5TE
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2023-09-07 01:26:51 -05:00 |
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44b59512c0
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feat(v5te): implement clz
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2023-09-07 01:26:51 -05:00 |
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ea3db88bec
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feat(v5te): stub LDRD / STRD
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2023-09-07 01:26:51 -05:00 |
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67bae5dcb4
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fix: ensure order of operations to prevent regression in arm.gba
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2023-09-06 20:04:00 -05:00 |
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e6863e7a9b
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fix(armv5te): implement obscure behaviour on invalid LDM writeback
All I have to do is implement ARMv5TE specific instructions, and then
we're finished with ARMWRESTLER!
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2023-09-06 01:29:08 -05:00 |
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591352a65b
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fix: Arm32 should represent generic, not pointer to generic
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2023-09-05 21:38:22 -05:00 |
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ada2a08516
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feat(v5te): implement basic DTCM + ITCM
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2023-07-26 00:14:32 -05:00 |
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ba22b856ec
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chore: drop *Bus argument from the InstrFn LUT
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2023-07-25 22:00:17 -05:00 |
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f31c4bdb65
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feat: stub coprocessor instructions
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2023-07-25 22:00:17 -05:00 |
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96a3a45d9b
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feat: add v5te arm and thumb namespaces
also, drop the comptime parameter from arm and thumb namespaces
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2023-07-25 22:00:17 -05:00 |
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2af9c351bc
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feat: allow lib use as git-submodule
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2023-07-25 22:00:17 -05:00 |
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6c81608c59
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fix: remove redundant casts from zig fmt
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2023-07-11 00:39:14 -05:00 |
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a831ab22fe
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chore: update dependencies
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2023-07-10 22:16:24 -05:00 |
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f8c2479ed9
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chore: update to latest builtin syntax
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2023-07-10 22:00:59 -05:00 |
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90d5c19e01
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feat: implement debug i/o in Bus Interface
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2023-06-29 23:27:24 -05:00 |
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3c8a87c14d
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chore: expose arm namespace
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2023-06-25 18:54:57 -05:00 |
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fa54f194a1
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feat: expose module for zig build system
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2023-06-25 18:54:57 -05:00 |
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d2db52e495
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feat: implement ARM7TDMI (and stub ARM946E-S)
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2023-06-25 18:54:57 -05:00 |
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c8e78c42ec
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feat: initial commit
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2023-06-25 01:04:02 -05:00 |
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