243 lines
8.1 KiB
Zig
243 lines
8.1 KiB
Zig
const std = @import("std");
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const AudioDeviceId = @import("sdl2").SDL_AudioDeviceID;
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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const Bios = @import("bus/Bios.zig");
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const Ewram = @import("bus/Ewram.zig");
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const GamePak = @import("bus/GamePak.zig");
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const Io = @import("bus/io.zig").Io;
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const Iwram = @import("bus/Iwram.zig");
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const Ppu = @import("ppu.zig").Ppu;
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const Apu = @import("apu.zig").Apu;
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const DmaTuple = @import("bus/dma.zig").DmaTuple;
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const TimerTuple = @import("bus/timer.zig").TimerTuple;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const FilePaths = @import("../util.zig").FilePaths;
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const io = @import("bus/io.zig");
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const Allocator = std.mem.Allocator;
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const log = std.log.scoped(.Bus);
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const createDmaTuple = @import("bus/dma.zig").create;
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const createTimerTuple = @import("bus/timer.zig").create;
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const rotr = @import("../util.zig").rotr;
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const timings: [2][0x10]u8 = [_][0x10]u8{
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// BIOS, Unused, EWRAM, IWRAM, I/0, PALRAM, VRAM, OAM, ROM0, ROM0, ROM1, ROM1, ROM2, ROM2, SRAM, Unused
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[_]u8{ 1, 1, 3, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5, 5, 5 }, // 8-bit & 16-bit
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[_]u8{ 1, 1, 6, 1, 1, 2, 2, 1, 8, 8, 8, 8, 8, 8, 8, 8 }, // 32-bit
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};
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pub const fetch_timings: [2][0x10]u8 = [_][0x10]u8{
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// BIOS, Unused, EWRAM, IWRAM, I/0, PALRAM, VRAM, OAM, ROM0, ROM0, ROM1, ROM1, ROM2, ROM2, SRAM, Unused
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[_]u8{ 1, 1, 3, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 5, 5 }, // 8-bit & 16-bit
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[_]u8{ 1, 1, 6, 1, 1, 2, 2, 1, 4, 4, 4, 4, 4, 4, 8, 8 }, // 32-bit
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};
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const Self = @This();
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pak: GamePak,
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bios: Bios,
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ppu: Ppu,
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apu: Apu,
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dma: DmaTuple,
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tim: TimerTuple,
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iwram: Iwram,
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ewram: Ewram,
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io: Io,
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cpu: ?*Arm7tdmi,
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sched: *Scheduler,
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pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
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self.* = .{
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.pak = try GamePak.init(allocator, cpu, paths.rom, paths.save),
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.bios = try Bios.init(allocator, paths.bios),
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.ppu = try Ppu.init(allocator, sched),
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.apu = Apu.init(sched),
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.iwram = try Iwram.init(allocator),
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.ewram = try Ewram.init(allocator),
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.dma = createDmaTuple(),
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.tim = createTimerTuple(sched),
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.io = Io.init(),
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.cpu = cpu,
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.sched = sched,
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};
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}
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pub fn deinit(self: *Self) void {
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self.iwram.deinit();
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self.ewram.deinit();
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self.pak.deinit();
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self.bios.deinit();
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self.ppu.deinit();
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self.* = undefined;
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}
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pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
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const page = @truncate(u8, address >> 24);
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const aligned_addr = forceAlign(T, address);
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return switch (page) {
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// General Internal Memory
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0x00 => blk: {
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if (address < Bios.size)
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break :blk self.bios.dbgRead(T, self.cpu.?.r[15], aligned_addr);
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break :blk self.readOpenBus(T, address);
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},
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0x02 => self.ewram.read(T, aligned_addr),
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0x03 => self.iwram.read(T, aligned_addr),
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0x04 => self.readIo(T, address),
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// Internal Display Memory
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0x05 => self.ppu.palette.read(T, aligned_addr),
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0x06 => self.ppu.vram.read(T, aligned_addr),
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0x07 => self.ppu.oam.read(T, aligned_addr),
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// External Memory (Game Pak)
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0x08...0x0D => self.pak.dbgRead(T, aligned_addr),
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0x0E...0x0F => blk: {
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const value = self.pak.backup.read(address);
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const multiplier = switch (T) {
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u32 => 0x01010101,
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u16 => 0x0101,
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u8 => 1,
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else => @compileError("Backup: Unsupported read width"),
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};
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break :blk @as(T, value) * multiplier;
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},
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else => self.readOpenBus(T, address),
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};
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}
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fn readIo(self: *const Self, comptime T: type, unaligned_address: u32) T {
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const maybe_value = io.read(self, T, forceAlign(T, unaligned_address));
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return if (maybe_value) |value| value else self.readOpenBus(T, unaligned_address);
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}
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fn readOpenBus(self: *const Self, comptime T: type, address: u32) T {
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const r15 = self.cpu.?.r[15];
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const word = blk: {
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// If u32 Open Bus, read recently fetched opcode (PC + 8)
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if (!self.cpu.?.cpsr.t.read()) break :blk self.dbgRead(u32, r15 + 4);
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const page = @truncate(u8, r15 >> 24);
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switch (page) {
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// EWRAM, PALRAM, VRAM, and Game ROM (16-bit)
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0x02, 0x05, 0x06, 0x08...0x0D => {
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// (PC + 4)
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const halfword = self.dbgRead(u16, r15 + 2);
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break :blk @as(u32, halfword) << 16 | halfword;
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},
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// BIOS or OAM (32-bit)
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0x00, 0x07 => {
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// Aligned: (PC + 6) | (PC + 4)
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// Unaligned: (PC + 4) | (PC + 2)
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const offset: u32 = if (address & 3 == 0b00) 2 else 0;
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break :blk @as(u32, self.dbgRead(u16, r15 + 2 + offset)) << 16 | self.dbgRead(u16, r15 + offset);
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},
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// IWRAM (16-bit but special)
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0x03 => {
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// Aligned: (PC + 2) | (PC + 4)
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// Unaligned: (PC + 4) | (PC + 2)
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const offset: u32 = if (address & 3 == 0b00) 2 else 0;
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break :blk @as(u32, self.dbgRead(u16, r15 + 2 - offset)) << 16 | self.dbgRead(u16, r15 + offset);
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},
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else => unreachable,
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}
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};
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return @truncate(T, rotr(u32, word, 8 * (address & 3)));
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}
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pub fn read(self: *Self, comptime T: type, address: u32) T {
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const page = @truncate(u8, address >> 24);
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const aligned_addr = forceAlign(T, address);
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self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
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return switch (page) {
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// General Internal Memory
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0x00 => blk: {
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if (address < Bios.size)
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break :blk self.bios.read(T, self.cpu.?.r[15], aligned_addr);
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break :blk self.readOpenBus(T, address);
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},
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0x02 => self.ewram.read(T, aligned_addr),
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0x03 => self.iwram.read(T, aligned_addr),
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0x04 => self.readIo(T, address),
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// Internal Display Memory
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0x05 => self.ppu.palette.read(T, aligned_addr),
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0x06 => self.ppu.vram.read(T, aligned_addr),
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0x07 => self.ppu.oam.read(T, aligned_addr),
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// External Memory (Game Pak)
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0x08...0x0D => self.pak.read(T, aligned_addr),
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0x0E...0x0F => blk: {
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const value = self.pak.backup.read(address);
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const multiplier = switch (T) {
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u32 => 0x01010101,
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u16 => 0x0101,
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u8 => 1,
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else => @compileError("Backup: Unsupported read width"),
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};
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break :blk @as(T, value) * multiplier;
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},
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else => self.readOpenBus(T, address),
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};
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}
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pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
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const page = @truncate(u8, address >> 24);
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const aligned_addr = forceAlign(T, address);
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self.sched.tick += timings[@boolToInt(T == u32)][@truncate(u4, page)];
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switch (page) {
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// General Internal Memory
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0x00 => self.bios.write(T, aligned_addr, value),
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0x02 => self.ewram.write(T, aligned_addr, value),
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0x03 => self.iwram.write(T, aligned_addr, value),
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0x04 => io.write(self, T, aligned_addr, value),
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// Internal Display Memory
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0x05 => self.ppu.palette.write(T, aligned_addr, value),
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0x06 => self.ppu.vram.write(T, self.ppu.dispcnt, aligned_addr, value),
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0x07 => self.ppu.oam.write(T, aligned_addr, value),
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// External Memory (Game Pak)
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0x08...0x0D => self.pak.write(T, self.dma[3].word_count, aligned_addr, value),
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0x0E...0x0F => {
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const rotate_by = switch (T) {
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u32 => address & 3,
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u16 => address & 1,
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u8 => 0,
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else => @compileError("Backup: Unsupported write width"),
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};
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self.pak.backup.write(address, @truncate(u8, rotr(T, value, 8 * rotate_by)));
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},
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else => {},
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}
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}
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fn forceAlign(comptime T: type, address: u32) u32 {
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return switch (T) {
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u32 => address & 0xFFFF_FFFC,
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u16 => address & 0xFFFF_FFFE,
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u8 => address,
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else => @compileError("Bus: Invalid read/write type"),
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};
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}
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