63 lines
2.2 KiB
Zig
63 lines
2.2 KiB
Zig
const std = @import("std");
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const util = @import("../util.zig");
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const Bus = @import("../Bus.zig");
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../cpu.zig").InstrFn;
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pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
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const rn = opcode >> 16 & 0xF;
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const rd = opcode >> 12 & 0xF;
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const rm = opcode & 0xF;
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const imm_offset_high = opcode >> 8 & 0xF;
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const base = cpu.r[rn];
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var offset: u32 = undefined;
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if (I) {
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offset = imm_offset_high << 4 | rm;
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} else {
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offset = cpu.r[rm];
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}
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const modified_base = if (U) base + offset else base - offset;
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var address = if (P) modified_base else base;
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if (L) {
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switch (@truncate(u2, opcode >> 5)) {
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0b00 => {
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// SWP
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std.debug.panic("[CPU] TODO: Implement SWP", .{});
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},
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0b01 => {
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// LDRH
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cpu.r[rd] = bus.read16(address);
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},
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0b10 => {
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// LDRSB
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cpu.r[rd] = util.u32SignExtend(8, @as(u32, bus.read8(address)));
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std.debug.panic("TODO: Affect the CPSR", .{});
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},
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0b11 => {
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// LDRSH
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cpu.r[rd] = util.u32SignExtend(16, @as(u32, bus.read16(address)));
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std.debug.panic("TODO: Affect the CPSR", .{});
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},
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}
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} else {
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if (opcode >> 5 & 0x01 == 0x01) {
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// STRH
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bus.write16(address, @truncate(u16, cpu.r[rd]));
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} else {
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std.debug.panic("[CPU] TODO: Figure out if this is also SWP", .{});
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}
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}
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address = modified_base;
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if (W and P or !P) cpu.r[rn] = address;
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}
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}.inner;
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}
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