src/cpu.zig

@@ -81,7 +81,7 @@ pub const Arm7tdmi = struct {
             .r = [_]u32{0x00} ** 16,
             .sched = sched,
             .bus = bus,
-            .cpsr = .{ .raw = 0x0000_001F },
+            .cpsr = .{ .raw = 0x0000_00DF },
             .spsr = .{ .raw = 0x0000_0000 },
             .banked_fiq = [_]u32{0x00} ** 10,
             .banked_r = [_]u32{0x00} ** 12,
@@ -220,6 +220,7 @@ pub const Arm7tdmi = struct {
             .User, .System => {
                 self.r[13] = self.banked_r[bankedIdx(next) * 2 + 0];
                 self.r[14] = self.banked_r[bankedIdx(next) * 2 + 1];
+                // FIXME: Should we clear out SPSR?
             },
             else => {
                 self.r[13] = self.banked_r[bankedIdx(next) * 2 + 0];
@@ -428,7 +429,7 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
         0x6 => cpsr.v.read(), // VS - Overflow
         0x7 => !cpsr.v.read(), // VC - No overflow
         0x8 => cpsr.c.read() and !cpsr.z.read(), // HI - unsigned higher
-        0x9 => !cpsr.c.read() or cpsr.z.read(), // LS - unsigned lower or same
+        0x9 => !cpsr.c.read() and cpsr.z.read(), // LS - unsigned lower or same
         0xA => cpsr.n.read() == cpsr.v.read(), // GE - Greater or equal
         0xB => cpsr.n.read() != cpsr.v.read(), // LT - Less than
         0xC => !cpsr.z.read() and (cpsr.n.read() == cpsr.v.read()), // GT - Greater than

src/cpu/arm/block_data_transfer.zig

@@ -1,3 +1,5 @@
+const std = @import("std");
+
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ArmInstrFn;
@@ -46,17 +48,17 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
             var address = start;
 
             if (rlist == 0) {
-                var und_addr = cpu.r[rn];
+                var pc_addr = cpu.r[rn];
                 if (U) {
-                    und_addr += if (P) 4 else 0;
+                    pc_addr += if (P) 4 else 0;
                 } else {
-                    und_addr -= 0x40 - if (!P) 4 else 0;
+                    pc_addr -= 0x40 - if (!P) 4 else 0;
                 }
 
                 if (L) {
-                    cpu.r[15] = bus.read32(und_addr & 0xFFFF_FFFC);
+                    cpu.r[15] = bus.read32(pc_addr);
                 } else {
-                    bus.write32(und_addr & 0xFFFF_FFFC, cpu.r[15] + 8);
+                    bus.write32(pc_addr, cpu.r[15] + 8);
                 }
 
                 cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
@@ -83,9 +85,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
             if (L) {
                 if (S and !r15_present) {
                     // Always Transfer User mode Registers
-                    cpu.setUserModeRegister(i, bus.read32(address & 0xFFFF_FFFC));
+                    cpu.setUserModeRegister(i, bus.read32(address));
                 } else {
-                    const value = bus.read32(address & 0xFFFF_FFFC);
+                    const value = bus.read32(address);
                     cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
                     if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
                 }
@@ -94,9 +96,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
                     // Always Transfer User mode Registers
                     // This happens regardless if r15 is in the list
                     const value = cpu.getUserModeRegister(i);
-                    bus.write32(address & 0xFFFF_FFFC, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
+                    bus.write32(address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
                 } else {
-                    bus.write32(address & 0xFFFF_FFFC, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
+                    bus.write32(address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
                 }
             }
         }

src/cpu/arm/branch.zig

@@ -1,16 +1,19 @@
 const std = @import("std");
+const util = @import("../../util.zig");
 
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ArmInstrFn;
 
-const u32SignExtend = @import("../../util.zig").u32SignExtend;
-
 pub fn branch(comptime L: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
-            if (L) cpu.r[14] = cpu.r[15];
+            if (L) {
-            cpu.r[15] = cpu.fakePC() +% u32SignExtend(24, opcode << 2);
+                // TODO: Debugging beeg.gba w/ MGBA seems to suggest that I don't do anything here
+                cpu.r[14] = cpu.r[15];
+            }
+
+            cpu.r[15] = cpu.fakePC() +% util.u32SignExtend(24, opcode << 2);
         }
     }.inner;
 }
@@ -18,5 +21,7 @@ pub fn branch(comptime L: bool) InstrFn {
 pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
     const rn = opcode & 0xF;
     cpu.cpsr.t.write(cpu.r[rn] & 1 == 1);
+
+    // TODO: Is this how I should do it?
     cpu.r[15] = cpu.r[rn] & 0xFFFF_FFFE;
 }

src/cpu/arm/data_processing.zig

@@ -1,10 +1,10 @@
+const std = @import("std");
+
+const shifter = @import("../barrel_shifter.zig");
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ArmInstrFn;
 
-const rotateRight = @import("../barrel_shifter.zig").rotateRight;
-const execute = @import("../barrel_shifter.zig").execute;
-
 pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
@@ -20,9 +20,9 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
             var op2: u32 = undefined;
             if (I) {
                 const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
-                op2 = rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
+                op2 = shifter.rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
             } else {
-                op2 = execute(S, cpu, opcode);
+                op2 = shifter.execute(S, cpu, opcode);
             }
 
             // Undo special condition from above
@@ -275,7 +275,7 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
     cpu.cpsr.n.write(result >> 31 & 1 == 1);
     cpu.cpsr.z.write(result == 0);
     // Barrel Shifter should always calc CPSR C in TST
-    if (!S) _ = execute(true, cpu, opcode);
+    if (!S) _ = shifter.execute(true, cpu, opcode);
 }
 
 fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {

src/cpu/arm/half_signed_data_transfer.zig

@@ -1,11 +1,10 @@
 const std = @import("std");
+const util = @import("../../util.zig");
 
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ArmInstrFn;
 
-const u32SignExtend = @import("../../util.zig").u32SignExtend;
-
 pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
@@ -42,14 +41,14 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
                     },
                     0b10 => {
                         // LDRSB
-                        result = u32SignExtend(8, bus.read8(address));
+                        result = util.u32SignExtend(8, bus.read8(address));
                     },
                     0b11 => {
                         // LDRSH
                         const value = if (address & 1 == 1) blk: {
-                            break :blk u32SignExtend(8, bus.read8(address));
+                            break :blk util.u32SignExtend(8, bus.read8(address));
                         } else blk: {
-                            break :blk u32SignExtend(16, bus.read16(address));
+                            break :blk util.u32SignExtend(16, bus.read16(address));
                         };
 
                         result = std.math.rotr(u32, value, 8 * (address & 1));

src/cpu/arm/multiply.zig

@@ -1,3 +1,5 @@
+const std = @import("std");
+
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ArmInstrFn;

src/cpu/arm/software_interrupt.zig

@@ -1,3 +1,5 @@
+const std = @import("std");
+
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ArmInstrFn;

src/cpu/thumb/alu.zig

@@ -1,6 +1,9 @@
+const std = @import("std");
+
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+const shifter = @import("../barrel_shifter.zig");
 
 const adc = @import("../arm/data_processing.zig").adc;
 const sbc = @import("../arm/data_processing.zig").sbc;
@@ -10,11 +13,6 @@ const cmn = @import("../arm/data_processing.zig").cmn;
 const setTestOpFlags = @import("../arm/data_processing.zig").setTestOpFlags;
 const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
 
-const logicalLeft = @import("../barrel_shifter.zig").logicalLeft;
-const logicalRight = @import("../barrel_shifter.zig").logicalRight;
-const arithmeticRight = @import("../barrel_shifter.zig").arithmeticRight;
-const rotateRight = @import("../barrel_shifter.zig").rotateRight;
-
 pub fn format4(comptime op: u4) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
@@ -37,19 +35,19 @@ pub fn format4(comptime op: u4) InstrFn {
                 },
                 0x2 => {
                     // LSL
-                    const result = logicalLeft(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
+                    const result = shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
                     cpu.r[rd] = result;
                     setLogicOpFlags(true, cpu, result);
                 },
                 0x3 => {
                     // LSR
-                    const result = logicalRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
+                    const result = shifter.logicalRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
                     cpu.r[rd] = result;
                     setLogicOpFlags(true, cpu, result);
                 },
                 0x4 => {
                     // ASR
-                    const result = arithmeticRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
+                    const result = shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
                     cpu.r[rd] = result;
                     setLogicOpFlags(true, cpu, result);
                 },
@@ -63,14 +61,14 @@ pub fn format4(comptime op: u4) InstrFn {
                 },
                 0x7 => {
                     // ROR
-                    const result = rotateRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
+                    const result = shifter.rotateRight(true, &cpu.cpsr, cpu.r[rd], @truncate(u8, cpu.r[rs]));
                     cpu.r[rd] = result;
                     setLogicOpFlags(true, cpu, result);
                 },
                 0x8 => {
                     // TST
                     const result = cpu.r[rd] & cpu.r[rs];
-                    setLogicOpFlags(true, cpu, result);
+                    setLogicOpFlags(true, cpu, result); // FIXME: Barrel Shifter?
                 },
                 0x9 => {
                     // NEG

src/cpu/thumb/block_data_transfer.zig

@@ -5,42 +5,44 @@ const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
 pub fn format14(comptime L: bool, comptime R: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
-            const count = countRlist(opcode);
+            var address: u32 = undefined;
-            const start = cpu.r[13] - if (!L) 4 * (@boolToInt(R) + count) else 0;
-
-            var end = cpu.r[13];
             if (L) {
-                end += 4 * (@boolToInt(R) + count);
+                // POP
-            } else {
+                address = cpu.r[13];
-                end -= 4;
-            }
-
-            var address = start;
 
                 var i: u4 = 0;
                 while (i < 8) : (i += 1) {
-                if (opcode >> i & 1 == 1) {
+                    if ((opcode >> i) & 1 == 1) {
-                    if (L) {
+                        cpu.r[i] = bus.read32(address);
-                        cpu.r[i] = bus.read32(address & 0xFFFF_FFFC);
-                    } else {
-                        bus.write32(address & 0xFFFF_FFFC, cpu.r[i]);
-                    }
-
                         address += 4;
                     }
                 }
 
                 if (R) {
-                if (L) {
+                    const value = bus.read32(address);
-                    const value = bus.read32(address & 0xFFFF_FFFC);
                     cpu.r[15] = value & 0xFFFF_FFFE;
-                } else {
-                    bus.write32(address & 0xFFFF_FFFC, cpu.r[14]);
-                }
                     address += 4;
                 }
+            } else {
+                address = cpu.r[13] - 4;
 
-            cpu.r[13] = if (L) end else cpu.r[13] - 4 * (@boolToInt(R) + count);
+                if (R) {
+                    bus.write32(address, cpu.r[14]);
+                    address -= 4;
+                }
+
+                var i: u4 = 8;
+                while (i > 0) : (i -= 1) {
+                    const j = i - 1;
+
+                    if ((opcode >> j) & 1 == 1) {
+                        bus.write32(address, cpu.r[j]);
+                        address -= 4;
+                    }
+                }
+            }
+
+            cpu.r[13] = address + if (!L) 4 else 0;
         }
     }.inner;
 }
@@ -52,7 +54,7 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
             const end_address = cpu.r[rb] + 4 * countRlist(opcode);
 
             if (opcode & 0xFF == 0) {
-                if (L) cpu.r[15] = bus.read32(address & 0xFFFF_FFFC) else bus.write32(address & 0xFFFF_FFFC, cpu.r[15] + 4);
+                if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 4);
                 cpu.r[rb] += 0x40;
                 return;
             }
@@ -63,9 +65,9 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
             while (i < 8) : (i += 1) {
                 if (opcode >> i & 1 == 1) {
                     if (L) {
-                        cpu.r[i] = bus.read32(address & 0xFFFF_FFFC);
+                        cpu.r[i] = bus.read32(address);
                     } else {
-                        bus.write32(address & 0xFFFF_FFFC, cpu.r[i]);
+                        bus.write32(address, cpu.r[i]);
                     }
 
                     if (!L and first_write) {

src/cpu/thumb/data_processing.zig

@@ -101,7 +101,7 @@ pub fn format12(comptime isSP: bool, comptime rd: u3) InstrFn {
             // ADD
             const left = if (isSP) cpu.r[13] else (cpu.r[15] + 2) & 0xFFFF_FFFD;
             const right = (opcode & 0xFF) << 2;
-            const result = left + right;
+            const result = left + right; // TODO: What about overflows?
             cpu.r[rd] = result;
         }
     }.inner;

src/cpu/thumb/data_transfer.zig

@@ -9,6 +9,8 @@ pub fn format6(comptime rd: u3) InstrFn {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
             // LDR
             const offset = (opcode & 0xFF) << 2;
+
+            // FIXME: Should this overflow?
             cpu.r[rd] = bus.read32((cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
         }
     }.inner;

src/cpu/thumb/processing_branch.zig

@@ -1,3 +1,5 @@
+const std = @import("std");
+
 const Bus = @import("../../Bus.zig");
 const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
 const InstrFn = @import("../../cpu.zig").ThumbInstrFn;