feat(cpu): implement branch and exchange

If I want to continue with armwrestler, I'll have to implement
THUMB instructions now

src/cpu.zig

@@ -13,6 +13,7 @@ const singleDataTransfer = @import("cpu/single_data_transfer.zig").singleDataTra
 const halfAndSignedDataTransfer = @import("cpu/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
 const blockDataTransfer = @import("cpu/block_data_transfer.zig").blockDataTransfer;
 const branch = @import("cpu/branch.zig").branch;
+const branchAndExchange = @import("cpu/branch.zig").branchAndExchange;
 
 pub const InstrFn = fn (*Arm7tdmi, *Bus, u32) void;
 const arm_lut: [0x1000]InstrFn = populate();
@@ -57,7 +58,7 @@ pub const Arm7tdmi = struct {
 
     fn fetch(self: *Self) u32 {
         const word = self.bus.read32(self.r[15]);
-        self.r[15] += 4;
+        self.r[15] += if (self.cpsr.t.read()) @as(u32, 2) else @as(u32, 4);
         return word;
     }
 
@@ -142,6 +143,10 @@ fn populate() [0x1000]InstrFn {
                 lut[i] = psrTransfer(I, isSpsr);
             }
 
+            if (i == 0x121) {
+                lut[i] = branchAndExchange;
+            }
+
             if (i >> 9 & 0x7 == 0b000 and i >> 3 & 1 == 1 and i & 1 == 1) {
                 const P = i >> 8 & 1 == 1;
                 const U = i >> 7 & 1 == 1;

src/cpu/barrel_shifter.zig

@@ -12,21 +12,27 @@ pub fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     }
 
     const rm = cpu.r[opcode & 0xF];
+    var value: u32 = undefined;
+    if (rm == 0xF) {
+        value = cpu.fakePC() + 4; // 12 ahead
+    } else {
+        value = cpu.r[opcode & 0xF];
+    }
 
     if (S) {
         return switch (@truncate(u2, opcode >> 5)) {
-            0b00 => logical_left(&cpu.cpsr, rm, shift_amt),
+            0b00 => logical_left(&cpu.cpsr, value, shift_amt),
-            0b01 => logical_right(&cpu.cpsr, rm, shift_amt),
+            0b01 => logical_right(&cpu.cpsr, value, shift_amt),
-            0b10 => arithmetic_right(&cpu.cpsr, rm, shift_amt),
+            0b10 => arithmetic_right(&cpu.cpsr, value, shift_amt),
-            0b11 => rotate_right(&cpu.cpsr, rm, shift_amt),
+            0b11 => rotate_right(&cpu.cpsr, value, shift_amt),
         };
     } else {
         var dummy = CPSR{ .raw = 0x0000_0000 };
         return switch (@truncate(u2, opcode >> 5)) {
-            0b00 => logical_left(&dummy, rm, shift_amt),
+            0b00 => logical_left(&dummy, value, shift_amt),
-            0b01 => logical_right(&dummy, rm, shift_amt),
+            0b01 => logical_right(&dummy, value, shift_amt),
-            0b10 => arithmetic_right(&dummy, rm, shift_amt),
+            0b10 => arithmetic_right(&dummy, value, shift_amt),
-            0b11 => rotate_right(&dummy, rm, shift_amt),
+            0b11 => rotate_right(&dummy, value, shift_amt),
         };
     }
 }

src/cpu/branch.zig

@@ -1,3 +1,4 @@
+const std = @import("std");
 const util = @import("../util.zig");
 
 const Bus = @import("../Bus.zig");
@@ -16,3 +17,11 @@ pub fn branch(comptime L: bool) InstrFn {
         }
     }.inner;
 }
+
+pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+    const rn = opcode & 0xF;
+    cpu.cpsr.t.write(cpu.r[rn] & 1 == 1);
+
+    // TODO: Is this how I should do it?
+    cpu.r[15] = cpu.r[rn] & 0xFFFF_FFFE;
+}

src/cpu/data_processing.zig

@@ -9,24 +9,29 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
             const rd = opcode >> 12 & 0xF;
-            const op1 = opcode >> 16 & 0xF;
+            const rn = opcode >> 16 & 0xF;
+
+            if (S and rd == 0xF) std.debug.panic("[CPU] Data Processing Instruction w/ S set and Rd == 15", .{});
+
+            var op1: u32 = undefined;
+            if (rn == 0xF) {
+                op1 = cpu.fakePC();
+            } else {
+                op1 = cpu.r[rn];
+            }
 
             var op2: u32 = undefined;
             if (I) {
                 op2 = std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1);
-            } else {
-                if (S and rd == 0xF) {
-                    std.debug.panic("[CPU] Data Processing Instruction w/ S set and Rd == 15", .{});
             } else {
                 op2 = BarrelShifter.exec(S, cpu, opcode);
             }
-            }
 
             switch (instrKind) {
                 0x4 => {
                     // ADD
                     var result: u32 = undefined;
-                    const didOverflow = @addWithOverflow(u32, cpu.r[op1], op2, &result);
+                    const didOverflow = @addWithOverflow(u32, op1, op2, &result);
                     cpu.r[rd] = result;
 
                     if (S and rd != 0xF) {
@@ -38,7 +43,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                 },
                 0x8 => {
                     // TST
-                    const result = cpu.r[op1] & op2;
+                    const result = op1 & op2;
 
                     cpu.cpsr.n.write(result >> 31 & 1 == 1);
                     cpu.cpsr.z.write(result == 0);
@@ -47,7 +52,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                 },
                 0x9 => {
                     // TEQ
-                    const result = cpu.r[op1] ^ op2;
+                    const result = op1 ^ op2;
 
                     cpu.cpsr.n.write(result >> 31 & 1 == 1);
                     cpu.cpsr.z.write(result == 0);
@@ -66,16 +71,16 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
                 },
                 0xA => {
                     // CMP
-                    const result = cpu.r[op1] -% op2;
+                    const result = op1 -% op2;
 
                     cpu.cpsr.n.write(result >> 31 & 1 == 1);
                     cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(op2 <= cpu.r[op1]);
+                    cpu.cpsr.c.write(op2 <= op1);
                     cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
                 },
                 0xC => {
                     // ORR
-                    const result = cpu.r[op1] | op2;
+                    const result = op1 | op2;
                     cpu.r[rd] = result;
 
                     if (S and rd != 0xF) {

src/cpu/half_signed_data_transfer.zig

@@ -13,7 +13,13 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
             const rm = opcode & 0xF;
             const imm_offset_high = opcode >> 8 & 0xF;
 
-            const base = cpu.r[rn];
+            var base: u32 = undefined;
+            if (rn == 0xF) {
+                base = cpu.fakePC();
+                if (!L) base += 4;
+            } else {
+                base = cpu.r[rn];
+            }
 
             var offset: u32 = undefined;
             if (I) {
@@ -33,7 +39,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
                     },
                     0b01 => {
                         // LDRH
-                        cpu.r[rd] = bus.read16(address);
+                        const value = bus.read16(address & 0xFFFF_FFFE);
+                        cpu.r[rd] = std.math.rotr(u32, @as(u32, value), 8 * (address & 1));
                     },
                     0b10 => {
                         // LDRSB