feat: add gdb support to zba

is this really a fix? the error never happens with mach-glfw

README.md

@@ -10,7 +10,7 @@ This is a simple (read: incomplete) for-fun long-term project. I hope to get "mo
 
 ### TODO
 
-- [ ] Affine Sprites
+- [x] Affine Sprites
 - [ ] Windowing (see [this branch](https://git.musuka.dev/paoda/zba/src/branch/window))
 - [ ] Audio Resampler (Having issues with SDL2's)
 - [ ] Immediate Mode GUI
@@ -77,7 +77,7 @@ arm7wrestler GBA Fixed | [destoer](https://github.com/destoer)
 
 ## Compiling
 
-Most recently built on Zig [0.11.0-dev.368+1829b6eab](https://github.com/ziglang/zig/tree/1829b6eab)
+Most recently built on Zig [v0.11.0-dev.987+a1d82352d](https://github.com/ziglang/zig/tree/a1d82352d)
 
 ### Dependencies
 

build.zig

@@ -6,7 +6,7 @@ const Gdbstub = @import("lib/zba-gdbstub/build.zig");
 
 pub fn build(b: *std.build.Builder) void {
     // Minimum Zig Version
-    const min_ver = std.SemanticVersion.parse("0.11.0-dev.323+30eb2a175") catch return; // https://github.com/ziglang/zig/commit/30eb2a175
+    const min_ver = std.SemanticVersion.parse("0.11.0-dev.987+a1d82352d") catch return; // https://github.com/ziglang/zig/commit/19056cb68
     if (builtin.zig_version.order(min_ver).compare(.lt)) {
         std.log.err("{s}", .{b.fmt("Zig v{} does not meet the minimum version requirement. (Zig v{})", .{ builtin.zig_version, min_ver })});
         std.os.exit(1);

lib/zba-gdbstub

@@ -1 +1 @@
-Subproject commit 1bd9964f58b21aecfb39675258370c68ffeb0593
+Subproject commit 4bca44e5f2a4aa19361b51b7617a21f46f88eef4

lib/zig-clap

@@ -1 +1 @@
-Subproject commit 8a38c14266d1d00e0c3aee16b2e2b69675209147
+Subproject commit 88edafd00ec25dcc01deb8fc69e9864a16f8717c

src/core/Bus.zig

@@ -60,9 +60,8 @@ allocator: Allocator,
 pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
     const tables = try allocator.alloc(?*anyopaque, 3 * table_len); // Allocate all tables
 
-    const read_table: *[table_len]?*const anyopaque = tables[0..table_len];
+    const read_table = tables[0..table_len];
-    const left_write: *[table_len]?*anyopaque = tables[table_len .. 2 * table_len];
+    const write_tables = .{ tables[table_len .. 2 * table_len], tables[2 * table_len .. 3 * table_len] };
-    const right_write: *[table_len]?*anyopaque = tables[2 * table_len .. 3 * table_len];
 
     self.* = .{
         .pak = try GamePak.init(allocator, cpu, paths.rom, paths.save),
@@ -78,18 +77,15 @@ pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi
         .sched = sched,
 
         .read_table = read_table,
-        .write_tables = .{ left_write, right_write },
+        .write_tables = write_tables,
         .allocator = allocator,
     };
 
-    // read_table, write_tables, and *Self are not restricted to the lifetime
+    self.fillReadTable(read_table);
-    // of this init function so we can initialize our tables here
-    fillReadTable(self, read_table);
 
-    // Internal Display Memory behavious unusually on 8-bit reads
+    // Internal Display Memory behaves differently on 8-bit reads
-    // so we have two different tables depending on whether there's an 8-bit read or not
+    self.fillWriteTable(u32, write_tables[0]);
-    fillWriteTable(u32, self, left_write);
+    self.fillWriteTable(u8, write_tables[1]);
-    fillWriteTable(u8, self, right_write);
 }
 
 pub fn deinit(self: *Self) void {
@@ -106,50 +102,50 @@ pub fn deinit(self: *Self) void {
     self.* = undefined;
 }
 
-fn fillReadTable(bus: *Self, table: *[table_len]?*const anyopaque) void {
+fn fillReadTable(self: *Self, table: *[table_len]?*const anyopaque) void {
-    const vramMirror = @import("ppu.zig").Vram.mirror;
+    const vramMirror = @import("ppu/Vram.zig").mirror;
 
     for (table) |*ptr, i| {
-        const addr = page_size * i;
+        const addr = @intCast(u32, page_size * i);
 
         ptr.* = switch (addr) {
             // General Internal Memory
             0x0000_0000...0x0000_3FFF => null, // BIOS has it's own checks
-            0x0200_0000...0x02FF_FFFF => &bus.ewram.buf[addr & 0x3FFFF],
+            0x0200_0000...0x02FF_FFFF => &self.ewram.buf[addr & 0x3FFFF],
-            0x0300_0000...0x03FF_FFFF => &bus.iwram.buf[addr & 0x7FFF],
+            0x0300_0000...0x03FF_FFFF => &self.iwram.buf[addr & 0x7FFF],
             0x0400_0000...0x0400_03FF => null, // I/O
 
             // Internal Display Memory
-            0x0500_0000...0x05FF_FFFF => &bus.ppu.palette.buf[addr & 0x3FF],
+            0x0500_0000...0x05FF_FFFF => &self.ppu.palette.buf[addr & 0x3FF],
-            0x0600_0000...0x06FF_FFFF => &bus.ppu.vram.buf[vramMirror(addr)],
+            0x0600_0000...0x06FF_FFFF => &self.ppu.vram.buf[vramMirror(addr)],
-            0x0700_0000...0x07FF_FFFF => &bus.ppu.oam.buf[addr & 0x3FF],
+            0x0700_0000...0x07FF_FFFF => &self.ppu.oam.buf[addr & 0x3FF],
 
             // External Memory (Game Pak)
-            0x0800_0000...0x0DFF_FFFF => fillTableExternalMemory(bus, addr),
+            0x0800_0000...0x0DFF_FFFF => self.fillReadTableExternal(addr),
             0x0E00_0000...0x0FFF_FFFF => null, // SRAM
             else => null,
         };
     }
 }
 
-fn fillWriteTable(comptime T: type, bus: *Self, table: *[table_len]?*const anyopaque) void {
+fn fillWriteTable(self: *Self, comptime T: type, table: *[table_len]?*const anyopaque) void {
     comptime std.debug.assert(T == u32 or T == u16 or T == u8);
-    const vramMirror = @import("ppu.zig").Vram.mirror;
+    const vramMirror = @import("ppu/Vram.zig").mirror;
 
     for (table) |*ptr, i| {
-        const addr = page_size * i;
+        const addr = @intCast(u32, page_size * i);
 
         ptr.* = switch (addr) {
             // General Internal Memory
             0x0000_0000...0x0000_3FFF => null, // BIOS has it's own checks
-            0x0200_0000...0x02FF_FFFF => &bus.ewram.buf[addr & 0x3FFFF],
+            0x0200_0000...0x02FF_FFFF => &self.ewram.buf[addr & 0x3FFFF],
-            0x0300_0000...0x03FF_FFFF => &bus.iwram.buf[addr & 0x7FFF],
+            0x0300_0000...0x03FF_FFFF => &self.iwram.buf[addr & 0x7FFF],
             0x0400_0000...0x0400_03FF => null, // I/O
 
             // Internal Display Memory
-            0x0500_0000...0x05FF_FFFF => if (T != u8) &bus.ppu.palette.buf[addr & 0x3FF] else null,
+            0x0500_0000...0x05FF_FFFF => if (T != u8) &self.ppu.palette.buf[addr & 0x3FF] else null,
-            0x0600_0000...0x06FF_FFFF => if (T != u8) &bus.ppu.vram.buf[vramMirror(addr)] else null,
+            0x0600_0000...0x06FF_FFFF => if (T != u8) &self.ppu.vram.buf[vramMirror(addr)] else null,
-            0x0700_0000...0x07FF_FFFF => if (T != u8) &bus.ppu.oam.buf[addr & 0x3FF] else null,
+            0x0700_0000...0x07FF_FFFF => if (T != u8) &self.ppu.oam.buf[addr & 0x3FF] else null,
 
             // External Memory (Game Pak)
             0x0800_0000...0x0DFF_FFFF => null, // ROM
@@ -159,24 +155,29 @@ fn fillWriteTable(comptime T: type, bus: *Self, table: *[table_len]?*const anyop
     }
 }
 
-fn fillTableExternalMemory(bus: *Self, addr: usize) ?*anyopaque {
+fn fillReadTableExternal(self: *Self, addr: u32) ?*anyopaque {
     // see `GamePak.zig` for more information about what conditions need to be true
     // so that a simple pointer dereference isn't possible
 
+    std.debug.assert(addr & @as(u32, page_size - 1) == 0); // addr is guaranteed to be page-aligned
+
     const start_addr = addr;
-    const end_addr = addr + page_size;
+    const end_addr = start_addr + page_size;
 
-    const gpio_data = start_addr <= 0x0800_00C4 and 0x0800_00C4 < end_addr;
+    {
-    const gpio_direction = start_addr <= 0x0800_00C6 and 0x0800_00C6 < end_addr;
+        const data = start_addr <= 0x0800_00C4 and 0x0800_00C4 < end_addr; // GPIO Data
-    const gpio_control = start_addr <= 0x0800_00C8 and 0x0800_00C8 < end_addr;
+        const direction = start_addr <= 0x0800_00C6 and 0x0800_00C6 < end_addr; // GPIO Direction
+        const control = start_addr <= 0x0800_00C8 and 0x0800_00C8 < end_addr; // GPIO Control
 
-    if (bus.pak.gpio.device.kind != .None and (gpio_data or gpio_direction or gpio_control)) {
+        const has_gpio = data or direction or control;
-        // We found a GPIO device, and this page a GPIO register. We want to handle this in slowmem
+        const gpio_kind = self.pak.gpio.device.kind;
-        return null;
+
+        // There is a GPIO Device, and the current page contains at least one memory-mapped GPIO register
+        if (gpio_kind != .None and has_gpio) return null;
     }
 
-    if (bus.pak.backup.kind == .Eeprom) {
+    if (self.pak.backup.kind == .Eeprom) {
-        if (bus.pak.buf.len > 0x100_000) {
+        if (self.pak.buf.len > 0x100_000) {
             // We are using a "large" EEPROM which means that if the below check is true
             // this page has an address that's reserved for the EEPROM and therefore must
             // be handled in slowmem
@@ -192,9 +193,9 @@ fn fillTableExternalMemory(bus: *Self, addr: usize) ?*anyopaque {
     // Finally, the GamePak has some unique behaviour for reads past the end of the ROM,
     // so those will be handled by slowmem as well
     const masked_addr = addr & 0x1FF_FFFF;
-    if (masked_addr >= bus.pak.buf.len) return null;
+    if (masked_addr >= self.pak.buf.len) return null;
 
-    return &bus.pak.buf[masked_addr];
+    return &self.pak.buf[masked_addr];
 }
 
 pub fn dbgRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
@@ -208,8 +209,7 @@ pub fn dbgRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
     if (self.read_table[page]) |some_ptr| {
         // We have a pointer to a page, cast the pointer to it's underlying type
         const Ptr = [*]const T;
-        const alignment = @alignOf(std.meta.Child(Ptr));
+        const ptr = @ptrCast(Ptr, @alignCast(@alignOf(std.meta.Child(Ptr)), some_ptr));
-        const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
 
         // Note: We don't check array length, since we force align the
         // lower bits of the address as the GBA would
@@ -227,7 +227,7 @@ fn dbgSlowRead(self: *const Self, comptime T: type, unaligned_address: u32) T {
         // General Internal Memory
         0x00 => blk: {
             if (address < Bios.size)
-                break :blk self.bios.dbgRead(T, self.cpu.r[15], address);
+                break :blk self.bios.dbgRead(T, self.cpu.r[15], unaligned_address);
 
             break :blk self.openBus(T, address);
         },
@@ -326,8 +326,7 @@ pub fn read(self: *Self, comptime T: type, unaligned_address: u32) T {
     if (self.read_table[page]) |some_ptr| {
         // We have a pointer to a page, cast the pointer to it's underlying type
         const Ptr = [*]const T;
-        const alignment = @alignOf(std.meta.Child(Ptr));
+        const ptr = @ptrCast(Ptr, @alignCast(@alignOf(std.meta.Child(Ptr)), some_ptr));
-        const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
 
         // Note: We don't check array length, since we force align the
         // lower bits of the address as the GBA would
@@ -347,7 +346,7 @@ fn slowRead(self: *Self, comptime T: type, unaligned_address: u32) T {
         // General Internal Memory
         0x00 => blk: {
             if (address < Bios.size)
-                break :blk self.bios.read(T, self.cpu.r[15], address);
+                break :blk self.bios.read(T, self.cpu.r[15], unaligned_address);
 
             break :blk self.openBus(T, address);
         },
@@ -394,8 +393,7 @@ pub fn write(self: *Self, comptime T: type, unaligned_address: u32, value: T) vo
     if (self.write_tables[@boolToInt(T == u8)][page]) |some_ptr| {
         // We have a pointer to a page, cast the pointer to it's underlying type
         const Ptr = [*]T;
-        const alignment = @alignOf(std.meta.Child(Ptr));
+        const ptr = @ptrCast(Ptr, @alignCast(@alignOf(std.meta.Child(Ptr)), some_ptr));
-        const ptr = @ptrCast(Ptr, @alignCast(alignment, some_ptr));
 
         // Note: We don't check array length, since we force align the
         // lower bits of the address as the GBA would
@@ -408,8 +406,9 @@ pub fn write(self: *Self, comptime T: type, unaligned_address: u32, value: T) vo
     }
 }
 
-pub fn slowWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
+fn slowWrite(self: *Self, comptime T: type, unaligned_address: u32, value: T) void {
-    // @setCold(true);
+    @setCold(true);
+
     const page = @truncate(u8, unaligned_address >> 24);
     const address = forceAlign(T, unaligned_address);
 
@@ -437,11 +436,11 @@ inline fn rotateBy(comptime T: type, address: u32) u32 {
         u32 => address & 3,
         u16 => address & 1,
         u8 => 0,
-        else => @compileError("Backup: Unsupported write width"),
+        else => @compileError("Unsupported write width"),
     };
 }
 
-inline fn forceAlign(comptime T: type, address: u32) u32 {
+pub inline fn forceAlign(comptime T: type, address: u32) u32 {
     return switch (T) {
         u32 => address & ~@as(u32, 3),
         u16 => address & ~@as(u32, 1),

src/core/bus/Bios.zig

@@ -3,6 +3,9 @@ const std = @import("std");
 const Allocator = std.mem.Allocator;
 const log = std.log.scoped(.Bios);
 
+const rotr = @import("../../util.zig").rotr;
+const forceAlign = @import("../Bus.zig").forceAlign;
+
 /// Size of the BIOS in bytes
 pub const size = 0x4000;
 const Self = @This();
@@ -10,21 +13,37 @@ const Self = @This();
 buf: ?[]u8,
 allocator: Allocator,
 
-addr_latch: u32,
+addr_latch: u32 = 0,
 
-pub fn read(self: *Self, comptime T: type, r15: u32, addr: u32) T {
+// https://github.com/ITotalJustice/notorious_beeg/issues/106
+pub fn read(self: *Self, comptime T: type, r15: u32, address: u32) T {
     if (r15 < Self.size) {
+        const addr = forceAlign(T, address);
+
         self.addr_latch = addr;
         return self._read(T, addr);
     }
 
-    log.debug("Rejected read since r15=0x{X:0>8}", .{r15});
+    log.warn("Open Bus! Read from 0x{X:0>8}, but PC was 0x{X:0>8}", .{ address, r15 });
-    return @truncate(T, self._read(T, self.addr_latch));
+    const value = self._read(u32, self.addr_latch);
+
+    return @truncate(T, rotr(u32, value, 8 * rotateBy(T, address)));
 }
 
-pub fn dbgRead(self: *const Self, comptime T: type, r15: u32, addr: u32) T {
+fn rotateBy(comptime T: type, address: u32) u32 {
-    if (r15 < Self.size) return self._read(T, addr);
+    return switch (T) {
-    return @truncate(T, self._read(T, self.addr_latch + 8));
+        u8 => address & 3,
+        u16 => address & 2,
+        u32 => 0,
+        else => @compileError("bios: unsupported read width"),
+    };
+}
+
+pub fn dbgRead(self: *const Self, comptime T: type, r15: u32, address: u32) T {
+    if (r15 < Self.size) return self._read(T, forceAlign(T, address));
+
+    const value = self._read(u32, self.addr_latch);
+    return @truncate(T, rotr(u32, value, 8 * rotateBy(T, address)));
 }
 
 /// Read without the GBA safety checks
@@ -43,18 +62,19 @@ pub fn write(_: *Self, comptime T: type, addr: u32, value: T) void {
 }
 
 pub fn init(allocator: Allocator, maybe_path: ?[]const u8) !Self {
-    const buf: ?[]u8 = if (maybe_path) |path| blk: {
+    if (maybe_path == null) return .{ .buf = null, .allocator = allocator };
+    const path = maybe_path.?;
+
+    const buf = try allocator.alloc(u8, Self.size);
+    errdefer allocator.free(buf);
+
     const file = try std.fs.cwd().openFile(path, .{});
     defer file.close();
 
-        break :blk try file.readToEndAlloc(allocator, try file.getEndPos());
+    const file_len = try file.readAll(buf);
-    } else null;
+    if (file_len != Self.size) log.err("Expected BIOS to be {}B, was {}B", .{ Self.size, file_len });
 
-    return Self{
+    return Self{ .buf = buf, .allocator = allocator };
-        .buf = buf,
-        .allocator = allocator,
-        .addr_latch = 0,
-    };
 }
 
 pub fn deinit(self: *Self) void {

src/core/bus/dma.zig

@@ -338,7 +338,7 @@ fn DmaController(comptime id: u2) type {
     };
 }
 
-pub fn pollDmaOnBlank(bus: *Bus, comptime kind: DmaKind) void {
+pub fn onBlanking(bus: *Bus, comptime kind: DmaKind) void {
     comptime var i: usize = 0;
     inline while (i < 4) : (i += 1) {
         bus.dma[i].poll(kind);

src/core/bus/io.zig

@@ -449,6 +449,8 @@ pub const BldY = extern union {
     raw: u16,
 };
 
+const u8WriteKind = enum { Hi, Lo };
+
 /// Write-only
 pub const WinH = extern union {
     x2: Bitfield(u16, 0, 8),
@@ -458,6 +460,8 @@ pub const WinH = extern union {
 
 /// Write-only
 pub const WinV = extern union {
+    const Self = @This();
+
     y2: Bitfield(u16, 0, 8),
     y1: Bitfield(u16, 8, 8),
     raw: u16,
@@ -466,20 +470,20 @@ pub const WinV = extern union {
 pub const WinIn = extern union {
     w0_bg: Bitfield(u16, 0, 4),
     w0_obj: Bit(u16, 4),
-    w0_colour: Bit(u16, 5),
+    w0_bld: Bit(u16, 5),
     w1_bg: Bitfield(u16, 8, 4),
     w1_obj: Bit(u16, 12),
-    w1_colour: Bit(u16, 13),
+    w1_bld: Bit(u16, 13),
     raw: u16,
 };
 
 pub const WinOut = extern union {
     out_bg: Bitfield(u16, 0, 4),
     out_obj: Bit(u16, 4),
-    out_colour: Bit(u16, 5),
+    out_bld: Bit(u16, 5),
     obj_bg: Bitfield(u16, 8, 4),
     obj_obj: Bit(u16, 12),
-    obj_colour: Bit(u16, 13),
+    obj_bld: Bit(u16, 13),
     raw: u16,
 };
 

src/core/cpu/arm/data_processing.zig

@@ -24,7 +24,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
 
             var result: u32 = undefined;
-            var overflow: bool = undefined;
+            var overflow: u1 = undefined;
 
             // Perform Data Processing Logic
             switch (kind) {
@@ -62,7 +62,9 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
                     if (rd == 0xF)
                         return undefinedTestBehaviour(cpu);
 
-                    overflow = @addWithOverflow(u32, op1, op2, &result);
+                    const tmp = @addWithOverflow(op1, op2);
+                    result = tmp[0];
+                    overflow = tmp[1];
                 },
                 0xC => result = op1 | op2, // ORR
                 0xD => result = op2, // MOV
@@ -110,7 +112,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
                     // ADD, ADC Flags
                     cpu.cpsr.n.write(result >> 31 & 1 == 1);
                     cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(overflow);
+                    cpu.cpsr.c.write(overflow == 0b1);
                     cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
                 },
                 0x6, 0x7 => if (S and rd != 0xF) {
@@ -141,7 +143,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) Ins
                         cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
                     } else if (kind == 0xB) {
                         // CMN specific
-                        cpu.cpsr.c.write(overflow);
+                        cpu.cpsr.c.write(overflow == 0b1);
                         cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
                     } else {
                         // TST, TEQ specific
@@ -162,19 +164,19 @@ pub fn sbc(left: u32, right: u32, old_carry: u1) u32 {
     return ret;
 }
 
-pub fn add(overflow: *bool, left: u32, right: u32) u32 {
+pub fn add(overflow: *u1, left: u32, right: u32) u32 {
-    var ret: u32 = undefined;
+    const ret = @addWithOverflow(left, right);
-    overflow.* = @addWithOverflow(u32, left, right, &ret);
+    overflow.* = ret[1];
-    return ret;
+
+    return ret[0];
 }
 
-pub fn adc(overflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
+pub fn adc(overflow: *u1, left: u32, right: u32, old_carry: u1) u32 {
-    var ret: u32 = undefined;
+    const tmp = @addWithOverflow(left, right);
-    const first = @addWithOverflow(u32, left, right, &ret);
+    const ret = @addWithOverflow(tmp[0], old_carry);
-    const second = @addWithOverflow(u32, ret, old_carry, &ret);
+    overflow.* = tmp[1] | ret[1];
 
-    overflow.* = first or second;
+    return ret[0];
-    return ret;
 }
 
 fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {

src/core/cpu/thumb/alu.zig

@@ -21,7 +21,8 @@ pub fn fmt4(comptime op: u4) InstrFn {
             const op2 = cpu.r[rs];
 
             var result: u32 = undefined;
-            var overflow: bool = undefined;
+            var overflow: u1 = undefined;
+
             switch (op) {
                 0x0 => result = op1 & op2, // AND
                 0x1 => result = op1 ^ op2, // EOR
@@ -34,7 +35,12 @@ pub fn fmt4(comptime op: u4) InstrFn {
                 0x8 => result = op1 & op2, // TST
                 0x9 => result = 0 -% op2, // NEG
                 0xA => result = op1 -% op2, // CMP
-                0xB => overflow = @addWithOverflow(u32, op1, op2, &result), // CMN
+                0xB => {
+                    // CMN
+                    const tmp = @addWithOverflow(op1, op2);
+                    result = tmp[0];
+                    overflow = tmp[1];
+                },
                 0xC => result = op1 | op2, // ORR
                 0xD => result = @truncate(u32, @as(u64, op2) * @as(u64, op1)),
                 0xE => result = op1 & ~op2,
@@ -71,7 +77,7 @@ pub fn fmt4(comptime op: u4) InstrFn {
                     // ADC, CMN
                     cpu.cpsr.n.write(result >> 31 & 1 == 1);
                     cpu.cpsr.z.write(result == 0);
-                    cpu.cpsr.c.write(overflow);
+                    cpu.cpsr.c.write(overflow == 0b1);
                     cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
                 },
                 0x6 => {

src/core/cpu/thumb/data_processing.zig

@@ -64,7 +64,7 @@ pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
             const op2 = cpu.r[rs];
 
             var result: u32 = undefined;
-            var overflow: bool = undefined;
+            var overflow: u1 = undefined;
             switch (op) {
                 0b00 => result = add(&overflow, op1, op2), // ADD
                 0b01 => result = op1 -% op2, // CMP
@@ -126,13 +126,13 @@ pub fn fmt2(comptime I: bool, is_sub: bool, rn: u3) InstrFn {
                 cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
             } else {
                 // ADD
-                var overflow: bool = undefined;
+                var overflow: u1 = undefined;
                 const result = add(&overflow, op1, op2);
                 cpu.r[rd] = result;
 
                 cpu.cpsr.n.write(result >> 31 & 1 == 1);
                 cpu.cpsr.z.write(result == 0);
-                cpu.cpsr.c.write(overflow);
+                cpu.cpsr.c.write(overflow == 0b1);
                 cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
             }
         }
@@ -145,7 +145,7 @@ pub fn fmt3(comptime op: u2, comptime rd: u3) InstrFn {
             const op1 = cpu.r[rd];
             const op2: u32 = opcode & 0xFF; // Offset
 
-            var overflow: bool = undefined;
+            var overflow: u1 = undefined;
             const result: u32 = switch (op) {
                 0b00 => op2, // MOV
                 0b01 => op1 -% op2, // CMP
@@ -169,7 +169,7 @@ pub fn fmt3(comptime op: u2, comptime rd: u3) InstrFn {
                 },
                 0b10 => {
                     // ADD
-                    cpu.cpsr.c.write(overflow);
+                    cpu.cpsr.c.write(overflow == 0b1);
                     cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
                 },
             }

src/core/emu.zig

@@ -94,7 +94,7 @@ pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi) void {
         if (!cpu.stepDmaTransfer()) {
             if (cpu.isHalted()) {
                 // Fast-forward to next Event
-                sched.tick = sched.queue.peek().?.tick;
+                sched.tick = sched.nextTimestamp();
             } else {
                 cpu.step();
             }

src/core/ppu/Oam.zig

@@ -0,0 +1,40 @@
+const std = @import("std");
+
+const Allocator = std.mem.Allocator;
+
+const buf_len = 0x400;
+const Self = @This();
+
+buf: []u8,
+allocator: Allocator,
+
+pub fn read(self: *const Self, comptime T: type, address: usize) T {
+    const addr = address & 0x3FF;
+
+    return switch (T) {
+        u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
+        else => @compileError("OAM: Unsupported read width"),
+    };
+}
+
+pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
+    const addr = address & 0x3FF;
+
+    switch (T) {
+        u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
+        u8 => return, // 8-bit writes are explicitly ignored
+        else => @compileError("OAM: Unsupported write width"),
+    }
+}
+
+pub fn init(allocator: Allocator) !Self {
+    const buf = try allocator.alloc(u8, buf_len);
+    std.mem.set(u8, buf, 0);
+
+    return Self{ .buf = buf, .allocator = allocator };
+}
+
+pub fn deinit(self: *Self) void {
+    self.allocator.free(self.buf);
+    self.* = undefined;
+}

src/core/ppu/Palette.zig

@@ -0,0 +1,47 @@
+const std = @import("std");
+
+const Allocator = std.mem.Allocator;
+
+const buf_len = 0x400;
+const Self = @This();
+
+buf: []u8,
+allocator: Allocator,
+
+pub fn read(self: *const Self, comptime T: type, address: usize) T {
+    const addr = address & 0x3FF;
+
+    return switch (T) {
+        u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
+        else => @compileError("PALRAM: Unsupported read width"),
+    };
+}
+
+pub fn write(self: *Self, comptime T: type, address: usize, value: T) void {
+    const addr = address & 0x3FF;
+
+    switch (T) {
+        u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)], value),
+        u8 => {
+            const align_addr = addr & ~@as(u32, 1); // Aligned to Halfword boundary
+            std.mem.writeIntSliceLittle(u16, self.buf[align_addr..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
+        },
+        else => @compileError("PALRAM: Unsupported write width"),
+    }
+}
+
+pub fn init(allocator: Allocator) !Self {
+    const buf = try allocator.alloc(u8, buf_len);
+    std.mem.set(u8, buf, 0);
+
+    return Self{ .buf = buf, .allocator = allocator };
+}
+
+pub fn deinit(self: *Self) void {
+    self.allocator.free(self.buf);
+    self.* = undefined;
+}
+
+pub inline fn backdrop(self: *const Self) u16 {
+    return std.mem.readIntNative(u16, self.buf[0..2]);
+}

src/core/ppu/Vram.zig

@@ -0,0 +1,60 @@
+const std = @import("std");
+const io = @import("../bus/io.zig");
+
+const Allocator = std.mem.Allocator;
+
+const buf_len = 0x18000;
+const Self = @This();
+
+buf: []u8,
+allocator: Allocator,
+
+pub fn read(self: *const Self, comptime T: type, address: usize) T {
+    const addr = Self.mirror(address);
+
+    return switch (T) {
+        u32, u16, u8 => std.mem.readIntSliceLittle(T, self.buf[addr..][0..@sizeOf(T)]),
+        else => @compileError("VRAM: Unsupported read width"),
+    };
+}
+
+pub fn write(self: *Self, comptime T: type, dispcnt: io.DisplayControl, address: usize, value: T) void {
+    const mode: u3 = dispcnt.bg_mode.read();
+    const idx = Self.mirror(address);
+
+    switch (T) {
+        u32, u16 => std.mem.writeIntSliceLittle(T, self.buf[idx..][0..@sizeOf(T)], value),
+        u8 => {
+            // Ignore write if it falls within the boundaries of OBJ VRAM
+            switch (mode) {
+                0, 1, 2 => if (0x0001_0000 <= idx) return,
+                else => if (0x0001_4000 <= idx) return,
+            }
+
+            const align_idx = idx & ~@as(u32, 1); // Aligned to a halfword boundary
+            std.mem.writeIntSliceLittle(u16, self.buf[align_idx..][0..@sizeOf(u16)], @as(u16, value) * 0x101);
+        },
+        else => @compileError("VRAM: Unsupported write width"),
+    }
+}
+
+pub fn init(allocator: Allocator) !Self {
+    const buf = try allocator.alloc(u8, buf_len);
+    std.mem.set(u8, buf, 0);
+
+    return Self{ .buf = buf, .allocator = allocator };
+}
+
+pub fn deinit(self: *Self) void {
+    self.allocator.free(self.buf);
+    self.* = undefined;
+}
+
+pub fn mirror(address: usize) usize {
+    // Mirrored in steps of 128K (64K + 32K + 32K) (abcc)
+    const addr = address & 0x1FFFF;
+
+    // If the address is within 96K we don't do anything,
+    // otherwise we want to mirror the last 32K (addresses between 64K and 96K)
+    return if (addr < buf_len) addr else 0x10000 + (addr & 0x7FFF);
+}

src/core/scheduler.zig

@@ -31,7 +31,7 @@ pub const Scheduler = struct {
     }
 
     pub fn handleEvent(self: *Self, cpu: *Arm7tdmi) void {
-        if (self.queue.removeOrNull()) |event| {
+        const event = self.queue.remove();
         const late = self.tick - event.tick;
 
         switch (event.kind) {
@@ -70,22 +70,16 @@ pub const Scheduler = struct {
             .VBlank => cpu.bus.ppu.onHdrawEnd(cpu, late), // The end of a VBlank
         }
     }
-    }
 
     /// Removes the **first** scheduled event of type `needle`
     pub fn removeScheduledEvent(self: *Self, needle: EventKind) void {
-        var it = self.queue.iterator();
+        for (self.queue.items) |event, i| {
-
-        var i: usize = 0;
-        while (it.next()) |event| : (i += 1) {
             if (std.meta.eql(event.kind, needle)) {
 
-                // This invalidates the iterator
+                // invalidates the slice we're iterating over
                 _ = self.queue.removeIndex(i);
 
-                // Since removing something from the PQ invalidates the iterator,
+                log.debug("Removed {?}@{}", .{ event.kind, event.tick });
-                // this implementation can safely only remove the first instance of
-                // a Scheduled Event. Exit Early
                 break;
             }
         }

src/platform.zig

@@ -64,7 +64,7 @@ pub const Gui = struct {
         const ctx = SDL.SDL_GL_CreateContext(window) orelse panic();
         if (SDL.SDL_GL_MakeCurrent(window, ctx) < 0) panic();
 
-        try gl.load(ctx, Self.glGetProcAddress);
+        gl.load(ctx, Self.glGetProcAddress) catch {};
         if (SDL.SDL_GL_SetSwapInterval(@boolToInt(config.config().host.vsync)) < 0) panic();
 
         const program_id = try compileShaders();

src/util.zig

@@ -5,6 +5,8 @@ const config = @import("config.zig");
 const Log2Int = std.math.Log2Int;
 const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
 
+const Allocator = std.mem.Allocator;
+
 // Sign-Extend value of type `T` to type `U`
 pub fn sext(comptime T: type, comptime U: type, value: T) T {
     // U must have less bits than T
@@ -123,6 +125,7 @@ pub const io = struct {
 
 pub const Logger = struct {
     const Self = @This();
+    const FmtArgTuple = std.meta.Tuple(&.{ u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32 });
 
     buf: std.io.BufferedWriter(4096 << 2, std.fs.File.Writer),
 
@@ -181,8 +184,6 @@ pub const Logger = struct {
     }
 };
 
-const FmtArgTuple = struct { u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32, u32 };
-
 pub const audio = struct {
     const _io = @import("core/bus/io.zig");
 
@@ -275,3 +276,44 @@ fn HalfInt(comptime T: type) type {
 
     return std.meta.Int(type_info.Int.signedness, type_info.Int.bits >> 1);
 }
+
+/// Double Buffering Implementation
+pub const FrameBuffer = struct {
+    const Self = @This();
+
+    layers: [2][]u8,
+    buf: []u8,
+    current: u1,
+
+    allocator: Allocator,
+
+    // TODO: Rename
+    const Device = enum { Emulator, Renderer };
+
+    pub fn init(allocator: Allocator, comptime len: comptime_int) !Self {
+        const buf = try allocator.alloc(u8, len * 2);
+        std.mem.set(u8, buf, 0);
+
+        return .{
+            // Front and Back Framebuffers
+            .layers = [_][]u8{ buf[0..][0..len], buf[len..][0..len] },
+            .buf = buf,
+            .current = 0,
+
+            .allocator = allocator,
+        };
+    }
+
+    pub fn deinit(self: *Self) void {
+        self.allocator.free(self.buf);
+        self.* = undefined;
+    }
+
+    pub fn swap(self: *Self) void {
+        self.current = ~self.current;
+    }
+
+    pub fn get(self: *Self, comptime dev: Device) []u8 {
+        return self.layers[if (dev == .Emulator) self.current else ~self.current];
+    }
+};