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17 Commits
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b2ecfd1b6b
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@ -2,13 +2,13 @@
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An in-progress Game Boy Advance Emulator written in Zig ⚡!
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## Tests
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- [ ] [jsmolka's GBA Test Collection](https://github.com/jsmolka/gba-tests)
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- [x] [jsmolka's GBA Test Collection](https://github.com/jsmolka/gba-tests)
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- [x] `arm.gba` and `thumb.gba`
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- [x] `flash64.gba`, `flash128.gba`, `none.gba`, and `sram.gba`
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- [x] `hello.gba`, `shades.gba`, and `stripes.gba`
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- [x] `memory.gba`
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- [x] `bios.gba`
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- [ ] `nes.gba`
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- [x] `nes.gba`
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- [ ] [DenSinH's GBA ROMs](https://github.com/DenSinH/GBARoms)
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- [x] `eeprom-test` and `flash-test`
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- [x] `midikey2freq`
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194
src/Gui.zig
194
src/Gui.zig
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@ -1,194 +0,0 @@
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const std = @import("std");
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const SDL = @import("sdl2");
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const Self = @This();
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const Apu = @import("core/apu.zig").Apu;
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const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
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const Scheduler = @import("core/scheduler.zig").Scheduler;
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const FpsTracker = @import("core/util.zig").FpsTracker;
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const pitch = @import("core/ppu.zig").framebuf_pitch;
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const scale = @import("core/emu.zig").win_scale;
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const emu = @import("core/emu.zig");
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const log = std.log.scoped(.GUI);
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const default_title: []const u8 = "ZBA";
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window: *SDL.SDL_Window,
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base_title: [12]u8,
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renderer: *SDL.SDL_Renderer,
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texture: *SDL.SDL_Texture,
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audio: ?Audio,
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pub fn init(title: [12]u8, width: i32, height: i32) Self {
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const ret = SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO | SDL.SDL_INIT_GAMECONTROLLER);
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if (ret < 0) panic();
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const window = SDL.SDL_CreateWindow(
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default_title.ptr,
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SDL.SDL_WINDOWPOS_CENTERED,
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SDL.SDL_WINDOWPOS_CENTERED,
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@as(c_int, width * scale),
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@as(c_int, height * scale),
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SDL.SDL_WINDOW_SHOWN,
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) orelse panic();
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const renderer = SDL.SDL_CreateRenderer(window, -1, SDL.SDL_RENDERER_ACCELERATED | SDL.SDL_RENDERER_PRESENTVSYNC) orelse panic();
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const texture = SDL.SDL_CreateTexture(
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renderer,
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SDL.SDL_PIXELFORMAT_RGBA8888,
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SDL.SDL_TEXTUREACCESS_STREAMING,
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@as(c_int, width),
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@as(c_int, height),
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) orelse panic();
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return Self{
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.window = window,
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.base_title = title,
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.renderer = renderer,
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.texture = texture,
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.audio = null,
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};
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}
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pub fn run(self: *Self, cpu: *Arm7tdmi, scheduler: *Scheduler) !void {
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var quit = std.atomic.Atomic(bool).init(false);
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var frame_rate = FpsTracker.init();
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const thread = try std.Thread.spawn(.{}, emu.run, .{ &quit, &frame_rate, scheduler, cpu });
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defer thread.join();
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var title_buf: [0x100]u8 = [_]u8{0} ** 0x100;
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emu_loop: while (true) {
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var event: SDL.SDL_Event = undefined;
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while (SDL.SDL_PollEvent(&event) != 0) {
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switch (event.type) {
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SDL.SDL_QUIT => break :emu_loop,
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SDL.SDL_KEYDOWN => {
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const io = &cpu.bus.io;
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const key_code = event.key.keysym.sym;
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switch (key_code) {
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SDL.SDLK_UP => io.keyinput.up.unset(),
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SDL.SDLK_DOWN => io.keyinput.down.unset(),
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SDL.SDLK_LEFT => io.keyinput.left.unset(),
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SDL.SDLK_RIGHT => io.keyinput.right.unset(),
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SDL.SDLK_x => io.keyinput.a.unset(),
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SDL.SDLK_z => io.keyinput.b.unset(),
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SDL.SDLK_a => io.keyinput.shoulder_l.unset(),
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SDL.SDLK_s => io.keyinput.shoulder_r.unset(),
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SDL.SDLK_RETURN => io.keyinput.start.unset(),
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SDL.SDLK_RSHIFT => io.keyinput.select.unset(),
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else => {},
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}
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},
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SDL.SDL_KEYUP => {
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const io = &cpu.bus.io;
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const key_code = event.key.keysym.sym;
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switch (key_code) {
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SDL.SDLK_UP => io.keyinput.up.set(),
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SDL.SDLK_DOWN => io.keyinput.down.set(),
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SDL.SDLK_LEFT => io.keyinput.left.set(),
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SDL.SDLK_RIGHT => io.keyinput.right.set(),
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SDL.SDLK_x => io.keyinput.a.set(),
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SDL.SDLK_z => io.keyinput.b.set(),
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SDL.SDLK_a => io.keyinput.shoulder_l.set(),
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SDL.SDLK_s => io.keyinput.shoulder_r.set(),
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SDL.SDLK_RETURN => io.keyinput.start.set(),
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SDL.SDLK_RSHIFT => io.keyinput.select.set(),
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SDL.SDLK_i => log.err("Sample Count: {}", .{@intCast(u32, SDL.SDL_AudioStreamAvailable(cpu.bus.apu.stream)) / (2 * @sizeOf(u16))}),
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SDL.SDLK_j => log.err("Scheduler Capacity: {} | Scheduler Event Count: {}", .{ scheduler.queue.capacity(), scheduler.queue.count() }),
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SDL.SDLK_k => {
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// Dump IWRAM to file
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log.info("PC: 0x{X:0>8}", .{cpu.r[15]});
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log.info("LR: 0x{X:0>8}", .{cpu.r[14]});
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// const iwram_file = try std.fs.cwd().createFile("iwram.bin", .{});
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// defer iwram_file.close();
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// try iwram_file.writeAll(cpu.bus.iwram.buf);
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},
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else => {},
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}
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},
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else => {},
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}
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}
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// Emulator has an internal Double Buffer
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const framebuf = cpu.bus.ppu.framebuf.get(.Renderer);
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_ = SDL.SDL_UpdateTexture(self.texture, null, framebuf.ptr, pitch);
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_ = SDL.SDL_RenderCopy(self.renderer, self.texture, null, null);
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SDL.SDL_RenderPresent(self.renderer);
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const title = std.fmt.bufPrint(&title_buf, "ZBA | {s} [Emu: {}fps] ", .{ self.base_title, frame_rate.value() }) catch unreachable;
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SDL.SDL_SetWindowTitle(self.window, title.ptr);
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}
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quit.store(true, .SeqCst); // Terminate Emulator Thread
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}
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pub fn initAudio(self: *Self, apu: *Apu) void {
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self.audio = Audio.init(apu);
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self.audio.?.play();
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}
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pub fn deinit(self: *Self) void {
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if (self.audio) |*aud| aud.deinit();
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SDL.SDL_DestroyTexture(self.texture);
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SDL.SDL_DestroyRenderer(self.renderer);
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SDL.SDL_DestroyWindow(self.window);
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SDL.SDL_Quit();
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self.* = undefined;
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}
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const Audio = struct {
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const This = @This();
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const sample_rate = @import("core/apu.zig").host_sample_rate;
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device: SDL.SDL_AudioDeviceID,
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fn init(apu: *Apu) This {
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var have: SDL.SDL_AudioSpec = undefined;
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var want: SDL.SDL_AudioSpec = std.mem.zeroes(SDL.SDL_AudioSpec);
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want.freq = sample_rate;
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want.format = SDL.AUDIO_U16;
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want.channels = 2;
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want.samples = 0x100;
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want.callback = This.callback;
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want.userdata = apu;
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const device = SDL.SDL_OpenAudioDevice(null, 0, &want, &have, 0);
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if (device == 0) panic();
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return .{
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.device = device,
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};
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}
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fn deinit(self: *This) void {
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SDL.SDL_CloseAudioDevice(self.device);
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self.* = undefined;
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}
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pub fn play(self: *This) void {
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SDL.SDL_PauseAudioDevice(self.device, 0);
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}
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export fn callback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void {
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const apu = @ptrCast(*Apu, @alignCast(@alignOf(*Apu), userdata));
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_ = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
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// If we don't write anything, play silence otherwise garbage will be played
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// FIXME: I don't think this hack to remove DC Offset is acceptable :thinking:
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// if (written == 0) std.mem.set(u8, stream[0..@intCast(usize, len)], 0x40);
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}
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};
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fn panic() noreturn {
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const str = @as(?[*:0]const u8, SDL.SDL_GetError()) orelse "unknown error";
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@panic(std.mem.sliceTo(str, 0));
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}
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@ -39,12 +39,12 @@ pub fn read(self: *Self, comptime T: type, r15: u32, addr: u32) T {
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}
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log.debug("Rejected read since r15=0x{X:0>8}", .{r15});
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return @truncate(T, self.uncheckedRead(T, self.addr_latch + 8));
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return @truncate(T, self.uncheckedRead(T, self.addr_latch));
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}
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pub fn dbgRead(self: *const Self, comptime T: type, r15: u32, addr: u32) T {
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if (r15 < Self.size) return self.uncheckedRead(T, addr);
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return @truncate(T, self.uncheckedRead(T, self.addr_latch + 8));
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return @truncate(T, self.uncheckedRead(T, self.addr_latch));
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}
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fn uncheckedRead(self: *const Self, comptime T: type, addr: u32) T {
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@ -1,10 +1,11 @@
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const std = @import("std");
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const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const DateTime = @import("datetime").datetime.Datetime;
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const Bit = @import("bitfield").Bit;
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const Bitfield = @import("bitfield").Bitfield;
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const Backup = @import("backup.zig").Backup;
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const Gpio = @import("gpio.zig").Gpio;
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const Allocator = std.mem.Allocator;
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const force_rtc = @import("../emu.zig").force_rtc;
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@ -239,463 +240,3 @@ test "OOB Access" {
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std.debug.assert(pak.get(4) == 0x02); // 0x0002
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std.debug.assert(pak.get(5) == 0x00);
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}
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/// GPIO Register Implementation
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const Gpio = struct {
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const This = @This();
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data: u4,
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direction: u4,
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cnt: u1,
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device: Device,
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const Device = struct {
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ptr: ?*anyopaque,
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kind: Kind, // TODO: Make comptime known?
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const Kind = enum { Rtc, None };
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fn step(self: *Device, value: u4) u4 {
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return switch (self.kind) {
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.Rtc => blk: {
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const clock = @ptrCast(*Clock, @alignCast(@alignOf(*Clock), self.ptr.?));
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break :blk clock.step(Clock.Data{ .raw = value });
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},
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.None => value,
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};
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}
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fn init(kind: Kind, ptr: ?*anyopaque) Device {
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return .{ .kind = kind, .ptr = ptr };
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}
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};
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const Register = enum {
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Data,
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Direction,
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Control,
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};
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fn init(allocator: Allocator, cpu: *Arm7tdmi, kind: Device.Kind) !*This {
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log.info("Device: {}", .{kind});
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const self = try allocator.create(This);
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self.* = .{
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.data = 0b0000,
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.direction = 0b1111, // TODO: What is GPIO DIrection set to by default?
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.cnt = 0b0,
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.device = switch (kind) {
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.Rtc => blk: {
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const clock = try allocator.create(Clock);
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clock.init(cpu, self);
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break :blk Device{ .kind = kind, .ptr = clock };
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},
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.None => Device{ .kind = kind, .ptr = null },
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},
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};
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return self;
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}
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fn deinit(self: *This, allocator: Allocator) void {
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switch (self.device.kind) {
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.Rtc => {
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allocator.destroy(@ptrCast(*Clock, @alignCast(@alignOf(*Clock), self.device.ptr.?)));
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},
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.None => {},
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}
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self.* = undefined;
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}
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fn write(self: *This, comptime reg: Register, value: if (reg == .Control) u1 else u4) void {
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switch (reg) {
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.Data => {
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const masked_value = value & self.direction;
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// The value which is actually stored in the GPIO register
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// might be modified by the device implementing the GPIO interface e.g. RTC reads
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self.data = self.device.step(masked_value);
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},
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.Direction => self.direction = value,
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.Control => self.cnt = value,
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}
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}
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fn read(self: *const This, comptime reg: Register) if (reg == .Control) u1 else u4 {
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if (self.cnt == 0) return 0;
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return switch (reg) {
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.Data => self.data & ~self.direction,
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.Direction => self.direction,
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.Control => self.cnt,
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};
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}
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};
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/// GBA Real Time Clock
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pub const Clock = struct {
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const This = @This();
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writer: Writer,
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reader: Reader,
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state: State,
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cnt: Control,
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year: u8,
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month: u5,
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day: u6,
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weekday: u3,
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hour: u6,
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minute: u7,
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second: u7,
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cpu: *Arm7tdmi,
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gpio: *const Gpio,
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const Register = enum {
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Control,
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DateTime,
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Time,
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};
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const State = union(enum) {
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Idle,
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Command,
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Write: Register,
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Read: Register,
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};
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const Reader = struct {
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i: u4,
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count: u8,
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/// Reads a bit from RTC registers. Which bit it reads is dependent on
|
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///
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/// 1. The RTC State Machine, whitch tells us which register we're accessing
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/// 2. A `count`, which keeps track of which byte is currently being read
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/// 3. An index, which keeps track of which bit of the byte determined by `count` is being read
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fn read(self: *Reader, clock: *const Clock, register: Register) u1 {
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const idx = @intCast(u3, self.i);
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defer self.i += 1;
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// FIXME: What do I do about the unused bits?
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return switch (register) {
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.Control => @truncate(u1, switch (self.count) {
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0 => clock.cnt.raw >> idx,
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else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 1 byte)", .{ self.count, register }),
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}),
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.DateTime => @truncate(u1, switch (self.count) {
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// Date
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0 => clock.year >> idx,
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1 => @as(u8, clock.month) >> idx,
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2 => @as(u8, clock.day) >> idx,
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3 => @as(u8, clock.weekday) >> idx,
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// Time
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4 => @as(u8, clock.hour) >> idx,
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5 => @as(u8, clock.minute) >> idx,
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6 => @as(u8, clock.second) >> idx,
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else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 7 bytes)", .{ self.count, register }),
|
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}),
|
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.Time => @truncate(u1, switch (self.count) {
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0 => @as(u8, clock.hour) >> idx,
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1 => @as(u8, clock.minute) >> idx,
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2 => @as(u8, clock.second) >> idx,
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else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 3 bytes)", .{ self.count, register }),
|
||||
}),
|
||||
};
|
||||
}
|
||||
|
||||
/// Is true when a Reader has read a u8's worth of bits
|
||||
fn finished(self: *const Reader) bool {
|
||||
return self.i >= 8;
|
||||
}
|
||||
|
||||
/// Resets the index used to shift bits out of RTC registers
|
||||
/// and `count`, which is used to keep track of which byte we're reading
|
||||
/// is incremeneted
|
||||
fn lap(self: *Reader) void {
|
||||
self.i = 0;
|
||||
self.count += 1;
|
||||
}
|
||||
|
||||
/// Resets the state of a `Reader` in preparation for a future
|
||||
/// read command
|
||||
fn reset(self: *Reader) void {
|
||||
self.i = 0;
|
||||
self.count = 0;
|
||||
}
|
||||
};
|
||||
|
||||
const Writer = struct {
|
||||
buf: u8,
|
||||
i: u4,
|
||||
|
||||
/// The Number of bytes written since last reset
|
||||
count: u8,
|
||||
|
||||
/// Append a bit to the internal bit buffer (aka an integer)
|
||||
fn push(self: *Writer, value: u1) void {
|
||||
const idx = @intCast(u3, self.i);
|
||||
self.buf = (self.buf & ~(@as(u8, 1) << idx)) | @as(u8, value) << idx;
|
||||
self.i += 1;
|
||||
}
|
||||
|
||||
/// Takes the contents of the internal buffer and writes it to an RTC register
|
||||
/// Where it writes to is dependent on:
|
||||
///
|
||||
/// 1. The RTC State Machine, whitch tells us which register we're accessing
|
||||
/// 2. A `count`, which keeps track of which byte is currently being read
|
||||
fn write(self: *const Writer, clock: *Clock, register: Register) void {
|
||||
// FIXME: What do do about unused bits?
|
||||
switch (register) {
|
||||
.Control => switch (self.count) {
|
||||
0 => clock.cnt.raw = (clock.cnt.raw & 0x80) | (self.buf & 0x7F), // Bit 7 read-only
|
||||
else => std.debug.panic("Tried to write to byte #{} of {} (hint: there's only 1 byte)", .{ self.count, register }),
|
||||
},
|
||||
.DateTime, .Time => log.debug("RTC: Ignoring {} write", .{register}),
|
||||
}
|
||||
}
|
||||
|
||||
/// Is true when 8 bits have been shifted into the internal buffer
|
||||
fn finished(self: *const Writer) bool {
|
||||
return self.i >= 8;
|
||||
}
|
||||
|
||||
/// Resets the internal buffer
|
||||
/// resets the index used to shift bits into the internal buffer
|
||||
/// increments `count` (which keeps track of byte offsets) by one
|
||||
fn lap(self: *Writer) void {
|
||||
self.buf = 0;
|
||||
self.i = 0;
|
||||
self.count += 1;
|
||||
}
|
||||
|
||||
/// Resets `Writer` to a clean state in preparation for a future write command
|
||||
fn reset(self: *Writer) void {
|
||||
self.buf = 0;
|
||||
self.i = 0;
|
||||
self.count = 0;
|
||||
}
|
||||
};
|
||||
|
||||
const Data = extern union {
|
||||
sck: Bit(u8, 0),
|
||||
sio: Bit(u8, 1),
|
||||
cs: Bit(u8, 2),
|
||||
raw: u8,
|
||||
};
|
||||
|
||||
const Control = extern union {
|
||||
/// Unknown, value should be preserved though
|
||||
unk: Bit(u8, 1),
|
||||
/// Per-minute IRQ
|
||||
/// If set, fire a Gamepak IRQ every 30s,
|
||||
irq: Bit(u8, 3),
|
||||
/// 12/24 Hour Bit
|
||||
/// If set, 12h mode
|
||||
/// If cleared, 24h mode
|
||||
mode: Bit(u8, 6),
|
||||
/// Read-Only, bit cleared on read
|
||||
/// If is set, means that there has been a failure / time has been lost
|
||||
off: Bit(u8, 7),
|
||||
raw: u8,
|
||||
};
|
||||
|
||||
fn init(ptr: *This, cpu: *Arm7tdmi, gpio: *const Gpio) void {
|
||||
ptr.* = .{
|
||||
.writer = .{ .buf = 0, .i = 0, .count = 0 },
|
||||
.reader = .{ .i = 0, .count = 0 },
|
||||
.state = .Idle,
|
||||
.cnt = .{ .raw = 0 },
|
||||
.year = 0x01,
|
||||
.month = 0x6,
|
||||
.day = 0x13,
|
||||
.weekday = 0x3,
|
||||
.hour = 0x23,
|
||||
.minute = 0x59,
|
||||
.second = 0x59,
|
||||
.cpu = cpu,
|
||||
.gpio = gpio, // Can't use Arm7tdmi ptr b/c not initialized yet
|
||||
};
|
||||
|
||||
cpu.sched.push(.RealTimeClock, 1 << 24); // Every Second
|
||||
}
|
||||
|
||||
pub fn updateTime(self: *This, late: u64) void {
|
||||
self.cpu.sched.push(.RealTimeClock, (1 << 24) -| late); // Reschedule
|
||||
|
||||
const now = DateTime.now();
|
||||
self.year = toBcd(u8, @intCast(u8, now.date.year - 2000));
|
||||
self.month = toBcd(u5, now.date.month);
|
||||
self.day = toBcd(u6, now.date.day);
|
||||
self.weekday = toBcd(u3, (now.date.weekday() + 1) % 7); // API is Monday = 0, Sunday = 6. We want Sunday = 0, Saturday = 6
|
||||
self.hour = toBcd(u6, now.time.hour);
|
||||
self.minute = toBcd(u7, now.time.minute);
|
||||
self.second = toBcd(u7, now.time.second);
|
||||
}
|
||||
|
||||
fn step(self: *This, value: Data) u4 {
|
||||
const cache: Data = .{ .raw = self.gpio.data };
|
||||
|
||||
return switch (self.state) {
|
||||
.Idle => blk: {
|
||||
// FIXME: Maybe check incoming value to see if SCK is also high?
|
||||
if (cache.sck.read()) {
|
||||
if (!cache.cs.read() and value.cs.read()) {
|
||||
log.debug("RTC: Entering Command Mode", .{});
|
||||
self.state = .Command;
|
||||
}
|
||||
}
|
||||
|
||||
break :blk @truncate(u4, value.raw);
|
||||
},
|
||||
.Command => blk: {
|
||||
if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
|
||||
|
||||
// If SCK rises, sample SIO
|
||||
if (!cache.sck.read() and value.sck.read()) {
|
||||
self.writer.push(@boolToInt(value.sio.read()));
|
||||
|
||||
if (self.writer.finished()) {
|
||||
self.state = self.processCommand(self.writer.buf);
|
||||
self.writer.reset();
|
||||
|
||||
log.debug("RTC: Switching to {}", .{self.state});
|
||||
}
|
||||
}
|
||||
|
||||
break :blk @truncate(u4, value.raw);
|
||||
},
|
||||
.Write => |register| blk: {
|
||||
if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
|
||||
|
||||
// If SCK rises, sample SIO
|
||||
if (!cache.sck.read() and value.sck.read()) {
|
||||
self.writer.push(@boolToInt(value.sio.read()));
|
||||
|
||||
const register_width: u32 = switch (register) {
|
||||
.Control => 1,
|
||||
.DateTime => 7,
|
||||
.Time => 3,
|
||||
};
|
||||
|
||||
if (self.writer.finished()) {
|
||||
self.writer.write(self, register); // write inner buffer to RTC register
|
||||
self.writer.lap();
|
||||
|
||||
if (self.writer.count == register_width) {
|
||||
self.writer.reset();
|
||||
self.state = .Idle;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
break :blk @truncate(u4, value.raw);
|
||||
},
|
||||
.Read => |register| blk: {
|
||||
if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
|
||||
var ret = value;
|
||||
|
||||
// if SCK rises, sample SIO
|
||||
if (!cache.sck.read() and value.sck.read()) {
|
||||
ret.sio.write(self.reader.read(self, register) == 0b1);
|
||||
|
||||
const register_width: u32 = switch (register) {
|
||||
.Control => 1,
|
||||
.DateTime => 7,
|
||||
.Time => 3,
|
||||
};
|
||||
|
||||
if (self.reader.finished()) {
|
||||
self.reader.lap();
|
||||
|
||||
if (self.reader.count == register_width) {
|
||||
self.reader.reset();
|
||||
self.state = .Idle;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
break :blk @truncate(u4, ret.raw);
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn reset(self: *This) void {
|
||||
// mGBA and NBA only zero the control register. We will do the same
|
||||
log.debug("RTC: Reset (control register was zeroed)", .{});
|
||||
|
||||
self.cnt.raw = 0;
|
||||
}
|
||||
|
||||
fn irq(self: *This) void {
|
||||
// TODO: Confirm that this is the right behaviour
|
||||
log.debug("RTC: Force GamePak IRQ", .{});
|
||||
|
||||
self.cpu.bus.io.irq.game_pak.set();
|
||||
self.cpu.handleInterrupt();
|
||||
}
|
||||
|
||||
fn processCommand(self: *This, raw_command: u8) State {
|
||||
const command = blk: {
|
||||
// If High Nybble is 0x6, no need to switch the endianness
|
||||
if (raw_command >> 4 & 0xF == 0x6) break :blk raw_command;
|
||||
|
||||
// Turns out reversing the order of bits isn't trivial at all
|
||||
// https://stackoverflow.com/questions/2602823/in-c-c-whats-the-simplest-way-to-reverse-the-order-of-bits-in-a-byte
|
||||
var ret = raw_command;
|
||||
ret = (ret & 0xF0) >> 4 | (ret & 0x0F) << 4;
|
||||
ret = (ret & 0xCC) >> 2 | (ret & 0x33) << 2;
|
||||
ret = (ret & 0xAA) >> 1 | (ret & 0x55) << 1;
|
||||
|
||||
break :blk ret;
|
||||
};
|
||||
log.debug("RTC: Handling Command 0x{X:0>2} [0b{b:0>8}]", .{ command, command });
|
||||
|
||||
const is_write = command & 1 == 0;
|
||||
const rtc_register = @truncate(u3, command >> 1 & 0x7);
|
||||
|
||||
if (is_write) {
|
||||
return switch (rtc_register) {
|
||||
0 => blk: {
|
||||
self.reset();
|
||||
break :blk .Idle;
|
||||
},
|
||||
1 => .{ .Write = .Control },
|
||||
2 => .{ .Write = .DateTime },
|
||||
3 => .{ .Write = .Time },
|
||||
6 => blk: {
|
||||
self.irq();
|
||||
break :blk .Idle;
|
||||
},
|
||||
4, 5, 7 => .Idle,
|
||||
};
|
||||
} else {
|
||||
return switch (rtc_register) {
|
||||
1 => .{ .Read = .Control },
|
||||
2 => .{ .Read = .DateTime },
|
||||
3 => .{ .Read = .Time },
|
||||
0, 4, 5, 6, 7 => .Idle, // Do Nothing
|
||||
};
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
fn toBcd(comptime T: type, value: u8) T {
|
||||
var input = value;
|
||||
var ret: u8 = 0;
|
||||
var shift: u3 = 0;
|
||||
|
||||
while (input > 0) {
|
||||
ret |= (input % 10) << (shift << 2);
|
||||
shift += 1;
|
||||
input /= 10;
|
||||
}
|
||||
|
||||
return @truncate(T, ret);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,11 +3,12 @@ const Allocator = std.mem.Allocator;
|
|||
const log = std.log.scoped(.Backup);
|
||||
|
||||
const escape = @import("../util.zig").escape;
|
||||
const asStringSlice = @import("../util.zig").asStringSlice;
|
||||
const span = @import("../util.zig").span;
|
||||
|
||||
const backup_kinds = [5]Needle{
|
||||
const backup_kinds = [6]Needle{
|
||||
.{ .str = "EEPROM_V", .kind = .Eeprom },
|
||||
.{ .str = "SRAM_V", .kind = .Sram },
|
||||
.{ .str = "SRAM_F_V", .kind = .Sram },
|
||||
.{ .str = "FLASH_V", .kind = .Flash },
|
||||
.{ .str = "FLASH512_V", .kind = .Flash },
|
||||
.{ .str = "FLASH1M_V", .kind = .Flash1M },
|
||||
|
|
@ -128,7 +129,7 @@ pub const Backup = struct {
|
|||
}
|
||||
|
||||
fn getSaveFilename(self: *const Self, allocator: Allocator) ![]const u8 {
|
||||
const title_str = asStringSlice(&escape(self.title));
|
||||
const title_str = span(&escape(self.title));
|
||||
const name = if (title_str.len != 0) title_str else "untitled";
|
||||
|
||||
return try std.mem.concat(allocator, u8, &[_][]const u8{ name, ".sav" });
|
||||
|
|
|
|||
|
|
@ -0,0 +1,463 @@
|
|||
const std = @import("std");
|
||||
const Bit = @import("bitfield").Bit;
|
||||
const Bitfield = @import("bitfield").Bitfield;
|
||||
const DateTime = @import("datetime").datetime.Datetime;
|
||||
|
||||
const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
|
||||
const Allocator = std.mem.Allocator;
|
||||
|
||||
/// GPIO Register Implementation
|
||||
pub const Gpio = struct {
|
||||
const Self = @This();
|
||||
const log = std.log.scoped(.Gpio);
|
||||
|
||||
data: u4,
|
||||
direction: u4,
|
||||
cnt: u1,
|
||||
|
||||
device: Device,
|
||||
|
||||
const Register = enum { Data, Direction, Control };
|
||||
|
||||
pub const Device = struct {
|
||||
ptr: ?*anyopaque,
|
||||
kind: Kind, // TODO: Make comptime known?
|
||||
|
||||
pub const Kind = enum { Rtc, None };
|
||||
|
||||
fn step(self: *Device, value: u4) u4 {
|
||||
return switch (self.kind) {
|
||||
.Rtc => blk: {
|
||||
const clock = @ptrCast(*Clock, @alignCast(@alignOf(*Clock), self.ptr.?));
|
||||
break :blk clock.step(Clock.Data{ .raw = value });
|
||||
},
|
||||
.None => value,
|
||||
};
|
||||
}
|
||||
|
||||
fn init(kind: Kind, ptr: ?*anyopaque) Device {
|
||||
return .{ .kind = kind, .ptr = ptr };
|
||||
}
|
||||
};
|
||||
|
||||
pub fn write(self: *Self, comptime reg: Register, value: if (reg == .Control) u1 else u4) void {
|
||||
switch (reg) {
|
||||
.Data => {
|
||||
const masked_value = value & self.direction;
|
||||
|
||||
// The value which is actually stored in the GPIO register
|
||||
// might be modified by the device implementing the GPIO interface e.g. RTC reads
|
||||
self.data = self.device.step(masked_value);
|
||||
},
|
||||
.Direction => self.direction = value,
|
||||
.Control => self.cnt = value,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn read(self: *const Self, comptime reg: Register) if (reg == .Control) u1 else u4 {
|
||||
if (self.cnt == 0) return 0;
|
||||
|
||||
return switch (reg) {
|
||||
.Data => self.data & ~self.direction,
|
||||
.Direction => self.direction,
|
||||
.Control => self.cnt,
|
||||
};
|
||||
}
|
||||
|
||||
pub fn init(allocator: Allocator, cpu: *Arm7tdmi, kind: Device.Kind) !*Self {
|
||||
log.info("Device: {}", .{kind});
|
||||
|
||||
const self = try allocator.create(Self);
|
||||
self.* = .{
|
||||
.data = 0b0000,
|
||||
.direction = 0b1111, // TODO: What is GPIO DIrection set to by default?
|
||||
.cnt = 0b0,
|
||||
|
||||
.device = switch (kind) {
|
||||
.Rtc => blk: {
|
||||
const clock = try allocator.create(Clock);
|
||||
clock.init(cpu, self);
|
||||
|
||||
break :blk Device{ .kind = kind, .ptr = clock };
|
||||
},
|
||||
.None => Device{ .kind = kind, .ptr = null },
|
||||
},
|
||||
};
|
||||
|
||||
return self;
|
||||
}
|
||||
|
||||
pub fn deinit(self: *Self, allocator: Allocator) void {
|
||||
switch (self.device.kind) {
|
||||
.Rtc => allocator.destroy(@ptrCast(*Clock, @alignCast(@alignOf(*Clock), self.device.ptr.?))),
|
||||
.None => {},
|
||||
}
|
||||
|
||||
self.* = undefined;
|
||||
}
|
||||
};
|
||||
|
||||
/// GBA Real Time Clock
|
||||
pub const Clock = struct {
|
||||
const Self = @This();
|
||||
const log = std.log.scoped(.Rtc);
|
||||
|
||||
writer: Writer,
|
||||
reader: Reader,
|
||||
state: State,
|
||||
cnt: Control,
|
||||
|
||||
year: u8,
|
||||
month: u5,
|
||||
day: u6,
|
||||
weekday: u3,
|
||||
hour: u6,
|
||||
minute: u7,
|
||||
second: u7,
|
||||
|
||||
cpu: *Arm7tdmi,
|
||||
gpio: *const Gpio,
|
||||
|
||||
const Register = enum {
|
||||
Control,
|
||||
DateTime,
|
||||
Time,
|
||||
};
|
||||
|
||||
const State = union(enum) {
|
||||
Idle,
|
||||
Command,
|
||||
Write: Register,
|
||||
Read: Register,
|
||||
};
|
||||
|
||||
const Reader = struct {
|
||||
i: u4,
|
||||
count: u8,
|
||||
|
||||
/// Reads a bit from RTC registers. Which bit it reads is dependent on
|
||||
///
|
||||
/// 1. The RTC State Machine, whitch tells us which register we're accessing
|
||||
/// 2. A `count`, which keeps track of which byte is currently being read
|
||||
/// 3. An index, which keeps track of which bit of the byte determined by `count` is being read
|
||||
fn read(self: *Reader, clock: *const Clock, register: Register) u1 {
|
||||
const idx = @intCast(u3, self.i);
|
||||
defer self.i += 1;
|
||||
|
||||
// FIXME: What do I do about the unused bits?
|
||||
return switch (register) {
|
||||
.Control => @truncate(u1, switch (self.count) {
|
||||
0 => clock.cnt.raw >> idx,
|
||||
else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 1 byte)", .{ self.count, register }),
|
||||
}),
|
||||
.DateTime => @truncate(u1, switch (self.count) {
|
||||
// Date
|
||||
0 => clock.year >> idx,
|
||||
1 => @as(u8, clock.month) >> idx,
|
||||
2 => @as(u8, clock.day) >> idx,
|
||||
3 => @as(u8, clock.weekday) >> idx,
|
||||
|
||||
// Time
|
||||
4 => @as(u8, clock.hour) >> idx,
|
||||
5 => @as(u8, clock.minute) >> idx,
|
||||
6 => @as(u8, clock.second) >> idx,
|
||||
else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 7 bytes)", .{ self.count, register }),
|
||||
}),
|
||||
.Time => @truncate(u1, switch (self.count) {
|
||||
0 => @as(u8, clock.hour) >> idx,
|
||||
1 => @as(u8, clock.minute) >> idx,
|
||||
2 => @as(u8, clock.second) >> idx,
|
||||
else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 3 bytes)", .{ self.count, register }),
|
||||
}),
|
||||
};
|
||||
}
|
||||
|
||||
/// Is true when a Reader has read a u8's worth of bits
|
||||
fn finished(self: *const Reader) bool {
|
||||
return self.i >= 8;
|
||||
}
|
||||
|
||||
/// Resets the index used to shift bits out of RTC registers
|
||||
/// and `count`, which is used to keep track of which byte we're reading
|
||||
/// is incremeneted
|
||||
fn lap(self: *Reader) void {
|
||||
self.i = 0;
|
||||
self.count += 1;
|
||||
}
|
||||
|
||||
/// Resets the state of a `Reader` in preparation for a future
|
||||
/// read command
|
||||
fn reset(self: *Reader) void {
|
||||
self.i = 0;
|
||||
self.count = 0;
|
||||
}
|
||||
};
|
||||
|
||||
const Writer = struct {
|
||||
buf: u8,
|
||||
i: u4,
|
||||
|
||||
/// The Number of bytes written since last reset
|
||||
count: u8,
|
||||
|
||||
/// Append a bit to the internal bit buffer (aka an integer)
|
||||
fn push(self: *Writer, value: u1) void {
|
||||
const idx = @intCast(u3, self.i);
|
||||
self.buf = (self.buf & ~(@as(u8, 1) << idx)) | @as(u8, value) << idx;
|
||||
self.i += 1;
|
||||
}
|
||||
|
||||
/// Takes the contents of the internal buffer and writes it to an RTC register
|
||||
/// Where it writes to is dependent on:
|
||||
///
|
||||
/// 1. The RTC State Machine, whitch tells us which register we're accessing
|
||||
/// 2. A `count`, which keeps track of which byte is currently being read
|
||||
fn write(self: *const Writer, clock: *Clock, register: Register) void {
|
||||
// FIXME: What do do about unused bits?
|
||||
switch (register) {
|
||||
.Control => switch (self.count) {
|
||||
0 => clock.cnt.raw = (clock.cnt.raw & 0x80) | (self.buf & 0x7F), // Bit 7 read-only
|
||||
else => std.debug.panic("Tried to write to byte #{} of {} (hint: there's only 1 byte)", .{ self.count, register }),
|
||||
},
|
||||
.DateTime, .Time => log.debug("Ignoring {} write", .{register}),
|
||||
}
|
||||
}
|
||||
|
||||
/// Is true when 8 bits have been shifted into the internal buffer
|
||||
fn finished(self: *const Writer) bool {
|
||||
return self.i >= 8;
|
||||
}
|
||||
|
||||
/// Resets the internal buffer
|
||||
/// resets the index used to shift bits into the internal buffer
|
||||
/// increments `count` (which keeps track of byte offsets) by one
|
||||
fn lap(self: *Writer) void {
|
||||
self.buf = 0;
|
||||
self.i = 0;
|
||||
self.count += 1;
|
||||
}
|
||||
|
||||
/// Resets `Writer` to a clean state in preparation for a future write command
|
||||
fn reset(self: *Writer) void {
|
||||
self.buf = 0;
|
||||
self.i = 0;
|
||||
self.count = 0;
|
||||
}
|
||||
};
|
||||
|
||||
const Data = extern union {
|
||||
sck: Bit(u8, 0),
|
||||
sio: Bit(u8, 1),
|
||||
cs: Bit(u8, 2),
|
||||
raw: u8,
|
||||
};
|
||||
|
||||
const Control = extern union {
|
||||
/// Unknown, value should be preserved though
|
||||
unk: Bit(u8, 1),
|
||||
/// Per-minute IRQ
|
||||
/// If set, fire a Gamepak IRQ every 30s,
|
||||
irq: Bit(u8, 3),
|
||||
/// 12/24 Hour Bit
|
||||
/// If set, 12h mode
|
||||
/// If cleared, 24h mode
|
||||
mode: Bit(u8, 6),
|
||||
/// Read-Only, bit cleared on read
|
||||
/// If is set, means that there has been a failure / time has been lost
|
||||
off: Bit(u8, 7),
|
||||
raw: u8,
|
||||
};
|
||||
|
||||
fn init(ptr: *Self, cpu: *Arm7tdmi, gpio: *const Gpio) void {
|
||||
ptr.* = .{
|
||||
.writer = .{ .buf = 0, .i = 0, .count = 0 },
|
||||
.reader = .{ .i = 0, .count = 0 },
|
||||
.state = .Idle,
|
||||
.cnt = .{ .raw = 0 },
|
||||
.year = 0x01,
|
||||
.month = 0x6,
|
||||
.day = 0x13,
|
||||
.weekday = 0x3,
|
||||
.hour = 0x23,
|
||||
.minute = 0x59,
|
||||
.second = 0x59,
|
||||
.cpu = cpu,
|
||||
.gpio = gpio, // Can't use Arm7tdmi ptr b/c not initialized yet
|
||||
};
|
||||
|
||||
cpu.sched.push(.RealTimeClock, 1 << 24); // Every Second
|
||||
}
|
||||
|
||||
pub fn updateTime(self: *Self, late: u64) void {
|
||||
self.cpu.sched.push(.RealTimeClock, (1 << 24) -| late); // Reschedule
|
||||
|
||||
const now = DateTime.now();
|
||||
self.year = bcd(u8, @intCast(u8, now.date.year - 2000));
|
||||
self.month = bcd(u5, now.date.month);
|
||||
self.day = bcd(u6, now.date.day);
|
||||
self.weekday = bcd(u3, (now.date.weekday() + 1) % 7); // API is Monday = 0, Sunday = 6. We want Sunday = 0, Saturday = 6
|
||||
self.hour = bcd(u6, now.time.hour);
|
||||
self.minute = bcd(u7, now.time.minute);
|
||||
self.second = bcd(u7, now.time.second);
|
||||
}
|
||||
|
||||
fn step(self: *Self, value: Data) u4 {
|
||||
const cache: Data = .{ .raw = self.gpio.data };
|
||||
|
||||
return switch (self.state) {
|
||||
.Idle => blk: {
|
||||
// FIXME: Maybe check incoming value to see if SCK is also high?
|
||||
if (cache.sck.read()) {
|
||||
if (!cache.cs.read() and value.cs.read()) {
|
||||
log.debug("Entering Command Mode", .{});
|
||||
self.state = .Command;
|
||||
}
|
||||
}
|
||||
|
||||
break :blk @truncate(u4, value.raw);
|
||||
},
|
||||
.Command => blk: {
|
||||
if (!value.cs.read()) log.err("Expected CS to be set during {}, however CS was cleared", .{self.state});
|
||||
|
||||
// If SCK rises, sample SIO
|
||||
if (!cache.sck.read() and value.sck.read()) {
|
||||
self.writer.push(@boolToInt(value.sio.read()));
|
||||
|
||||
if (self.writer.finished()) {
|
||||
self.state = self.processCommand(self.writer.buf);
|
||||
self.writer.reset();
|
||||
|
||||
log.debug("Switching to {}", .{self.state});
|
||||
}
|
||||
}
|
||||
|
||||
break :blk @truncate(u4, value.raw);
|
||||
},
|
||||
.Write => |register| blk: {
|
||||
if (!value.cs.read()) log.err("Expected CS to be set during {}, however CS was cleared", .{self.state});
|
||||
|
||||
// If SCK rises, sample SIO
|
||||
if (!cache.sck.read() and value.sck.read()) {
|
||||
self.writer.push(@boolToInt(value.sio.read()));
|
||||
|
||||
const register_width: u32 = switch (register) {
|
||||
.Control => 1,
|
||||
.DateTime => 7,
|
||||
.Time => 3,
|
||||
};
|
||||
|
||||
if (self.writer.finished()) {
|
||||
self.writer.write(self, register); // write inner buffer to RTC register
|
||||
self.writer.lap();
|
||||
|
||||
if (self.writer.count == register_width) {
|
||||
self.writer.reset();
|
||||
self.state = .Idle;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
break :blk @truncate(u4, value.raw);
|
||||
},
|
||||
.Read => |register| blk: {
|
||||
if (!value.cs.read()) log.err("Expected CS to be set during {}, however CS was cleared", .{self.state});
|
||||
var ret = value;
|
||||
|
||||
// if SCK rises, sample SIO
|
||||
if (!cache.sck.read() and value.sck.read()) {
|
||||
ret.sio.write(self.reader.read(self, register) == 0b1);
|
||||
|
||||
const register_width: u32 = switch (register) {
|
||||
.Control => 1,
|
||||
.DateTime => 7,
|
||||
.Time => 3,
|
||||
};
|
||||
|
||||
if (self.reader.finished()) {
|
||||
self.reader.lap();
|
||||
|
||||
if (self.reader.count == register_width) {
|
||||
self.reader.reset();
|
||||
self.state = .Idle;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
break :blk @truncate(u4, ret.raw);
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn reset(self: *Self) void {
|
||||
// mGBA and NBA only zero the control register. We will do the same
|
||||
log.debug("Reset (control register was zeroed)", .{});
|
||||
|
||||
self.cnt.raw = 0;
|
||||
}
|
||||
|
||||
fn irq(self: *Self) void {
|
||||
// TODO: Confirm that this is the right behaviour
|
||||
log.debug("Force GamePak IRQ", .{});
|
||||
|
||||
self.cpu.bus.io.irq.game_pak.set();
|
||||
self.cpu.handleInterrupt();
|
||||
}
|
||||
|
||||
fn processCommand(self: *Self, raw_command: u8) State {
|
||||
const command = blk: {
|
||||
// If High Nybble is 0x6, no need to switch the endianness
|
||||
if (raw_command >> 4 & 0xF == 0x6) break :blk raw_command;
|
||||
|
||||
// Turns out reversing the order of bits isn't trivial at all
|
||||
// https://stackoverflow.com/questions/2602823/in-c-c-whats-the-simplest-way-to-reverse-the-order-of-bits-in-a-byte
|
||||
var ret = raw_command;
|
||||
ret = (ret & 0xF0) >> 4 | (ret & 0x0F) << 4;
|
||||
ret = (ret & 0xCC) >> 2 | (ret & 0x33) << 2;
|
||||
ret = (ret & 0xAA) >> 1 | (ret & 0x55) << 1;
|
||||
|
||||
break :blk ret;
|
||||
};
|
||||
log.debug("Handling Command 0x{X:0>2} [0b{b:0>8}]", .{ command, command });
|
||||
|
||||
const is_write = command & 1 == 0;
|
||||
const rtc_register = @truncate(u3, command >> 1 & 0x7);
|
||||
|
||||
if (is_write) {
|
||||
return switch (rtc_register) {
|
||||
0 => blk: {
|
||||
self.reset();
|
||||
break :blk .Idle;
|
||||
},
|
||||
1 => .{ .Write = .Control },
|
||||
2 => .{ .Write = .DateTime },
|
||||
3 => .{ .Write = .Time },
|
||||
6 => blk: {
|
||||
self.irq();
|
||||
break :blk .Idle;
|
||||
},
|
||||
4, 5, 7 => .Idle,
|
||||
};
|
||||
} else {
|
||||
return switch (rtc_register) {
|
||||
1 => .{ .Read = .Control },
|
||||
2 => .{ .Read = .DateTime },
|
||||
3 => .{ .Read = .Time },
|
||||
0, 4, 5, 6, 7 => .Idle, // Do Nothing
|
||||
};
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
fn bcd(comptime T: type, value: u8) T {
|
||||
var input = value;
|
||||
var ret: u8 = 0;
|
||||
var shift: u3 = 0;
|
||||
|
||||
while (input > 0) {
|
||||
ret |= (input % 10) << (shift << 2);
|
||||
shift += 1;
|
||||
input /= 10;
|
||||
}
|
||||
|
||||
return @truncate(T, ret);
|
||||
}
|
||||
127
src/core/cpu.zig
127
src/core/cpu.zig
|
|
@ -243,6 +243,7 @@ pub const Arm7tdmi = struct {
|
|||
const Self = @This();
|
||||
|
||||
r: [16]u32,
|
||||
pipe: Pipline,
|
||||
sched: *Scheduler,
|
||||
bus: *Bus,
|
||||
cpsr: PSR,
|
||||
|
|
@ -263,6 +264,7 @@ pub const Arm7tdmi = struct {
|
|||
pub fn init(sched: *Scheduler, bus: *Bus, log_file: ?std.fs.File) Self {
|
||||
return Self{
|
||||
.r = [_]u32{0x00} ** 16,
|
||||
.pipe = Pipline.init(),
|
||||
.sched = sched,
|
||||
.bus = bus,
|
||||
.cpsr = .{ .raw = 0x0000_001F },
|
||||
|
|
@ -322,8 +324,21 @@ pub const Arm7tdmi = struct {
|
|||
return self.bus.io.haltcnt == .Halt;
|
||||
}
|
||||
|
||||
pub fn setCpsrNoFlush(self: *Self, value: u32) void {
|
||||
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
|
||||
self.cpsr.raw = value;
|
||||
}
|
||||
|
||||
pub fn setCpsr(self: *Self, value: u32) void {
|
||||
if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
|
||||
|
||||
const new: PSR = .{ .raw = value };
|
||||
if (self.cpsr.t.read() != new.t.read()) {
|
||||
// If THUMB to ARM or ARM to THUMB, flush pipeline
|
||||
self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
|
||||
if (new.t.read()) self.pipe.reload(u16, self) else self.pipe.reload(u32, self);
|
||||
}
|
||||
|
||||
self.cpsr.raw = value;
|
||||
}
|
||||
|
||||
|
|
@ -414,31 +429,35 @@ pub const Arm7tdmi = struct {
|
|||
pub fn fastBoot(self: *Self) void {
|
||||
self.r = std.mem.zeroes([16]u32);
|
||||
|
||||
self.r[0] = 0x08000000;
|
||||
self.r[1] = 0x000000EA;
|
||||
// self.r[0] = 0x08000000;
|
||||
// self.r[1] = 0x000000EA;
|
||||
self.r[13] = 0x0300_7F00;
|
||||
self.r[15] = 0x0800_0000;
|
||||
|
||||
self.banked_r[bankedIdx(.Irq, .R13)] = 0x0300_7FA0;
|
||||
self.banked_r[bankedIdx(.Supervisor, .R13)] = 0x0300_7FE0;
|
||||
|
||||
self.cpsr.raw = 0x6000001F;
|
||||
// self.cpsr.raw = 0x6000001F;
|
||||
self.cpsr.raw = 0x0000_001F;
|
||||
}
|
||||
|
||||
pub fn step(self: *Self) void {
|
||||
if (self.cpsr.t.read()) {
|
||||
const opcode = self.fetch(u16);
|
||||
if (self.cpsr.t.read()) blk: {
|
||||
const opcode = @truncate(u16, self.pipe.step(self, u16) orelse break :blk);
|
||||
if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
|
||||
|
||||
thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
|
||||
} else {
|
||||
const opcode = self.fetch(u32);
|
||||
} else blk: {
|
||||
const opcode = self.pipe.step(self, u32) orelse break :blk;
|
||||
if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
|
||||
|
||||
if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
|
||||
arm.lut[arm.idx(opcode)](self, self.bus, opcode);
|
||||
}
|
||||
}
|
||||
|
||||
if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
|
||||
self.pipe.flushed = false;
|
||||
}
|
||||
|
||||
pub fn stepDmaTransfer(self: *Self) bool {
|
||||
|
|
@ -473,27 +492,26 @@ pub const Arm7tdmi = struct {
|
|||
pub fn handleInterrupt(self: *Self) void {
|
||||
const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
|
||||
|
||||
if (should_handle != 0) {
|
||||
// Return if IME is disabled, CPSR I is set or there is nothing to handle
|
||||
if (!self.bus.io.ime or self.cpsr.i.read() or should_handle == 0) return;
|
||||
|
||||
// If pipeline isn't full, return but reschedule the handling of the event
|
||||
if (!self.pipe.isFull()) return;
|
||||
|
||||
// log.debug("Handling Interrupt!", .{});
|
||||
self.bus.io.haltcnt = .Execute;
|
||||
// log.debug("An Interrupt was Fired!", .{});
|
||||
|
||||
// Either IME is not true or I in CPSR is true
|
||||
// Don't handle interrupts
|
||||
if (!self.bus.io.ime or self.cpsr.i.read()) return;
|
||||
// log.debug("An interrupt was Handled!", .{});
|
||||
|
||||
// retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode
|
||||
const r15 = self.r[15] + 4;
|
||||
const cpsr = self.cpsr.raw;
|
||||
const ret_addr = self.r[15] - if (self.cpsr.t.read()) 2 else @as(u32, 4);
|
||||
const new_spsr = self.cpsr.raw;
|
||||
|
||||
self.changeMode(.Irq);
|
||||
self.cpsr.t.write(false);
|
||||
self.cpsr.i.write(true);
|
||||
|
||||
self.r[14] = r15;
|
||||
self.spsr.raw = cpsr;
|
||||
self.r[15] = 0x000_0018;
|
||||
}
|
||||
self.r[14] = ret_addr;
|
||||
self.spsr.raw = new_spsr;
|
||||
self.r[15] = 0x0000_0018;
|
||||
self.pipe.reload(u32, self);
|
||||
}
|
||||
|
||||
inline fn fetch(self: *Self, comptime T: type) T {
|
||||
|
|
@ -507,8 +525,12 @@ pub const Arm7tdmi = struct {
|
|||
return self.bus.read(T, self.r[15]);
|
||||
}
|
||||
|
||||
pub fn fakePC(self: *const Self) u32 {
|
||||
return self.r[15] + 4;
|
||||
fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
|
||||
if (self.binary_log) {
|
||||
self.skyLog(file) catch unreachable;
|
||||
} else {
|
||||
self.mgbaLog(file, opcode) catch unreachable;
|
||||
}
|
||||
}
|
||||
|
||||
pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
|
||||
|
|
@ -525,6 +547,8 @@ pub const Arm7tdmi = struct {
|
|||
std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
|
||||
prettyPrintPsr(&self.spsr);
|
||||
|
||||
std.debug.print("pipeline: {??X:0>8}\n", .{self.pipe.stage});
|
||||
|
||||
if (self.cpsr.t.read()) {
|
||||
const opcode = self.bus.dbgRead(u16, self.r[15] - 4);
|
||||
const id = thumb.idx(opcode);
|
||||
|
|
@ -588,7 +612,7 @@ pub const Arm7tdmi = struct {
|
|||
const r12 = self.r[12];
|
||||
const r13 = self.r[13];
|
||||
const r14 = self.r[14];
|
||||
const r15 = self.r[15];
|
||||
const r15 = self.r[15] -| if (self.cpsr.t.read()) 2 else @as(u32, 4);
|
||||
|
||||
const c_psr = self.cpsr.raw;
|
||||
|
||||
|
|
@ -596,7 +620,7 @@ pub const Arm7tdmi = struct {
|
|||
if (self.cpsr.t.read()) {
|
||||
if (opcode >> 11 == 0x1E) {
|
||||
// Instruction 1 of a BL Opcode, print in ARM mode
|
||||
const other_half = self.bus.dbgRead(u16, self.r[15]);
|
||||
const other_half = self.bus.debugRead(u16, self.r[15] - 2);
|
||||
const bl_opcode = @as(u32, opcode) << 16 | other_half;
|
||||
|
||||
log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
|
||||
|
|
@ -632,6 +656,59 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
|
|||
};
|
||||
}
|
||||
|
||||
const Pipline = struct {
|
||||
const Self = @This();
|
||||
stage: [2]?u32,
|
||||
flushed: bool,
|
||||
|
||||
fn init() Self {
|
||||
return .{
|
||||
.stage = [_]?u32{null} ** 2,
|
||||
.flushed = false,
|
||||
};
|
||||
}
|
||||
|
||||
pub fn flush(self: *Self) void {
|
||||
for (self.stage) |*opcode| opcode.* = null;
|
||||
self.flushed = true;
|
||||
|
||||
// Note: If using this, add
|
||||
// if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
|
||||
// to the end of Arm7tdmi.step
|
||||
}
|
||||
|
||||
pub fn isFull(self: *const Self) bool {
|
||||
return self.stage[0] != null and self.stage[1] != null;
|
||||
}
|
||||
|
||||
pub fn step(self: *Self, cpu: *Arm7tdmi, comptime T: type) ?u32 {
|
||||
comptime std.debug.assert(T == u32 or T == u16);
|
||||
|
||||
// FIXME: https://github.com/ziglang/zig/issues/12642
|
||||
const opcode = self.stage[0..1][0];
|
||||
|
||||
self.stage[0] = self.stage[1];
|
||||
self.stage[1] = cpu.bus.read(T, cpu.r[15]);
|
||||
|
||||
return opcode;
|
||||
}
|
||||
|
||||
pub fn reload(self: *Self, comptime T: type, cpu: *Arm7tdmi) void {
|
||||
comptime std.debug.assert(T == u32 or T == u16);
|
||||
|
||||
// Sometimes, the pipeline can be reloaded twice in the same instruction
|
||||
// This can happen if:
|
||||
// 1. R15 is written to
|
||||
// 2. The CPSR is written to (and T changes), so R15 is written to again
|
||||
|
||||
self.stage[0] = cpu.bus.read(T, cpu.r[15]);
|
||||
self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
|
||||
|
||||
cpu.r[15] += if (T == u32) 8 else @as(u32, 4);
|
||||
self.flushed = true;
|
||||
}
|
||||
};
|
||||
|
||||
pub const PSR = extern union {
|
||||
mode: Bitfield(u32, 0, 5),
|
||||
t: Bit(u32, 5),
|
||||
|
|
|
|||
|
|
@ -55,8 +55,10 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
|
|||
|
||||
if (L) {
|
||||
cpu.r[15] = bus.read(u32, und_addr);
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
} else {
|
||||
bus.write(u32, und_addr, cpu.r[15] + 8);
|
||||
// FIXME: Should r15 on write be +12 ahead?
|
||||
bus.write(u32, und_addr, cpu.r[15] + 4);
|
||||
}
|
||||
|
||||
cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
|
||||
|
|
@ -86,17 +88,23 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
|
|||
cpu.setUserModeRegister(i, bus.read(u32, address));
|
||||
} else {
|
||||
const value = bus.read(u32, address);
|
||||
cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
|
||||
if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
|
||||
cpu.r[i] = value;
|
||||
if (i == 0xF) {
|
||||
cpu.r[i] &= ~@as(u32, 3); // Align r15
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
|
||||
if (S) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (S) {
|
||||
// Always Transfer User mode Registers
|
||||
// This happens regardless if r15 is in the list
|
||||
const value = cpu.getUserModeRegister(i);
|
||||
bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
|
||||
bus.write(u32, address, value + if (i == 0xF) 4 else @as(u32, 0)); // PC is already 8 ahead to make 12
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
|
||||
bus.write(u32, address, cpu.r[i] + if (i == 0xF) 4 else @as(u32, 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,14 +9,20 @@ const sext = @import("../../util.zig").sext;
|
|||
pub fn branch(comptime L: bool) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
if (L) cpu.r[14] = cpu.r[15];
|
||||
cpu.r[15] = cpu.fakePC() +% (sext(u32, u24, opcode) << 2);
|
||||
if (L) cpu.r[14] = cpu.r[15] - 4;
|
||||
|
||||
cpu.r[15] +%= sext(u32, u24, opcode) << 2;
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
const rn = opcode & 0xF;
|
||||
cpu.cpsr.t.write(cpu.r[rn] & 1 == 1);
|
||||
cpu.r[15] = cpu.r[rn] & 0xFFFF_FFFE;
|
||||
|
||||
const thumb = cpu.r[rn] & 1 == 1;
|
||||
cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
|
||||
|
||||
cpu.cpsr.t.write(thumb);
|
||||
if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ const InstrFn = @import("../../cpu.zig").arm.InstrFn;
|
|||
const rotateRight = @import("../barrel_shifter.zig").rotateRight;
|
||||
const execute = @import("../barrel_shifter.zig").execute;
|
||||
|
||||
pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
|
||||
pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
const rd = @truncate(u4, opcode >> 12 & 0xF);
|
||||
|
|
@ -13,124 +13,276 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
|
|||
const old_carry = @boolToInt(cpu.cpsr.c.read());
|
||||
|
||||
// If certain conditions are met, PC is 12 ahead instead of 8
|
||||
// TODO: Why these conditions?
|
||||
if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
|
||||
const op1 = cpu.r[rn];
|
||||
|
||||
const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn];
|
||||
|
||||
var op2: u32 = undefined;
|
||||
if (I) {
|
||||
const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
|
||||
op2 = rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
|
||||
} else {
|
||||
op2 = execute(S, cpu, opcode);
|
||||
}
|
||||
const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
|
||||
|
||||
// Undo special condition from above
|
||||
if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
|
||||
|
||||
switch (instrKind) {
|
||||
0x0 => {
|
||||
// AND
|
||||
const result = op1 & op2;
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
},
|
||||
0x1 => {
|
||||
// EOR
|
||||
const result = op1 ^ op2;
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
},
|
||||
0x2 => {
|
||||
// SUB
|
||||
cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
|
||||
},
|
||||
0x3 => {
|
||||
// RSB
|
||||
cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
|
||||
},
|
||||
0x4 => {
|
||||
// ADD
|
||||
cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
|
||||
},
|
||||
0x5 => {
|
||||
// ADC
|
||||
cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
|
||||
},
|
||||
0x6 => {
|
||||
// SBC
|
||||
cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
|
||||
},
|
||||
0x7 => {
|
||||
// RSC
|
||||
cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
|
||||
},
|
||||
var result: u32 = undefined;
|
||||
var didOverflow: bool = undefined;
|
||||
|
||||
// Perform Data Processing Logic
|
||||
switch (kind) {
|
||||
0x0 => result = op1 & op2, // AND
|
||||
0x1 => result = op1 ^ op2, // EOR
|
||||
0x2 => result = op1 -% op2, // SUB
|
||||
0x3 => result = op2 -% op1, // RSB
|
||||
0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
|
||||
0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
|
||||
0x6 => result = newSbc(op1, op2, old_carry), // SBC
|
||||
0x7 => result = newSbc(op2, op1, old_carry), // RSC
|
||||
0x8 => {
|
||||
// TST
|
||||
if (rd == 0xF) {
|
||||
undefinedTestBehaviour(cpu);
|
||||
return;
|
||||
}
|
||||
if (rd == 0xF)
|
||||
return undefinedTestBehaviour(cpu);
|
||||
|
||||
const result = op1 & op2;
|
||||
setTestOpFlags(S, cpu, opcode, result);
|
||||
result = op1 & op2;
|
||||
},
|
||||
0x9 => {
|
||||
// TEQ
|
||||
if (rd == 0xF) {
|
||||
undefinedTestBehaviour(cpu);
|
||||
return;
|
||||
}
|
||||
if (rd == 0xF)
|
||||
return undefinedTestBehaviour(cpu);
|
||||
|
||||
const result = op1 ^ op2;
|
||||
setTestOpFlags(S, cpu, opcode, result);
|
||||
result = op1 ^ op2;
|
||||
},
|
||||
0xA => {
|
||||
// CMP
|
||||
if (rd == 0xF) {
|
||||
undefinedTestBehaviour(cpu);
|
||||
return;
|
||||
}
|
||||
if (rd == 0xF)
|
||||
return undefinedTestBehaviour(cpu);
|
||||
|
||||
cmp(cpu, op1, op2);
|
||||
result = op1 -% op2;
|
||||
},
|
||||
0xB => {
|
||||
// CMN
|
||||
if (rd == 0xF) {
|
||||
undefinedTestBehaviour(cpu);
|
||||
return;
|
||||
if (rd == 0xF)
|
||||
return undefinedTestBehaviour(cpu);
|
||||
|
||||
didOverflow = @addWithOverflow(u32, op1, op2, &result);
|
||||
},
|
||||
0xC => result = op1 | op2, // ORR
|
||||
0xD => result = op2, // MOV
|
||||
0xE => result = op1 & ~op2, // BIC
|
||||
0xF => result = ~op2, // MVN
|
||||
}
|
||||
|
||||
cmn(cpu, op1, op2);
|
||||
},
|
||||
0xC => {
|
||||
// ORR
|
||||
const result = op1 | op2;
|
||||
// Write to Destination Register
|
||||
switch (kind) {
|
||||
0x8, 0x9, 0xA, 0xB => {}, // Test Operations
|
||||
else => {
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
if (rd == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
},
|
||||
0xD => {
|
||||
// MOV
|
||||
cpu.r[rd] = op2;
|
||||
setArmLogicOpFlags(S, cpu, rd, op2);
|
||||
}
|
||||
|
||||
// Write Flags
|
||||
switch (kind) {
|
||||
0x0, 0x1, 0xC, 0xD, 0xE, 0xF => {
|
||||
// Logic Operation Flags
|
||||
if (S) {
|
||||
if (rd == 0xF) {
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
} else {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
// C set by Barrel Shifter, V is unaffected
|
||||
}
|
||||
}
|
||||
},
|
||||
0xE => {
|
||||
// BIC
|
||||
const result = op1 & ~op2;
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
0x2, 0x3 => {
|
||||
// SUB, RSB Flags
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
if (kind == 0x2) {
|
||||
// SUB specific
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else {
|
||||
// RSB Specific
|
||||
cpu.cpsr.c.write(op1 <= op2);
|
||||
cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
},
|
||||
0xF => {
|
||||
// MVN
|
||||
const result = ~op2;
|
||||
cpu.r[rd] = result;
|
||||
setArmLogicOpFlags(S, cpu, rd, result);
|
||||
0x4, 0x5 => {
|
||||
// ADD, ADC Flags
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
cpu.cpsr.c.write(didOverflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
|
||||
if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
},
|
||||
0x6, 0x7 => {
|
||||
// SBC, RSC Flags
|
||||
if (S) {
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
if (kind == 0x6) {
|
||||
// SBC specific
|
||||
const subtrahend = @as(u64, op2) -% old_carry +% 1;
|
||||
cpu.cpsr.c.write(subtrahend <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else {
|
||||
// RSC Specific
|
||||
const subtrahend = @as(u64, op1) -% old_carry +% 1;
|
||||
cpu.cpsr.c.write(subtrahend <= op2);
|
||||
cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
|
||||
}
|
||||
|
||||
if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
|
||||
}
|
||||
},
|
||||
0x8, 0x9, 0xA, 0xB => {
|
||||
// Test Operation Flags
|
||||
cpu.cpsr.n.write(result >> 31 & 1 == 1);
|
||||
cpu.cpsr.z.write(result == 0);
|
||||
|
||||
if (kind == 0xA) {
|
||||
// CMP specific
|
||||
cpu.cpsr.c.write(op2 <= op1);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else if (kind == 0xB) {
|
||||
// CMN specific
|
||||
cpu.cpsr.c.write(didOverflow);
|
||||
cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
|
||||
} else {
|
||||
// TEST, TEQ specific
|
||||
// Barrel Shifter should always calc CPSR C in TST
|
||||
if (!S) _ = execute(true, cpu, opcode);
|
||||
}
|
||||
},
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
||||
// pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
|
||||
// return struct {
|
||||
// fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||
// const rd = @truncate(u4, opcode >> 12 & 0xF);
|
||||
// const rn = opcode >> 16 & 0xF;
|
||||
// const old_carry = @boolToInt(cpu.cpsr.c.read());
|
||||
|
||||
// // If certain conditions are met, PC is 12 ahead instead of 8
|
||||
// // TODO: What are these conditions? I can't remember
|
||||
// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
|
||||
// const op1 = cpu.r[rn];
|
||||
|
||||
// const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
|
||||
// const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
|
||||
|
||||
// // Undo special condition from above
|
||||
// if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
|
||||
|
||||
// switch (instrKind) {
|
||||
// 0x0 => {
|
||||
// // AND
|
||||
// const result = op1 & op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0x1 => {
|
||||
// // EOR
|
||||
// const result = op1 ^ op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0x2 => {
|
||||
// // SUB
|
||||
// cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
|
||||
// },
|
||||
// 0x3 => {
|
||||
// // RSB
|
||||
// cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
|
||||
// },
|
||||
// 0x4 => {
|
||||
// // ADD
|
||||
// cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
|
||||
// },
|
||||
// 0x5 => {
|
||||
// // ADC
|
||||
// cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
|
||||
// },
|
||||
// 0x6 => {
|
||||
// // SBC
|
||||
// cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
|
||||
// },
|
||||
// 0x7 => {
|
||||
// // RSC
|
||||
// cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
|
||||
// },
|
||||
// 0x8 => {
|
||||
// // TST
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// const result = op1 & op2;
|
||||
// setTestOpFlags(S, cpu, opcode, result);
|
||||
// },
|
||||
// 0x9 => {
|
||||
// // TEQ
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// const result = op1 ^ op2;
|
||||
// setTestOpFlags(S, cpu, opcode, result);
|
||||
// },
|
||||
// 0xA => {
|
||||
// // CMP
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// cmp(cpu, op1, op2);
|
||||
// },
|
||||
// 0xB => {
|
||||
// // CMN
|
||||
// if (rd == 0xF)
|
||||
// return undefinedTestBehaviour(cpu);
|
||||
|
||||
// cmn(cpu, op1, op2);
|
||||
// },
|
||||
// 0xC => {
|
||||
// // ORR
|
||||
// const result = op1 | op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0xD => {
|
||||
// // MOV
|
||||
// cpu.r[rd] = op2;
|
||||
// setArmLogicOpFlags(S, cpu, rd, op2);
|
||||
// },
|
||||
// 0xE => {
|
||||
// // BIC
|
||||
// const result = op1 & ~op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// 0xF => {
|
||||
// // MVN
|
||||
// const result = ~op2;
|
||||
// cpu.r[rd] = result;
|
||||
// setArmLogicOpFlags(S, cpu, rd, result);
|
||||
// },
|
||||
// }
|
||||
|
||||
// if (rd == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
// }
|
||||
// }.inner;
|
||||
// }
|
||||
|
||||
fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var result: u32 = undefined;
|
||||
if (S and rd == 0xF) {
|
||||
|
|
@ -143,6 +295,14 @@ fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
|
|||
return result;
|
||||
}
|
||||
|
||||
fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
|
||||
// TODO: Make your own version (thanks peach.bot)
|
||||
const subtrahend = @as(u64, right) -% old_carry +% 1;
|
||||
const ret = @truncate(u32, left -% subtrahend);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
|
||||
// TODO: Make your own version (thanks peach.bot)
|
||||
const subtrahend = @as(u64, right) -% old_carry +% 1;
|
||||
|
|
@ -195,6 +355,12 @@ fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
|
|||
return result;
|
||||
}
|
||||
|
||||
fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
|
||||
var ret: u32 = undefined;
|
||||
didOverflow.* = @addWithOverflow(u32, left, right, &ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
|
||||
var result: u32 = undefined;
|
||||
const didOverflow = @addWithOverflow(u32, left, right, &result);
|
||||
|
|
@ -221,6 +387,15 @@ fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
|
|||
return result;
|
||||
}
|
||||
|
||||
fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var ret: u32 = undefined;
|
||||
const did = @addWithOverflow(u32, left, right, &ret);
|
||||
const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
|
||||
|
||||
didOverflow.* = did or overflow;
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
|
||||
var result: u32 = undefined;
|
||||
const did = @addWithOverflow(u32, left, right, &result);
|
||||
|
|
@ -280,5 +455,5 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
|
|||
|
||||
fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
|
||||
@setCold(true);
|
||||
cpu.setCpsr(cpu.spsr.raw);
|
||||
cpu.setCpsrNoFlush(cpu.spsr.raw);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,20 +15,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
|
|||
const rm = opcode & 0xF;
|
||||
const imm_offset_high = opcode >> 8 & 0xF;
|
||||
|
||||
var base: u32 = undefined;
|
||||
if (rn == 0xF) {
|
||||
base = cpu.fakePC();
|
||||
if (!L) base += 4;
|
||||
} else {
|
||||
base = cpu.r[rn];
|
||||
}
|
||||
|
||||
var offset: u32 = undefined;
|
||||
if (I) {
|
||||
offset = imm_offset_high << 4 | rm;
|
||||
} else {
|
||||
offset = cpu.r[rm];
|
||||
}
|
||||
const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
|
||||
const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
|
||||
|
||||
const modified_base = if (U) base +% offset else base -% offset;
|
||||
var address = if (P) modified_base else base;
|
||||
|
|
|
|||
|
|
@ -14,13 +14,8 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
|
|||
const rn = opcode >> 16 & 0xF;
|
||||
const rd = opcode >> 12 & 0xF;
|
||||
|
||||
var base: u32 = undefined;
|
||||
if (rn == 0xF) {
|
||||
base = cpu.fakePC();
|
||||
if (!L) base += 4; // Offset of 12
|
||||
} else {
|
||||
base = cpu.r[rn];
|
||||
}
|
||||
// rn is r15 and L is not set, the PC is 12 ahead
|
||||
const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
|
||||
|
||||
const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
|
||||
|
||||
|
|
@ -40,18 +35,26 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
|
|||
} else {
|
||||
if (B) {
|
||||
// STRB
|
||||
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
|
||||
const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
|
||||
bus.write(u8, address, @truncate(u8, value));
|
||||
} else {
|
||||
// STR
|
||||
const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
|
||||
const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);
|
||||
bus.write(u32, address, value);
|
||||
}
|
||||
}
|
||||
|
||||
address = modified_base;
|
||||
if (W and P or !P) cpu.r[rn] = address;
|
||||
if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
|
||||
if (W and P or !P) {
|
||||
cpu.r[rn] = address;
|
||||
if (rn == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
|
||||
if (L) {
|
||||
// This emulates the LDR rd == rn behaviour
|
||||
cpu.r[rd] = result;
|
||||
if (rd == 0xF) cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ pub fn armSoftwareInterrupt() InstrFn {
|
|||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
|
||||
// Copy Values from Current Mode
|
||||
const r15 = cpu.r[15];
|
||||
const ret_addr = cpu.r[15] - 4;
|
||||
const cpsr = cpu.cpsr.raw;
|
||||
|
||||
// Switch Mode
|
||||
|
|
@ -14,9 +14,10 @@ pub fn armSoftwareInterrupt() InstrFn {
|
|||
cpu.cpsr.t.write(false); // Force ARM Mode
|
||||
cpu.cpsr.i.write(true); // Disable normal interrupts
|
||||
|
||||
cpu.r[14] = r15; // Resume Execution
|
||||
cpu.r[14] = ret_addr; // Resume Execution
|
||||
cpu.spsr.raw = cpsr; // Previous mode CPSR
|
||||
cpu.r[15] = 0x0000_0008;
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,11 +18,9 @@ pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
|
|||
|
||||
fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
|
||||
const rs_idx = opcode >> 8 & 0xF;
|
||||
const rm = cpu.r[opcode & 0xF];
|
||||
const rs = @truncate(u8, cpu.r[rs_idx]);
|
||||
|
||||
const rm_idx = opcode & 0xF;
|
||||
const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
|
||||
|
||||
return switch (@truncate(u2, opcode >> 5)) {
|
||||
0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
|
||||
0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
|
||||
|
|
@ -33,9 +31,7 @@ fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
|
|||
|
||||
pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
|
||||
const amount = @truncate(u8, opcode >> 7 & 0x1F);
|
||||
|
||||
const rm_idx = opcode & 0xF;
|
||||
const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
|
||||
const rm = cpu.r[opcode & 0xF];
|
||||
|
||||
var result: u32 = undefined;
|
||||
if (amount == 0) {
|
||||
|
|
|
|||
|
|
@ -33,7 +33,8 @@ pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
|
|||
if (R) {
|
||||
if (L) {
|
||||
const value = bus.read(u32, address);
|
||||
cpu.r[15] = value & 0xFFFF_FFFE;
|
||||
cpu.r[15] = value & ~@as(u32, 1);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[14]);
|
||||
}
|
||||
|
|
@ -52,7 +53,13 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
|
|||
const end_address = cpu.r[rb] + 4 * countRlist(opcode);
|
||||
|
||||
if (opcode & 0xFF == 0) {
|
||||
if (L) cpu.r[15] = bus.read(u32, address) else bus.write(u32, address, cpu.r[15] + 4);
|
||||
if (L) {
|
||||
cpu.r[15] = bus.read(u32, address);
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
bus.write(u32, address, cpu.r[15] + 2);
|
||||
}
|
||||
|
||||
cpu.r[rb] += 0x40;
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,16 +9,13 @@ pub fn fmt16(comptime cond: u4) InstrFn {
|
|||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
// B
|
||||
const offset = sext(u32, u8, opcode & 0xFF) << 1;
|
||||
if (cond == 0xE or cond == 0xF)
|
||||
cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
|
||||
|
||||
const should_execute = switch (cond) {
|
||||
0xE, 0xF => cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond}),
|
||||
else => checkCond(cpu.cpsr, cond),
|
||||
};
|
||||
if (!checkCond(cpu.cpsr, cond)) return;
|
||||
|
||||
if (should_execute) {
|
||||
cpu.r[15] = (cpu.r[15] + 2) +% offset;
|
||||
}
|
||||
cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
@ -27,8 +24,8 @@ pub fn fmt18() InstrFn {
|
|||
return struct {
|
||||
// B but conditional
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
const offset = sext(u32, u11, opcode & 0x7FF) << 1;
|
||||
cpu.r[15] = (cpu.r[15] + 2) +% offset;
|
||||
cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
@ -41,13 +38,16 @@ pub fn fmt19(comptime is_low: bool) InstrFn {
|
|||
|
||||
if (is_low) {
|
||||
// Instruction 2
|
||||
const old_pc = cpu.r[15];
|
||||
const next_opcode = cpu.r[15] - 2;
|
||||
|
||||
cpu.r[15] = cpu.r[14] +% (offset << 1);
|
||||
cpu.r[14] = old_pc | 1;
|
||||
cpu.r[14] = next_opcode | 1;
|
||||
|
||||
cpu.pipe.reload(u16, cpu);
|
||||
} else {
|
||||
// Instruction 1
|
||||
cpu.r[14] = (cpu.r[15] + 2) +% (sext(u32, u11, offset) << 12);
|
||||
const lr_offset = sext(u32, u11, offset) << 12;
|
||||
cpu.r[14] = (cpu.r[15] +% lr_offset) & ~@as(u32, 1);
|
||||
}
|
||||
}
|
||||
}.inner;
|
||||
|
|
|
|||
|
|
@ -10,8 +10,6 @@ const sub = @import("../arm/data_processing.zig").sub;
|
|||
const cmp = @import("../arm/data_processing.zig").cmp;
|
||||
const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
|
||||
|
||||
const log = std.log.scoped(.Thumb1);
|
||||
|
||||
pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
|
|
@ -58,29 +56,38 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
|
|||
pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
|
||||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
const src_idx = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
|
||||
const dst_idx = @as(u4, h1) << 3 | (opcode & 0x7);
|
||||
const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
|
||||
const rd = @as(u4, h1) << 3 | (opcode & 0x7);
|
||||
|
||||
const src = if (src_idx == 0xF) (cpu.r[src_idx] + 2) & 0xFFFF_FFFE else cpu.r[src_idx];
|
||||
const dst = if (dst_idx == 0xF) (cpu.r[dst_idx] + 2) & 0xFFFF_FFFE else cpu.r[dst_idx];
|
||||
const rs_value = if (rs == 0xF) cpu.r[rs] & ~@as(u32, 1) else cpu.r[rs];
|
||||
const rd_value = if (rd == 0xF) cpu.r[rd] & ~@as(u32, 1) else cpu.r[rd];
|
||||
|
||||
switch (op) {
|
||||
0b00 => {
|
||||
// ADD
|
||||
const sum = add(false, cpu, dst, src);
|
||||
cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFE else sum;
|
||||
const sum = add(false, cpu, rd_value, rs_value);
|
||||
cpu.r[rd] = if (rd == 0xF) sum & ~@as(u32, 1) else sum;
|
||||
},
|
||||
0b01 => cmp(cpu, dst, src), // CMP
|
||||
0b01 => cmp(cpu, rd_value, rs_value), // CMP
|
||||
0b10 => {
|
||||
// MOV
|
||||
cpu.r[dst_idx] = if (dst_idx == 0xF) src & 0xFFFF_FFFE else src;
|
||||
cpu.r[rd] = if (rd == 0xF) rs_value & ~@as(u32, 1) else rs_value;
|
||||
},
|
||||
0b11 => {
|
||||
// BX
|
||||
cpu.cpsr.t.write(src & 1 == 1);
|
||||
cpu.r[15] = src & 0xFFFF_FFFE;
|
||||
const thumb = rs_value & 1 == 1;
|
||||
cpu.r[15] = rs_value & ~@as(u32, 1);
|
||||
|
||||
cpu.cpsr.t.write(thumb);
|
||||
if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
|
||||
|
||||
// TODO: We shouldn't need to worry about the if statement
|
||||
// below, because in BX, rd SBZ (and H1 is guaranteed to be 0)
|
||||
return;
|
||||
},
|
||||
}
|
||||
|
||||
if (rd == 0xF) cpu.pipe.reload(u16, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
@ -133,10 +140,9 @@ pub fn fmt12(comptime isSP: bool, comptime rd: u3) InstrFn {
|
|||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
|
||||
// ADD
|
||||
const left = if (isSP) cpu.r[13] else (cpu.r[15] + 2) & 0xFFFF_FFFD;
|
||||
const left = if (isSP) cpu.r[13] else cpu.r[15] & ~@as(u32, 2);
|
||||
const right = (opcode & 0xFF) << 2;
|
||||
const result = left + right;
|
||||
cpu.r[rd] = result;
|
||||
cpu.r[rd] = left + right;
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,7 +11,9 @@ pub fn fmt6(comptime rd: u3) InstrFn {
|
|||
fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
|
||||
// LDR
|
||||
const offset = (opcode & 0xFF) << 2;
|
||||
cpu.r[rd] = bus.read(u32, (cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
|
||||
|
||||
// Bit 1 of the PC intentionally ignored
|
||||
cpu.r[rd] = bus.read(u32, (cpu.r[15] & ~@as(u32, 2)) + offset);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ pub fn fmt17() InstrFn {
|
|||
return struct {
|
||||
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
|
||||
// Copy Values from Current Mode
|
||||
const r15 = cpu.r[15];
|
||||
const ret_addr = cpu.r[15] - 2;
|
||||
const cpsr = cpu.cpsr.raw;
|
||||
|
||||
// Switch Mode
|
||||
|
|
@ -14,9 +14,10 @@ pub fn fmt17() InstrFn {
|
|||
cpu.cpsr.t.write(false); // Force ARM Mode
|
||||
cpu.cpsr.i.write(true); // Disable normal interrupts
|
||||
|
||||
cpu.r[14] = r15; // Resume Execution
|
||||
cpu.r[14] = ret_addr; // Resume Execution
|
||||
cpu.spsr.raw = cpsr; // Previous mode CPSR
|
||||
cpu.r[15] = 0x0000_0008;
|
||||
cpu.pipe.reload(u32, cpu);
|
||||
}
|
||||
}.inner;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ const Allocator = std.mem.Allocator;
|
|||
// TODO: Move these to a TOML File
|
||||
const sync_audio = false; // Enable Audio Sync
|
||||
const sync_video: RunKind = .LimitedFPS; // Configure Video Sync
|
||||
pub const win_scale = 3; // 1x, 2x, 3x, etc. Window Scaling
|
||||
pub const win_scale = 4; // 1x, 2x, 3x, etc. Window Scaling
|
||||
pub const cpu_logging = false; // Enable detailed CPU logging
|
||||
pub const allow_unhandled_io = true; // Only relevant in Debug Builds
|
||||
pub const force_rtc = false;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ const std = @import("std");
|
|||
|
||||
const Bus = @import("Bus.zig");
|
||||
const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
|
||||
const Clock = @import("bus/GamePak.zig").Clock;
|
||||
const Clock = @import("bus/gpio.zig").Clock;
|
||||
|
||||
const Order = std.math.Order;
|
||||
const PriorityQueue = std.PriorityQueue;
|
||||
|
|
|
|||
|
|
@ -66,36 +66,68 @@ pub fn intToBytes(comptime T: type, value: anytype) [@sizeOf(T)]u8 {
|
|||
return result;
|
||||
}
|
||||
|
||||
/// The Title from the GBA Cartridge may be null padded to a maximum
|
||||
/// length of 12 bytes.
|
||||
/// The Title from the GBA Cartridge is an Uppercase ASCII string which is
|
||||
/// null-padded to 12 bytes
|
||||
///
|
||||
/// This function returns a slice of everything just before the first
|
||||
/// `\0`
|
||||
pub fn asStringSlice(title: *const [12]u8) []const u8 {
|
||||
var len = title.len;
|
||||
for (title) |char, i| {
|
||||
if (char == 0) {
|
||||
len = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return title[0..len];
|
||||
/// This function returns a slice of the ASCII string without the null terminator(s)
|
||||
/// (essentially, a proper Zig/Rust/Any modern language String)
|
||||
pub fn span(title: *const [12]u8) []const u8 {
|
||||
const end = std.mem.indexOfScalar(u8, title, '\x00');
|
||||
return title[0 .. end orelse title.len];
|
||||
}
|
||||
|
||||
/// Copies a Title and returns either an identical or similar
|
||||
/// array consisting of ASCII that won't make any file system angry
|
||||
test "span" {
|
||||
var example: *const [12]u8 = "POKEMON_EMER";
|
||||
try std.testing.expectEqualSlices(u8, "POKEMON_EMER", span(example));
|
||||
|
||||
example = "POKEMON_EME\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POKEMON_EME", span(example));
|
||||
|
||||
example = "POKEMON_EM\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POKEMON_EM", span(example));
|
||||
|
||||
example = "POKEMON_E\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POKEMON_E", span(example));
|
||||
|
||||
example = "POKEMON_\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POKEMON_", span(example));
|
||||
|
||||
example = "POKEMON\x00\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POKEMON", span(example));
|
||||
|
||||
example = "POKEMO\x00\x00\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POKEMO", span(example));
|
||||
|
||||
example = "POKEM\x00\x00\x00\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POKEM", span(example));
|
||||
|
||||
example = "POKE\x00\x00\x00\x00\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POKE", span(example));
|
||||
|
||||
example = "POK\x00\x00\x00\x00\x00\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "POK", span(example));
|
||||
|
||||
example = "PO\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "PO", span(example));
|
||||
|
||||
example = "P\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "P", span(example));
|
||||
|
||||
example = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
|
||||
try std.testing.expectEqualSlices(u8, "", span(example));
|
||||
}
|
||||
|
||||
/// Creates a copy of a title with all Filesystem-invalid characters replaced
|
||||
///
|
||||
/// e.g. POKEPIN R/S to POKEPIN R_S
|
||||
pub fn escape(title: [12]u8) [12]u8 {
|
||||
var result: [12]u8 = title;
|
||||
var ret: [12]u8 = title;
|
||||
|
||||
for (result) |*char| {
|
||||
if (char.* == '/' or char.* == '\\') char.* = '_';
|
||||
if (char.* == 0) break;
|
||||
}
|
||||
//TODO: Add more replacements
|
||||
std.mem.replaceScalar(u8, &ret, '/', '_');
|
||||
std.mem.replaceScalar(u8, &ret, '\\', '_');
|
||||
|
||||
return result;
|
||||
return ret;
|
||||
}
|
||||
|
||||
pub const FilePaths = struct {
|
||||
|
|
@ -151,6 +183,7 @@ pub const Logger = struct {
|
|||
|
||||
pub fn print(self: *Self, comptime format: []const u8, args: anytype) !void {
|
||||
try self.buf.writer().print(format, args);
|
||||
try self.buf.flush(); // FIXME: On panics, whatever is in the buffer isn't written to file
|
||||
}
|
||||
|
||||
pub fn mgbaLog(self: *Self, cpu: *const Arm7tdmi, opcode: u32) void {
|
||||
|
|
@ -190,7 +223,7 @@ pub const Logger = struct {
|
|||
cpu.r[12],
|
||||
cpu.r[13],
|
||||
cpu.r[14],
|
||||
cpu.r[15],
|
||||
cpu.r[15] - if (cpu.cpsr.t.read()) 2 else @as(u32, 4),
|
||||
cpu.cpsr.raw,
|
||||
opcode,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,14 +4,14 @@ const builtin = @import("builtin");
|
|||
const known_folders = @import("known_folders");
|
||||
const clap = @import("clap");
|
||||
|
||||
const Gui = @import("Gui.zig");
|
||||
const Gui = @import("platform.zig").Gui;
|
||||
const Bus = @import("core/Bus.zig");
|
||||
const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
|
||||
const Scheduler = @import("core/scheduler.zig").Scheduler;
|
||||
const FilePaths = @import("core/util.zig").FilePaths;
|
||||
|
||||
const Allocator = std.mem.Allocator;
|
||||
const log = std.log.scoped(.CLI);
|
||||
const log = std.log.scoped(.Cli);
|
||||
const width = @import("core/ppu.zig").width;
|
||||
const height = @import("core/ppu.zig").height;
|
||||
const cpu_logging = @import("core/emu.zig").cpu_logging;
|
||||
|
|
@ -54,8 +54,7 @@ pub fn main() anyerror!void {
|
|||
try bus.init(allocator, &scheduler, &cpu, paths);
|
||||
defer bus.deinit();
|
||||
|
||||
var gui = Gui.init(bus.pak.title, width, height);
|
||||
gui.initAudio(&bus.apu);
|
||||
var gui = Gui.init(&bus.pak.title, &bus.apu, width, height);
|
||||
defer gui.deinit();
|
||||
|
||||
try gui.run(&cpu, &scheduler);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,190 @@
|
|||
const std = @import("std");
|
||||
const SDL = @import("sdl2");
|
||||
const emu = @import("core/emu.zig");
|
||||
|
||||
const Apu = @import("core/apu.zig").Apu;
|
||||
const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
|
||||
const Scheduler = @import("core/scheduler.zig").Scheduler;
|
||||
const FpsTracker = @import("core/util.zig").FpsTracker;
|
||||
|
||||
const span = @import("core/util.zig").span;
|
||||
|
||||
const pitch = @import("core/ppu.zig").framebuf_pitch;
|
||||
const scale = @import("core/emu.zig").win_scale;
|
||||
|
||||
const default_title: []const u8 = "ZBA";
|
||||
|
||||
pub const Gui = struct {
|
||||
const Self = @This();
|
||||
const log = std.log.scoped(.Gui);
|
||||
|
||||
window: *SDL.SDL_Window,
|
||||
title: []const u8,
|
||||
renderer: *SDL.SDL_Renderer,
|
||||
texture: *SDL.SDL_Texture,
|
||||
audio: Audio,
|
||||
|
||||
pub fn init(title: *const [12]u8, apu: *Apu, width: i32, height: i32) Self {
|
||||
const ret = SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO | SDL.SDL_INIT_GAMECONTROLLER);
|
||||
if (ret < 0) panic();
|
||||
|
||||
const window = SDL.SDL_CreateWindow(
|
||||
default_title.ptr,
|
||||
SDL.SDL_WINDOWPOS_CENTERED,
|
||||
SDL.SDL_WINDOWPOS_CENTERED,
|
||||
@as(c_int, width * scale),
|
||||
@as(c_int, height * scale),
|
||||
SDL.SDL_WINDOW_SHOWN,
|
||||
) orelse panic();
|
||||
|
||||
const renderer = SDL.SDL_CreateRenderer(window, -1, SDL.SDL_RENDERER_ACCELERATED | SDL.SDL_RENDERER_PRESENTVSYNC) orelse panic();
|
||||
|
||||
const texture = SDL.SDL_CreateTexture(
|
||||
renderer,
|
||||
SDL.SDL_PIXELFORMAT_RGBA8888,
|
||||
SDL.SDL_TEXTUREACCESS_STREAMING,
|
||||
@as(c_int, width),
|
||||
@as(c_int, height),
|
||||
) orelse panic();
|
||||
|
||||
return Self{
|
||||
.window = window,
|
||||
.title = span(title),
|
||||
.renderer = renderer,
|
||||
.texture = texture,
|
||||
.audio = Audio.init(apu),
|
||||
};
|
||||
}
|
||||
|
||||
pub fn run(self: *Self, cpu: *Arm7tdmi, scheduler: *Scheduler) !void {
|
||||
var quit = std.atomic.Atomic(bool).init(false);
|
||||
var frame_rate = FpsTracker.init();
|
||||
|
||||
const thread = try std.Thread.spawn(.{}, emu.run, .{ &quit, &frame_rate, scheduler, cpu });
|
||||
defer thread.join();
|
||||
|
||||
var title_buf: [0x100]u8 = [_]u8{0} ** 0x100;
|
||||
|
||||
emu_loop: while (true) {
|
||||
var event: SDL.SDL_Event = undefined;
|
||||
while (SDL.SDL_PollEvent(&event) != 0) {
|
||||
switch (event.type) {
|
||||
SDL.SDL_QUIT => break :emu_loop,
|
||||
SDL.SDL_KEYDOWN => {
|
||||
const io = &cpu.bus.io;
|
||||
const key_code = event.key.keysym.sym;
|
||||
|
||||
switch (key_code) {
|
||||
SDL.SDLK_UP => io.keyinput.up.unset(),
|
||||
SDL.SDLK_DOWN => io.keyinput.down.unset(),
|
||||
SDL.SDLK_LEFT => io.keyinput.left.unset(),
|
||||
SDL.SDLK_RIGHT => io.keyinput.right.unset(),
|
||||
SDL.SDLK_x => io.keyinput.a.unset(),
|
||||
SDL.SDLK_z => io.keyinput.b.unset(),
|
||||
SDL.SDLK_a => io.keyinput.shoulder_l.unset(),
|
||||
SDL.SDLK_s => io.keyinput.shoulder_r.unset(),
|
||||
SDL.SDLK_RETURN => io.keyinput.start.unset(),
|
||||
SDL.SDLK_RSHIFT => io.keyinput.select.unset(),
|
||||
else => {},
|
||||
}
|
||||
},
|
||||
SDL.SDL_KEYUP => {
|
||||
const io = &cpu.bus.io;
|
||||
const key_code = event.key.keysym.sym;
|
||||
|
||||
switch (key_code) {
|
||||
SDL.SDLK_UP => io.keyinput.up.set(),
|
||||
SDL.SDLK_DOWN => io.keyinput.down.set(),
|
||||
SDL.SDLK_LEFT => io.keyinput.left.set(),
|
||||
SDL.SDLK_RIGHT => io.keyinput.right.set(),
|
||||
SDL.SDLK_x => io.keyinput.a.set(),
|
||||
SDL.SDLK_z => io.keyinput.b.set(),
|
||||
SDL.SDLK_a => io.keyinput.shoulder_l.set(),
|
||||
SDL.SDLK_s => io.keyinput.shoulder_r.set(),
|
||||
SDL.SDLK_RETURN => io.keyinput.start.set(),
|
||||
SDL.SDLK_RSHIFT => io.keyinput.select.set(),
|
||||
SDL.SDLK_i => log.err("Sample Count: {}", .{@intCast(u32, SDL.SDL_AudioStreamAvailable(cpu.bus.apu.stream)) / (2 * @sizeOf(u16))}),
|
||||
SDL.SDLK_j => log.err("Scheduler Capacity: {} | Scheduler Event Count: {}", .{ scheduler.queue.capacity(), scheduler.queue.count() }),
|
||||
SDL.SDLK_k => {
|
||||
// Dump IWRAM to file
|
||||
log.info("PC: 0x{X:0>8}", .{cpu.r[15]});
|
||||
log.info("LR: 0x{X:0>8}", .{cpu.r[14]});
|
||||
// const iwram_file = try std.fs.cwd().createFile("iwram.bin", .{});
|
||||
// defer iwram_file.close();
|
||||
|
||||
// try iwram_file.writeAll(cpu.bus.iwram.buf);
|
||||
},
|
||||
else => {},
|
||||
}
|
||||
},
|
||||
else => {},
|
||||
}
|
||||
}
|
||||
|
||||
// Emulator has an internal Double Buffer
|
||||
const framebuf = cpu.bus.ppu.framebuf.get(.Renderer);
|
||||
_ = SDL.SDL_UpdateTexture(self.texture, null, framebuf.ptr, pitch);
|
||||
_ = SDL.SDL_RenderCopy(self.renderer, self.texture, null, null);
|
||||
SDL.SDL_RenderPresent(self.renderer);
|
||||
|
||||
const dyn_title = std.fmt.bufPrint(&title_buf, "ZBA | {s} [Emu: {}fps] ", .{ self.title, frame_rate.value() }) catch unreachable;
|
||||
SDL.SDL_SetWindowTitle(self.window, dyn_title.ptr);
|
||||
}
|
||||
|
||||
quit.store(true, .SeqCst); // Terminate Emulator Thread
|
||||
}
|
||||
|
||||
pub fn deinit(self: *Self) void {
|
||||
self.audio.deinit();
|
||||
SDL.SDL_DestroyTexture(self.texture);
|
||||
SDL.SDL_DestroyRenderer(self.renderer);
|
||||
SDL.SDL_DestroyWindow(self.window);
|
||||
SDL.SDL_Quit();
|
||||
self.* = undefined;
|
||||
}
|
||||
};
|
||||
|
||||
const Audio = struct {
|
||||
const Self = @This();
|
||||
const log = std.log.scoped(.PlatformAudio);
|
||||
const sample_rate = @import("core/apu.zig").host_sample_rate;
|
||||
|
||||
device: SDL.SDL_AudioDeviceID,
|
||||
|
||||
fn init(apu: *Apu) Self {
|
||||
var have: SDL.SDL_AudioSpec = undefined;
|
||||
var want: SDL.SDL_AudioSpec = std.mem.zeroes(SDL.SDL_AudioSpec);
|
||||
want.freq = sample_rate;
|
||||
want.format = SDL.AUDIO_U16;
|
||||
want.channels = 2;
|
||||
want.samples = 0x100;
|
||||
want.callback = Self.callback;
|
||||
want.userdata = apu;
|
||||
|
||||
const device = SDL.SDL_OpenAudioDevice(null, 0, &want, &have, 0);
|
||||
if (device == 0) panic();
|
||||
|
||||
SDL.SDL_PauseAudioDevice(device, 0); // Unpause Audio
|
||||
|
||||
return .{ .device = device };
|
||||
}
|
||||
|
||||
fn deinit(self: *Self) void {
|
||||
SDL.SDL_CloseAudioDevice(self.device);
|
||||
self.* = undefined;
|
||||
}
|
||||
|
||||
export fn callback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void {
|
||||
const apu = @ptrCast(*Apu, @alignCast(@alignOf(*Apu), userdata));
|
||||
_ = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
|
||||
|
||||
// If we don't write anything, play silence otherwise garbage will be played
|
||||
// FIXME: I don't think this hack to remove DC Offset is acceptable :thinking:
|
||||
// if (written == 0) std.mem.set(u8, stream[0..@intCast(usize, len)], 0x40);
|
||||
}
|
||||
};
|
||||
|
||||
fn panic() noreturn {
|
||||
const str = @as(?[*:0]const u8, SDL.SDL_GetError()) orelse "unknown error";
|
||||
@panic(std.mem.sliceTo(str, 0));
|
||||
}
|
||||
Loading…
Reference in New Issue