feat: pass arm.gba

src/cpu/arm/block_data_transfer.zig

@@ -7,43 +7,78 @@ const InstrFn = @import("../../cpu.zig").ArmInstrFn;
 pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
-            const r15_present = opcode >> 15 & 1 == 1;
+            const rn = @truncate(u4, opcode >> 16 & 0xF);
-            const rn = opcode >> 16 & 0xF;
+            const rlist = opcode & 0xFFFF;
-            const base = cpu.r[rn];
+            const r15 = rlist >> 15 & 1 == 1;
 
-            const in_list = opcode >> @truncate(u4, rn) & 1 == 1;
+            var count: u32 = 0;
-
-            var address: u32 = base;
-            if (U) {
-                // Increment
             var i: u5 = 0;
-                while (i < 0x10) : (i += 1) {
+            var first: u4 = 0;
-                    if (opcode >> i & 1 == 1) {
+            var write_to_base = true;
-                        if (P) address += 4;
+
-                        transfer(cpu, bus, r15_present, i, address);
+            while (i < 16) : (i += 1) {
-                        if (!P) address += 4;
+                const r = @truncate(u4, 15 - i);
+                if (rlist >> r & 1 == 1) {
+                    first = r;
+                    count += 1;
                 }
             }
+
+            var start = cpu.r[rn];
+            if (U) {
+                start += if (P) 4 else 0;
             } else {
-                // Decrement
+                start = start - (4 * count) + if (!P) 4 else 0;
+            }
 
-                var i: u5 = 0x10;
+            var end = cpu.r[rn];
-                while (i > 0) : (i -= 1) {
+            if (U) {
-                    const j = i - 1;
+                end = end + (4 * count) - if (!P) 4 else 0;
+            } else {
+                end -= if (P) 4 else 0;
+            }
 
-                    if (opcode >> j & 1 == 1) {
+            var new_base = cpu.r[rn];
-                        if (P) address -= 4;
+            if (U) {
-                        transfer(cpu, bus, r15_present, j, address);
+                new_base += 4 * count;
-                        if (!P) address -= 4;
+            } else {
+                new_base -= 4 * count;
+            }
+
+            var address = start;
+
+            if (rlist == 0) {
+                var pc_addr = cpu.r[rn];
+                if (U) {
+                    pc_addr += if (P) 4 else 0;
+                } else {
+                    pc_addr -= 0x40 - if (!P) 4 else 0;
+                }
+
+                if (L) {
+                    cpu.r[15] = bus.read32(pc_addr);
+                } else {
+                    bus.write32(pc_addr, cpu.r[15] + 8);
+                }
+
+                cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
+                return;
+            }
+
+            i = first;
+            while (i < 16) : (i += 1) {
+                if (rlist >> i & 1 == 1) {
+                    transfer(cpu, bus, r15, i, address);
+                    address += 4;
+
+                    if (W and !L and write_to_base) {
+                        cpu.r[rn] = new_base;
+                        write_to_base = false;
                     }
                 }
             }
 
-            if (W) {
+            if (W and L and rlist >> rn & 1 == 0) cpu.r[rn] = new_base;
-                if (!L or (L and !in_list)) {
-                    cpu.r[rn] = address;
-                }
-            }
         }
 
         fn transfer(cpu: *Arm7tdmi, bus: *Bus, r15_present: bool, i: u5, address: u32) void {

src/cpu/arm/half_signed_data_transfer.zig

@@ -45,14 +45,20 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
                     },
                     0b11 => {
                         // LDRSH
-                        result = util.u32SignExtend(16, bus.read16(address & 0xFFFF_FFFE));
+                        const value = if (address & 1 == 1) blk: {
+                            break :blk util.u32SignExtend(8, bus.read8(address));
+                        } else blk: {
+                            break :blk util.u32SignExtend(16, bus.read16(address));
+                        };
+
+                        result = std.math.rotr(u32, value, 8 * (address & 1));
                     },
                     0b00 => unreachable, // SWP
                 }
             } else {
                 if (opcode >> 5 & 0x01 == 0x01) {
                     // STRH
-                    bus.write16(address, @truncate(u16, cpu.r[rd]));
+                    bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
                 } else unreachable; // SWP
             }
 

src/cpu/arm/single_data_swap.zig

@@ -20,8 +20,8 @@ pub fn singleDataSwap(comptime B: bool) InstrFn {
                 cpu.r[rd] = value;
             } else {
                 // SWP
-                const value = std.math.rotr(u32, bus.read32(address), 8 * (address & 0x3));
+                const value = std.math.rotr(u32, bus.read32(address & 0xFFFF_FFFC), 8 * (address & 0x3));
-                bus.write32(address, cpu.r[rm]);
+                bus.write32(address & 0xFFFF_FFFC, cpu.r[rm]);
                 cpu.r[rd] = value;
             }
         }

src/cpu/arm/single_data_transfer.zig

@@ -38,11 +38,12 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             } else {
                 if (B) {
                     // STRB
-                    bus.write8(address, @truncate(u8, cpu.r[rd]));
+                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    bus.write8(address, @truncate(u8, value));
                 } else {
                     // STR
-                    const force_aligned = address & 0xFFFF_FFFC;
+                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
-                    bus.write32(force_aligned, cpu.r[rd]);
+                    bus.write32(address & 0xFFFF_FFFC, value);
                 }
             }
 

src/cpu/thumb/block_data_transfer.zig

@@ -54,7 +54,7 @@ pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
             const end_address = cpu.r[rb] + 4 * countRlist(opcode);
 
             if (opcode & 0xFF == 0) {
-                if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 4); // TODO: Why is this r[15] + 4?
+                if (L) cpu.r[15] = bus.read32(address) else bus.write32(address, cpu.r[15] + 4);
                 cpu.r[rb] += 0x40;
                 return;
             }