fix: account for pipeline in obscure bios behaviour

The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code

Now, the PC is always incremented when the pipeline is reloaded

.gitmodules

@@ -7,3 +7,6 @@
 [submodule "lib/known-folders"]
 	path = lib/known-folders
 	url = https://github.com/ziglibs/known-folders
+[submodule "lib/zig-datetime"]
+	path = lib/zig-datetime
+	url = https://github.com/frmdstryr/zig-datetime

README.md

@@ -2,13 +2,13 @@
 An in-progress Game Boy Advance Emulator written in Zig ⚡!
 
 ## Tests 
-- [ ] [jsmolka's GBA Test Collection](https://github.com/jsmolka/gba-tests)
+- [x] [jsmolka's GBA Test Collection](https://github.com/jsmolka/gba-tests)
     - [x] `arm.gba` and `thumb.gba`
     - [x] `flash64.gba`, `flash128.gba`, `none.gba`, and `sram.gba`
     - [x] `hello.gba`, `shades.gba`, and `stripes.gba`
     - [x] `memory.gba`
     - [x] `bios.gba`
-    - [ ] `nes.gba`
+    - [x] `nes.gba`
 - [ ] [DenSinH's GBA ROMs](https://github.com/DenSinH/GBARoms)
     - [x] `eeprom-test` and `flash-test`
     - [x] `midikey2freq`

build.zig

@@ -13,10 +13,12 @@ pub fn build(b: *std.build.Builder) void {
     const mode = b.standardReleaseOptions();
 
     const exe = b.addExecutable("zba", "src/main.zig");
-    
     // Known Folders (%APPDATA%, XDG, etc.)
     exe.addPackagePath("known_folders", "lib/known-folders/known-folders.zig");
 
+    // DateTime Library
+    exe.addPackagePath("datetime", "lib/zig-datetime/src/main.zig");
+
     // Bitfield type from FlorenceOS: https://github.com/FlorenceOS/
     // exe.addPackage(.{ .name = "bitfield", .path = .{ .path = "lib/util/bitfield.zig" } });
     exe.addPackagePath("bitfield", "lib/util/bitfield.zig");

lib/zig-datetime

@@ -0,0 +1 @@
+Subproject commit 5ec1c36cf3791b3c6c5b330357bdb6feb93979ba

src/core/Bus.zig

@@ -51,7 +51,7 @@ sched: *Scheduler,
 
 pub fn init(self: *Self, allocator: Allocator, sched: *Scheduler, cpu: *Arm7tdmi, paths: FilePaths) !void {
     self.* = .{
-        .pak = try GamePak.init(allocator, paths.rom, paths.save),
+        .pak = try GamePak.init(allocator, cpu, paths.rom, paths.save),
         .bios = try Bios.init(allocator, paths.bios),
         .ppu = try Ppu.init(allocator, sched),
         .apu = Apu.init(sched),

src/core/bus/Bios.zig

@@ -39,12 +39,12 @@ pub fn read(self: *Self, comptime T: type, r15: u32, addr: u32) T {
     }
 
     log.debug("Rejected read since r15=0x{X:0>8}", .{r15});
-    return @truncate(T, self.uncheckedRead(T, self.addr_latch + 8));
+    return @truncate(T, self.uncheckedRead(T, self.addr_latch));
 }
 
 pub fn dbgRead(self: *const Self, comptime T: type, r15: u32, addr: u32) T {
     if (r15 < Self.size) return self.uncheckedRead(T, addr);
-    return @truncate(T, self.uncheckedRead(T, self.addr_latch + 8));
+    return @truncate(T, self.uncheckedRead(T, self.addr_latch));
 }
 
 fn uncheckedRead(self: *const Self, comptime T: type, addr: u32) T {

src/core/bus/GamePak.zig

@@ -1,7 +1,13 @@
 const std = @import("std");
+const DateTime = @import("datetime").datetime.Datetime;
 
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const Bit = @import("bitfield").Bit;
+const Bitfield = @import("bitfield").Bitfield;
 const Backup = @import("backup.zig").Backup;
 const Allocator = std.mem.Allocator;
+
+const force_rtc = @import("../emu.zig").force_rtc;
 const log = std.log.scoped(.GamePak);
 
 const Self = @This();
@@ -10,31 +16,48 @@ title: [12]u8,
 buf: []u8,
 allocator: Allocator,
 backup: Backup,
+gpio: *Gpio,
 
-pub fn init(allocator: Allocator, rom_path: []const u8, save_path: ?[]const u8) !Self {
+pub fn init(allocator: Allocator, cpu: *Arm7tdmi, rom_path: []const u8, save_path: ?[]const u8) !Self {
     const file = try std.fs.cwd().openFile(rom_path, .{});
     defer file.close();
 
     const file_buf = try file.readToEndAlloc(allocator, try file.getEndPos());
-    const title = parseTitle(file_buf);
-    const kind = Backup.guessKind(file_buf) orelse .None;
+    const title = file_buf[0xA0..0xAC].*;
+    const kind = Backup.guessKind(file_buf);
+    const device = if (force_rtc) .Rtc else guessDevice(file_buf);
 
-    const pak = Self{
+    logHeader(file_buf, &title);
+
+    return .{
         .buf = file_buf,
         .allocator = allocator,
         .title = title,
         .backup = try Backup.init(allocator, kind, title, save_path),
+        .gpio = try Gpio.init(allocator, cpu, device),
     };
-    pak.parseHeader();
-
-    return pak;
 }
 
-fn parseHeader(self: *const Self) void {
-    const title = parseTitle(self.buf);
-    const code = self.buf[0xAC..0xB0];
-    const maker = self.buf[0xB0..0xB2];
-    const version = self.buf[0xBC];
+/// Searches the ROM to see if it can determine whether the ROM it's searching uses
+/// any GPIO device, like a RTC for example.
+fn guessDevice(buf: []const u8) Gpio.Device.Kind {
+    // Try to Guess if ROM uses RTC
+    const needle = "RTC_V"; // I was told SIIRTC_V, though Pokemen Firered (USA) is a false negative
+
+    var i: usize = 0;
+    while ((i + needle.len) < buf.len) : (i += 1) {
+        if (std.mem.eql(u8, needle, buf[i..(i + needle.len)])) return .Rtc;
+    }
+
+    // TODO: Detect other GPIO devices
+
+    return .None;
+}
+
+fn logHeader(buf: []const u8, title: *const [12]u8) void {
+    const code = buf[0xAC..0xB0];
+    const maker = buf[0xB0..0xB2];
+    const version = buf[0xBC];
 
     log.info("Title: {s}", .{title});
     if (version != 0) log.info("Version: {}", .{version});
@@ -42,10 +65,6 @@ fn parseHeader(self: *const Self) void {
     if (lookupMaker(maker)) |c| log.info("Maker: {s}", .{c}) else log.info("Maker Code: {s}", .{maker});
 }
 
-fn parseTitle(buf: []u8) [12]u8 {
-    return buf[0xA0..0xAC].*;
-}
-
 fn lookupMaker(slice: *const [2]u8) ?[]const u8 {
     const id = @as(u16, slice[1]) << 8 | @as(u16, slice[0]);
     return switch (id) {
@@ -60,6 +79,8 @@ inline fn isLarge(self: *const Self) bool {
 
 pub fn deinit(self: *Self) void {
     self.backup.deinit();
+    self.gpio.deinit(self.allocator);
+    self.allocator.destroy(self.gpio);
     self.allocator.free(self.buf);
     self.* = undefined;
 }
@@ -83,6 +104,35 @@ pub fn read(self: *Self, comptime T: type, address: u32) T {
         }
     }
 
+    if (self.gpio.cnt == 1) {
+        // GPIO Can be read from
+        // We assume that this will only be true when a ROM actually does want something from GPIO
+
+        switch (T) {
+            u32 => switch (address) {
+                // TODO: Do I even need to implement these?
+                0x0800_00C4 => std.debug.panic("Handle 32-bit GPIO Data/Direction Reads", .{}),
+                0x0800_00C6 => std.debug.panic("Handle 32-bit GPIO Direction/Control Reads", .{}),
+                0x0800_00C8 => std.debug.panic("Handle 32-bit GPIO Control Reads", .{}),
+                else => {},
+            },
+            u16 => switch (address) {
+                // FIXME: What do 16-bit GPIO Reads look like?
+                0x0800_00C4 => return self.gpio.read(.Data),
+                0x0800_00C6 => return self.gpio.read(.Direction),
+                0x0800_00C8 => return self.gpio.read(.Control),
+                else => {},
+            },
+            u8 => switch (address) {
+                0x0800_00C4 => return self.gpio.read(.Data),
+                0x0800_00C6 => return self.gpio.read(.Direction),
+                0x0800_00C8 => return self.gpio.read(.Control),
+                else => {},
+            },
+            else => @compileError("GamePak[GPIO]: Unsupported read width"),
+        }
+    }
+
     return switch (T) {
         u32 => (@as(T, self.get(addr + 3)) << 24) | (@as(T, self.get(addr + 2)) << 16) | (@as(T, self.get(addr + 1)) << 8) | (@as(T, self.get(addr))),
         u16 => (@as(T, self.get(addr + 1)) << 8) | @as(T, self.get(addr)),
@@ -141,17 +191,23 @@ pub fn write(self: *Self, comptime T: type, word_count: u16, address: u32, value
 
     switch (T) {
         u32 => switch (address) {
-            0x0800_00C4 => log.debug("Wrote {} 0x{X:} to I/O Port Data and Direction", .{ T, value }),
-            0x0800_00C6 => log.debug("Wrote {} 0x{X:} to I/O Port Direction and Control", .{ T, value }),
-            else => {},
+            0x0800_00C4 => {
+                self.gpio.write(.Data, @truncate(u4, value));
+                self.gpio.write(.Direction, @truncate(u4, value >> 16));
+            },
+            0x0800_00C6 => {
+                self.gpio.write(.Direction, @truncate(u4, value));
+                self.gpio.write(.Control, @truncate(u1, value >> 16));
+            },
+            else => log.err("Wrote {} 0x{X:0>8} to 0x{X:0>8}, Unhandled", .{ T, value, address }),
         },
         u16 => switch (address) {
-            0x0800_00C4 => log.debug("Wrote {} 0x{X:} to I/O Port Data", .{ T, value }),
-            0x0800_00C6 => log.debug("Wrote {} 0x{X:} to I/O Port Direction", .{ T, value }),
-            0x0800_00C8 => log.debug("Wrote {} 0x{X:} to I/O Port Control", .{ T, value }),
-            else => {},
+            0x0800_00C4 => self.gpio.write(.Data, @truncate(u4, value)),
+            0x0800_00C6 => self.gpio.write(.Direction, @truncate(u4, value)),
+            0x0800_00C8 => self.gpio.write(.Control, @truncate(u1, value)),
+            else => log.err("Wrote {} 0x{X:0>4} to 0x{X:0>8}, Unhandled", .{ T, value, address }),
         },
-        u8 => log.debug("Wrote {} 0x{X:} to 0x{X:0>8}, Ignored.", .{ T, value, address }),
+        u8 => log.debug("Wrote {} 0x{X:0>2} to 0x{X:0>8}, Ignored.", .{ T, value, address }),
         else => @compileError("GamePak: Unsupported write width"),
     }
 }
@@ -183,3 +239,463 @@ test "OOB Access" {
     std.debug.assert(pak.get(4) == 0x02); // 0x0002
     std.debug.assert(pak.get(5) == 0x00);
 }
+
+/// GPIO Register Implementation
+const Gpio = struct {
+    const This = @This();
+
+    data: u4,
+    direction: u4,
+    cnt: u1,
+
+    device: Device,
+
+    const Device = struct {
+        ptr: ?*anyopaque,
+        kind: Kind, // TODO: Make comptime known?
+
+        const Kind = enum { Rtc, None };
+
+        fn step(self: *Device, value: u4) u4 {
+            return switch (self.kind) {
+                .Rtc => blk: {
+                    const clock = @ptrCast(*Clock, @alignCast(@alignOf(*Clock), self.ptr.?));
+                    break :blk clock.step(Clock.Data{ .raw = value });
+                },
+                .None => value,
+            };
+        }
+
+        fn init(kind: Kind, ptr: ?*anyopaque) Device {
+            return .{ .kind = kind, .ptr = ptr };
+        }
+    };
+
+    const Register = enum {
+        Data,
+        Direction,
+        Control,
+    };
+
+    fn init(allocator: Allocator, cpu: *Arm7tdmi, kind: Device.Kind) !*This {
+        log.info("Device: {}", .{kind});
+
+        const self = try allocator.create(This);
+        self.* = .{
+            .data = 0b0000,
+            .direction = 0b1111, // TODO: What is GPIO DIrection set to by default?
+            .cnt = 0b0,
+
+            .device = switch (kind) {
+                .Rtc => blk: {
+                    const clock = try allocator.create(Clock);
+                    clock.init(cpu, self);
+
+                    break :blk Device{ .kind = kind, .ptr = clock };
+                },
+                .None => Device{ .kind = kind, .ptr = null },
+            },
+        };
+
+        return self;
+    }
+
+    fn deinit(self: *This, allocator: Allocator) void {
+        switch (self.device.kind) {
+            .Rtc => {
+                allocator.destroy(@ptrCast(*Clock, @alignCast(@alignOf(*Clock), self.device.ptr.?)));
+            },
+            .None => {},
+        }
+
+        self.* = undefined;
+    }
+
+    fn write(self: *This, comptime reg: Register, value: if (reg == .Control) u1 else u4) void {
+        switch (reg) {
+            .Data => {
+                const masked_value = value & self.direction;
+
+                // The value which is actually stored in the GPIO register
+                // might be modified by the device implementing the GPIO interface e.g. RTC reads
+                self.data = self.device.step(masked_value);
+            },
+            .Direction => self.direction = value,
+            .Control => self.cnt = value,
+        }
+    }
+
+    fn read(self: *const This, comptime reg: Register) if (reg == .Control) u1 else u4 {
+        if (self.cnt == 0) return 0;
+
+        return switch (reg) {
+            .Data => self.data & ~self.direction,
+            .Direction => self.direction,
+            .Control => self.cnt,
+        };
+    }
+};
+
+/// GBA Real Time Clock
+pub const Clock = struct {
+    const This = @This();
+
+    writer: Writer,
+    reader: Reader,
+    state: State,
+    cnt: Control,
+
+    year: u8,
+    month: u5,
+    day: u6,
+    weekday: u3,
+    hour: u6,
+    minute: u7,
+    second: u7,
+
+    cpu: *Arm7tdmi,
+    gpio: *const Gpio,
+
+    const Register = enum {
+        Control,
+        DateTime,
+        Time,
+    };
+
+    const State = union(enum) {
+        Idle,
+        Command,
+        Write: Register,
+        Read: Register,
+    };
+
+    const Reader = struct {
+        i: u4,
+        count: u8,
+
+        /// Reads a bit from RTC registers. Which bit it reads is dependent on
+        ///
+        /// 1. The RTC State Machine, whitch tells us which register we're accessing
+        /// 2. A `count`, which keeps track of which byte is currently being read
+        /// 3. An index, which keeps track of which bit of the byte determined by `count` is being read
+        fn read(self: *Reader, clock: *const Clock, register: Register) u1 {
+            const idx = @intCast(u3, self.i);
+            defer self.i += 1;
+
+            // FIXME: What do I do about the unused bits?
+            return switch (register) {
+                .Control => @truncate(u1, switch (self.count) {
+                    0 => clock.cnt.raw >> idx,
+                    else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 1 byte)", .{ self.count, register }),
+                }),
+                .DateTime => @truncate(u1, switch (self.count) {
+                    // Date
+                    0 => clock.year >> idx,
+                    1 => @as(u8, clock.month) >> idx,
+                    2 => @as(u8, clock.day) >> idx,
+                    3 => @as(u8, clock.weekday) >> idx,
+
+                    // Time
+                    4 => @as(u8, clock.hour) >> idx,
+                    5 => @as(u8, clock.minute) >> idx,
+                    6 => @as(u8, clock.second) >> idx,
+                    else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 7 bytes)", .{ self.count, register }),
+                }),
+                .Time => @truncate(u1, switch (self.count) {
+                    0 => @as(u8, clock.hour) >> idx,
+                    1 => @as(u8, clock.minute) >> idx,
+                    2 => @as(u8, clock.second) >> idx,
+                    else => std.debug.panic("Tried to read from byte #{} of {} (hint: there's only 3 bytes)", .{ self.count, register }),
+                }),
+            };
+        }
+
+        /// Is true when a Reader has read a u8's worth of bits
+        fn finished(self: *const Reader) bool {
+            return self.i >= 8;
+        }
+
+        /// Resets the index used to shift bits out of RTC registers
+        /// and `count`, which is used to keep track of which byte we're reading
+        /// is incremeneted
+        fn lap(self: *Reader) void {
+            self.i = 0;
+            self.count += 1;
+        }
+
+        /// Resets the state of a `Reader` in preparation for a future
+        /// read command
+        fn reset(self: *Reader) void {
+            self.i = 0;
+            self.count = 0;
+        }
+    };
+
+    const Writer = struct {
+        buf: u8,
+        i: u4,
+
+        /// The Number of bytes written since last reset
+        count: u8,
+
+        /// Append a bit to the internal bit buffer (aka an integer)
+        fn push(self: *Writer, value: u1) void {
+            const idx = @intCast(u3, self.i);
+            self.buf = (self.buf & ~(@as(u8, 1) << idx)) | @as(u8, value) << idx;
+            self.i += 1;
+        }
+
+        /// Takes the contents of the internal buffer and writes it to an RTC register
+        /// Where it writes to is dependent on:
+        ///
+        /// 1. The RTC State Machine, whitch tells us which register we're accessing
+        /// 2. A `count`, which keeps track of which byte is currently being read
+        fn write(self: *const Writer, clock: *Clock, register: Register) void {
+            // FIXME: What do do about unused bits?
+            switch (register) {
+                .Control => switch (self.count) {
+                    0 => clock.cnt.raw = (clock.cnt.raw & 0x80) | (self.buf & 0x7F), // Bit 7 read-only
+                    else => std.debug.panic("Tried to write to byte #{} of {} (hint: there's only 1 byte)", .{ self.count, register }),
+                },
+                .DateTime, .Time => log.debug("RTC: Ignoring {} write", .{register}),
+            }
+        }
+
+        /// Is true when 8 bits have been shifted into the internal buffer
+        fn finished(self: *const Writer) bool {
+            return self.i >= 8;
+        }
+
+        /// Resets the internal buffer
+        /// resets the index used to shift bits into the internal buffer
+        /// increments `count` (which keeps track of byte offsets) by one
+        fn lap(self: *Writer) void {
+            self.buf = 0;
+            self.i = 0;
+            self.count += 1;
+        }
+
+        /// Resets `Writer` to a clean state in preparation for a future write command
+        fn reset(self: *Writer) void {
+            self.buf = 0;
+            self.i = 0;
+            self.count = 0;
+        }
+    };
+
+    const Data = extern union {
+        sck: Bit(u8, 0),
+        sio: Bit(u8, 1),
+        cs: Bit(u8, 2),
+        raw: u8,
+    };
+
+    const Control = extern union {
+        /// Unknown, value should be preserved though
+        unk: Bit(u8, 1),
+        /// Per-minute IRQ
+        /// If set, fire a Gamepak IRQ every 30s,
+        irq: Bit(u8, 3),
+        /// 12/24 Hour Bit
+        /// If set, 12h mode
+        /// If cleared, 24h mode
+        mode: Bit(u8, 6),
+        /// Read-Only, bit cleared on read
+        /// If is set, means that there has been a failure / time has been lost
+        off: Bit(u8, 7),
+        raw: u8,
+    };
+
+    fn init(ptr: *This, cpu: *Arm7tdmi, gpio: *const Gpio) void {
+        ptr.* = .{
+            .writer = .{ .buf = 0, .i = 0, .count = 0 },
+            .reader = .{ .i = 0, .count = 0 },
+            .state = .Idle,
+            .cnt = .{ .raw = 0 },
+            .year = 0x01,
+            .month = 0x6,
+            .day = 0x13,
+            .weekday = 0x3,
+            .hour = 0x23,
+            .minute = 0x59,
+            .second = 0x59,
+            .cpu = cpu,
+            .gpio = gpio, // Can't use Arm7tdmi ptr b/c not initialized yet
+        };
+
+        cpu.sched.push(.RealTimeClock, 1 << 24); // Every Second
+    }
+
+    pub fn updateTime(self: *This, late: u64) void {
+        self.cpu.sched.push(.RealTimeClock, (1 << 24) -| late); // Reschedule
+
+        const now = DateTime.now();
+        self.year = toBcd(u8, @intCast(u8, now.date.year - 2000));
+        self.month = toBcd(u5, now.date.month);
+        self.day = toBcd(u6, now.date.day);
+        self.weekday = toBcd(u3, (now.date.weekday() + 1) % 7); // API is Monday = 0, Sunday = 6. We want Sunday = 0, Saturday = 6
+        self.hour = toBcd(u6, now.time.hour);
+        self.minute = toBcd(u7, now.time.minute);
+        self.second = toBcd(u7, now.time.second);
+    }
+
+    fn step(self: *This, value: Data) u4 {
+        const cache: Data = .{ .raw = self.gpio.data };
+
+        return switch (self.state) {
+            .Idle => blk: {
+                // FIXME: Maybe check incoming value to see if SCK is also high?
+                if (cache.sck.read()) {
+                    if (!cache.cs.read() and value.cs.read()) {
+                        log.debug("RTC: Entering Command Mode", .{});
+                        self.state = .Command;
+                    }
+                }
+
+                break :blk @truncate(u4, value.raw);
+            },
+            .Command => blk: {
+                if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
+
+                // If SCK rises, sample SIO
+                if (!cache.sck.read() and value.sck.read()) {
+                    self.writer.push(@boolToInt(value.sio.read()));
+
+                    if (self.writer.finished()) {
+                        self.state = self.processCommand(self.writer.buf);
+                        self.writer.reset();
+
+                        log.debug("RTC: Switching to {}", .{self.state});
+                    }
+                }
+
+                break :blk @truncate(u4, value.raw);
+            },
+            .Write => |register| blk: {
+                if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
+
+                // If SCK rises, sample SIO
+                if (!cache.sck.read() and value.sck.read()) {
+                    self.writer.push(@boolToInt(value.sio.read()));
+
+                    const register_width: u32 = switch (register) {
+                        .Control => 1,
+                        .DateTime => 7,
+                        .Time => 3,
+                    };
+
+                    if (self.writer.finished()) {
+                        self.writer.write(self, register); // write inner buffer to RTC register
+                        self.writer.lap();
+
+                        if (self.writer.count == register_width) {
+                            self.writer.reset();
+                            self.state = .Idle;
+                        }
+                    }
+                }
+
+                break :blk @truncate(u4, value.raw);
+            },
+            .Read => |register| blk: {
+                if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
+                var ret = value;
+
+                // if SCK rises, sample SIO
+                if (!cache.sck.read() and value.sck.read()) {
+                    ret.sio.write(self.reader.read(self, register) == 0b1);
+
+                    const register_width: u32 = switch (register) {
+                        .Control => 1,
+                        .DateTime => 7,
+                        .Time => 3,
+                    };
+
+                    if (self.reader.finished()) {
+                        self.reader.lap();
+
+                        if (self.reader.count == register_width) {
+                            self.reader.reset();
+                            self.state = .Idle;
+                        }
+                    }
+                }
+
+                break :blk @truncate(u4, ret.raw);
+            },
+        };
+    }
+
+    fn reset(self: *This) void {
+        // mGBA and NBA only zero the control register. We will do the same
+        log.debug("RTC: Reset (control register was zeroed)", .{});
+
+        self.cnt.raw = 0;
+    }
+
+    fn irq(self: *This) void {
+        // TODO: Confirm that this is the right behaviour
+        log.debug("RTC: Force GamePak IRQ", .{});
+
+        self.cpu.bus.io.irq.game_pak.set();
+        self.cpu.handleInterrupt();
+    }
+
+    fn processCommand(self: *This, raw_command: u8) State {
+        const command = blk: {
+            // If High Nybble is 0x6, no need to switch the endianness
+            if (raw_command >> 4 & 0xF == 0x6) break :blk raw_command;
+
+            // Turns out reversing the order of bits isn't trivial at all
+            // https://stackoverflow.com/questions/2602823/in-c-c-whats-the-simplest-way-to-reverse-the-order-of-bits-in-a-byte
+            var ret = raw_command;
+            ret = (ret & 0xF0) >> 4 | (ret & 0x0F) << 4;
+            ret = (ret & 0xCC) >> 2 | (ret & 0x33) << 2;
+            ret = (ret & 0xAA) >> 1 | (ret & 0x55) << 1;
+
+            break :blk ret;
+        };
+        log.debug("RTC: Handling Command 0x{X:0>2} [0b{b:0>8}]", .{ command, command });
+
+        const is_write = command & 1 == 0;
+        const rtc_register = @truncate(u3, command >> 1 & 0x7);
+
+        if (is_write) {
+            return switch (rtc_register) {
+                0 => blk: {
+                    self.reset();
+                    break :blk .Idle;
+                },
+                1 => .{ .Write = .Control },
+                2 => .{ .Write = .DateTime },
+                3 => .{ .Write = .Time },
+                6 => blk: {
+                    self.irq();
+                    break :blk .Idle;
+                },
+                4, 5, 7 => .Idle,
+            };
+        } else {
+            return switch (rtc_register) {
+                1 => .{ .Read = .Control },
+                2 => .{ .Read = .DateTime },
+                3 => .{ .Read = .Time },
+                0, 4, 5, 6, 7 => .Idle, // Do Nothing
+            };
+        }
+    }
+};
+
+fn toBcd(comptime T: type, value: u8) T {
+    var input = value;
+    var ret: u8 = 0;
+    var shift: u3 = 0;
+
+    while (input > 0) {
+        ret |= (input % 10) << (shift << 2);
+        shift += 1;
+        input /= 10;
+    }
+
+    return @truncate(T, ret);
+}

src/core/bus/backup.zig

@@ -61,7 +61,7 @@ pub const Backup = struct {
         return backup;
     }
 
-    pub fn guessKind(rom: []const u8) ?Kind {
+    pub fn guessKind(rom: []const u8) Kind {
         for (backup_kinds) |needle| {
             const needle_len = needle.str.len;
 
@@ -71,7 +71,7 @@ pub const Backup = struct {
             }
         }
 
-        return null;
+        return .None;
     }
 
     pub fn deinit(self: *Self) void {

src/core/bus/io.zig

@@ -80,6 +80,8 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) ?T {
             0x0400_000E => bus.ppu.bg[3].cnt.raw,
             0x0400_004C => util.io.read.todo(log, "Read {} from MOSAIC", .{T}),
             0x0400_0050 => bus.ppu.bldcnt.raw,
+            0x0400_0052 => bus.ppu.bldalpha.raw,
+            0x0400_0054 => bus.ppu.bldy.raw,
 
             // Sound
             0x0400_0060...0x0400_009E => apu.read(T, &bus.apu, address),

src/core/cpu.zig

@@ -243,6 +243,7 @@ pub const Arm7tdmi = struct {
     const Self = @This();
 
     r: [16]u32,
+    pipe: Pipline,
     sched: *Scheduler,
     bus: *Bus,
     cpsr: PSR,
@@ -263,6 +264,7 @@ pub const Arm7tdmi = struct {
     pub fn init(sched: *Scheduler, bus: *Bus, log_file: ?std.fs.File) Self {
         return Self{
             .r = [_]u32{0x00} ** 16,
+            .pipe = Pipline.init(),
             .sched = sched,
             .bus = bus,
             .cpsr = .{ .raw = 0x0000_001F },
@@ -322,8 +324,21 @@ pub const Arm7tdmi = struct {
         return self.bus.io.haltcnt == .Halt;
     }
 
+    pub fn setCpsrNoFlush(self: *Self, value: u32) void {
+        if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+        self.cpsr.raw = value;
+    }
+
     pub fn setCpsr(self: *Self, value: u32) void {
         if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+
+        const new: PSR = .{ .raw = value };
+        if (self.cpsr.t.read() != new.t.read()) {
+            // If THUMB to ARM or ARM to THUMB, flush pipeline
+            self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
+            if (new.t.read()) self.pipe.reload(u16, self) else self.pipe.reload(u32, self);
+        }
+
         self.cpsr.raw = value;
     }
 
@@ -414,31 +429,35 @@ pub const Arm7tdmi = struct {
     pub fn fastBoot(self: *Self) void {
         self.r = std.mem.zeroes([16]u32);
 
-        self.r[0] = 0x08000000;
-        self.r[1] = 0x000000EA;
+        // self.r[0] = 0x08000000;
+        // self.r[1] = 0x000000EA;
         self.r[13] = 0x0300_7F00;
         self.r[15] = 0x0800_0000;
 
         self.banked_r[bankedIdx(.Irq, .R13)] = 0x0300_7FA0;
         self.banked_r[bankedIdx(.Supervisor, .R13)] = 0x0300_7FE0;
 
-        self.cpsr.raw = 0x6000001F;
+        // self.cpsr.raw = 0x6000001F;
+        self.cpsr.raw = 0x0000_001F;
     }
 
     pub fn step(self: *Self) void {
-        if (self.cpsr.t.read()) {
-            const opcode = self.fetch(u16);
+        if (self.cpsr.t.read()) blk: {
+            const opcode = @truncate(u16, self.pipe.step(self, u16) orelse break :blk);
             if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
 
             thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
-        } else {
-            const opcode = self.fetch(u32);
+        } else blk: {
+            const opcode = self.pipe.step(self, u32) orelse break :blk;
             if (cpu_logging) self.logger.?.mgbaLog(self, opcode);
 
             if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
                 arm.lut[arm.idx(opcode)](self, self.bus, opcode);
             }
         }
+
+        if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        self.pipe.flushed = false;
     }
 
     pub fn stepDmaTransfer(self: *Self) bool {
@@ -473,27 +492,26 @@ pub const Arm7tdmi = struct {
     pub fn handleInterrupt(self: *Self) void {
         const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw;
 
-        if (should_handle != 0) {
+        // Return if IME is disabled, CPSR I is set or there is nothing to handle
+        if (!self.bus.io.ime or self.cpsr.i.read() or should_handle == 0) return;
+
+        // If pipeline isn't full, return but reschedule the handling of the event
+        if (!self.pipe.isFull()) return;
+
+        // log.debug("Handling Interrupt!", .{});
         self.bus.io.haltcnt = .Execute;
-            // log.debug("An Interrupt was Fired!", .{});
 
-            // Either IME is not true or I in CPSR is true
-            // Don't handle interrupts
-            if (!self.bus.io.ime or self.cpsr.i.read()) return;
-            // log.debug("An interrupt was Handled!", .{});
-
-            // retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode
-            const r15 = self.r[15] + 4;
-            const cpsr = self.cpsr.raw;
+        const ret_addr = self.r[15] - if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        const new_spsr = self.cpsr.raw;
 
         self.changeMode(.Irq);
         self.cpsr.t.write(false);
         self.cpsr.i.write(true);
 
-            self.r[14] = r15;
-            self.spsr.raw = cpsr;
-            self.r[15] = 0x000_0018;
-        }
+        self.r[14] = ret_addr;
+        self.spsr.raw = new_spsr;
+        self.r[15] = 0x0000_0018;
+        self.pipe.reload(u32, self);
     }
 
     inline fn fetch(self: *Self, comptime T: type) T {
@@ -507,8 +525,12 @@ pub const Arm7tdmi = struct {
         return self.bus.read(T, self.r[15]);
     }
 
-    pub fn fakePC(self: *const Self) u32 {
-        return self.r[15] + 4;
+    fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
+        if (self.binary_log) {
+            self.skyLog(file) catch unreachable;
+        } else {
+            self.mgbaLog(file, opcode) catch unreachable;
+        }
     }
 
     pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
@@ -525,6 +547,8 @@ pub const Arm7tdmi = struct {
         std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
         prettyPrintPsr(&self.spsr);
 
+        std.debug.print("pipeline: {??X:0>8}\n", .{self.pipe.stage});
+
         if (self.cpsr.t.read()) {
             const opcode = self.bus.dbgRead(u16, self.r[15] - 4);
             const id = thumb.idx(opcode);
@@ -588,7 +612,7 @@ pub const Arm7tdmi = struct {
         const r12 = self.r[12];
         const r13 = self.r[13];
         const r14 = self.r[14];
-        const r15 = self.r[15];
+        const r15 = self.r[15] -| if (self.cpsr.t.read()) 2 else @as(u32, 4);
 
         const c_psr = self.cpsr.raw;
 
@@ -596,7 +620,7 @@ pub const Arm7tdmi = struct {
         if (self.cpsr.t.read()) {
             if (opcode >> 11 == 0x1E) {
                 // Instruction 1 of a BL Opcode, print in ARM mode
-                const other_half = self.bus.dbgRead(u16, self.r[15]);
+                const other_half = self.bus.debugRead(u16, self.r[15] - 2);
                 const bl_opcode = @as(u32, opcode) << 16 | other_half;
 
                 log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
@@ -632,6 +656,59 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
     };
 }
 
+const Pipline = struct {
+    const Self = @This();
+    stage: [2]?u32,
+    flushed: bool,
+
+    fn init() Self {
+        return .{
+            .stage = [_]?u32{null} ** 2,
+            .flushed = false,
+        };
+    }
+
+    pub fn flush(self: *Self) void {
+        for (self.stage) |*opcode| opcode.* = null;
+        self.flushed = true;
+
+        // Note: If using this, add
+        // if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        // to the end of Arm7tdmi.step
+    }
+
+    pub fn isFull(self: *const Self) bool {
+        return self.stage[0] != null and self.stage[1] != null;
+    }
+
+    pub fn step(self: *Self, cpu: *Arm7tdmi, comptime T: type) ?u32 {
+        comptime std.debug.assert(T == u32 or T == u16);
+
+        // FIXME: https://github.com/ziglang/zig/issues/12642
+        const opcode = self.stage[0..1][0];
+
+        self.stage[0] = self.stage[1];
+        self.stage[1] = cpu.bus.read(T, cpu.r[15]);
+
+        return opcode;
+    }
+
+    pub fn reload(self: *Self, comptime T: type, cpu: *Arm7tdmi) void {
+        comptime std.debug.assert(T == u32 or T == u16);
+
+        // Sometimes, the pipeline can be reloaded twice in the same instruction
+        // This can happen if:
+        // 1. R15 is written to
+        // 2. The CPSR is written to (and T changes), so R15 is written to again
+
+        self.stage[0] = cpu.bus.read(T, cpu.r[15]);
+        self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
+
+        cpu.r[15] += if (T == u32) 8 else @as(u32, 4);
+        self.flushed = true;
+    }
+};
+
 pub const PSR = extern union {
     mode: Bitfield(u32, 0, 5),
     t: Bit(u32, 5),

src/core/cpu/arm/block_data_transfer.zig

@@ -55,8 +55,10 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
 
                 if (L) {
                     cpu.r[15] = bus.read(u32, und_addr);
+                    cpu.pipe.reload(u32, cpu);
                 } else {
-                    bus.write(u32, und_addr, cpu.r[15] + 8);
+                    // FIXME: Should r15 on write be +12 ahead?
+                    bus.write(u32, und_addr, cpu.r[15] + 4);
                 }
 
                 cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
@@ -86,17 +88,23 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
                     cpu.setUserModeRegister(i, bus.read(u32, address));
                 } else {
                     const value = bus.read(u32, address);
-                    cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
-                    if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
+
+                    cpu.r[i] = value;
+                    if (i == 0xF) {
+                        cpu.r[i] &= ~@as(u32, 3); // Align r15
+                        cpu.pipe.reload(u32, cpu);
+
+                        if (S) cpu.setCpsr(cpu.spsr.raw);
+                    }
                 }
             } else {
                 if (S) {
                     // Always Transfer User mode Registers
                     // This happens regardless if r15 is in the list
                     const value = cpu.getUserModeRegister(i);
-                    bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
+                    bus.write(u32, address, value + if (i == 0xF) 4 else @as(u32, 0)); // PC is already 8 ahead to make 12
                 } else {
-                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
+                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 4 else @as(u32, 0));
                 }
             }
         }

src/core/cpu/arm/branch.zig

@@ -9,14 +9,20 @@ const sext = @import("../../util.zig").sext;
 pub fn branch(comptime L: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
-            if (L) cpu.r[14] = cpu.r[15];
-            cpu.r[15] = cpu.fakePC() +% (sext(u32, u24, opcode) << 2);
+            if (L) cpu.r[14] = cpu.r[15] - 4;
+
+            cpu.r[15] +%= sext(u32, u24, opcode) << 2;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }
 
 pub fn branchAndExchange(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
     const rn = opcode & 0xF;
-    cpu.cpsr.t.write(cpu.r[rn] & 1 == 1);
-    cpu.r[15] = cpu.r[rn] & 0xFFFF_FFFE;
+
+    const thumb = cpu.r[rn] & 1 == 1;
+    cpu.r[15] = cpu.r[rn] & if (thumb) ~@as(u32, 1) else ~@as(u32, 3);
+
+    cpu.cpsr.t.write(thumb);
+    if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
 }

src/core/cpu/arm/data_processing.zig

@@ -5,7 +5,7 @@ const InstrFn = @import("../../cpu.zig").arm.InstrFn;
 const rotateRight = @import("../barrel_shifter.zig").rotateRight;
 const execute = @import("../barrel_shifter.zig").execute;
 
-pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
             const rd = @truncate(u4, opcode >> 12 & 0xF);
@@ -13,124 +13,276 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
             const old_carry = @boolToInt(cpu.cpsr.c.read());
 
             // If certain conditions are met, PC is 12 ahead instead of 8
+            // TODO: Why these conditions?
             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
+            const op1 = cpu.r[rn];
 
-            const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn];
-
-            var op2: u32 = undefined;
-            if (I) {
             const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
-                op2 = rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount);
-            } else {
-                op2 = execute(S, cpu, opcode);
-            }
+            const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
 
             // Undo special condition from above
             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
 
-            switch (instrKind) {
-                0x0 => {
-                    // AND
-                    const result = op1 & op2;
-                    cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
-                },
-                0x1 => {
-                    // EOR
-                    const result = op1 ^ op2;
-                    cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
-                },
-                0x2 => {
-                    // SUB
-                    cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
-                },
-                0x3 => {
-                    // RSB
-                    cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
-                },
-                0x4 => {
-                    // ADD
-                    cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
-                },
-                0x5 => {
-                    // ADC
-                    cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
-                },
-                0x6 => {
-                    // SBC
-                    cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
-                },
-                0x7 => {
-                    // RSC
-                    cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
-                },
+            var result: u32 = undefined;
+            var didOverflow: bool = undefined;
+
+            // Perform Data Processing Logic
+            switch (kind) {
+                0x0 => result = op1 & op2, // AND
+                0x1 => result = op1 ^ op2, // EOR
+                0x2 => result = op1 -% op2, // SUB
+                0x3 => result = op2 -% op1, // RSB
+                0x4 => result = newAdd(&didOverflow, op1, op2), // ADD
+                0x5 => result = newAdc(&didOverflow, op1, op2, old_carry), // ADC
+                0x6 => result = newSbc(op1, op2, old_carry), // SBC
+                0x7 => result = newSbc(op2, op1, old_carry), // RSC
                 0x8 => {
                     // TST
-                    if (rd == 0xF) {
-                        undefinedTestBehaviour(cpu);
-                        return;
-                    }
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
 
-                    const result = op1 & op2;
-                    setTestOpFlags(S, cpu, opcode, result);
+                    result = op1 & op2;
                 },
                 0x9 => {
                     // TEQ
-                    if (rd == 0xF) {
-                        undefinedTestBehaviour(cpu);
-                        return;
-                    }
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
 
-                    const result = op1 ^ op2;
-                    setTestOpFlags(S, cpu, opcode, result);
+                    result = op1 ^ op2;
                 },
                 0xA => {
                     // CMP
-                    if (rd == 0xF) {
-                        undefinedTestBehaviour(cpu);
-                        return;
-                    }
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
 
-                    cmp(cpu, op1, op2);
+                    result = op1 -% op2;
                 },
                 0xB => {
                     // CMN
-                    if (rd == 0xF) {
-                        undefinedTestBehaviour(cpu);
-                        return;
+                    if (rd == 0xF)
+                        return undefinedTestBehaviour(cpu);
+
+                    didOverflow = @addWithOverflow(u32, op1, op2, &result);
+                },
+                0xC => result = op1 | op2, // ORR
+                0xD => result = op2, // MOV
+                0xE => result = op1 & ~op2, // BIC
+                0xF => result = ~op2, // MVN
             }
 
-                    cmn(cpu, op1, op2);
-                },
-                0xC => {
-                    // ORR
-                    const result = op1 | op2;
+            // Write to Destination Register
+            switch (kind) {
+                0x8, 0x9, 0xA, 0xB => {}, // Test Operations
+                else => {
                     cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                    if (rd == 0xF) cpu.pipe.reload(u32, cpu);
                 },
-                0xD => {
-                    // MOV
-                    cpu.r[rd] = op2;
-                    setArmLogicOpFlags(S, cpu, rd, op2);
+            }
+
+            // Write Flags
+            switch (kind) {
+                0x0, 0x1, 0xC, 0xD, 0xE, 0xF => {
+                    // Logic Operation Flags
+                    if (S) {
+                        if (rd == 0xF) {
+                            cpu.setCpsr(cpu.spsr.raw);
+                        } else {
+                            cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                            cpu.cpsr.z.write(result == 0);
+                            // C set by Barrel Shifter, V is unaffected
+                        }
+                    }
                 },
-                0xE => {
-                    // BIC
-                    const result = op1 & ~op2;
-                    cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                0x2, 0x3 => {
+                    // SUB, RSB Flags
+                    if (S) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+
+                        if (kind == 0x2) {
+                            // SUB specific
+                            cpu.cpsr.c.write(op2 <= op1);
+                            cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                        } else {
+                            // RSB Specific
+                            cpu.cpsr.c.write(op1 <= op2);
+                            cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                        }
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
                 },
-                0xF => {
-                    // MVN
-                    const result = ~op2;
-                    cpu.r[rd] = result;
-                    setArmLogicOpFlags(S, cpu, rd, result);
+                0x4, 0x5 => {
+                    // ADD, ADC Flags
+                    if (S) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+                        cpu.cpsr.c.write(didOverflow);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
+                },
+                0x6, 0x7 => {
+                    // SBC, RSC Flags
+                    if (S) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+
+                        if (kind == 0x6) {
+                            // SBC specific
+                            const subtrahend = @as(u64, op2) -% old_carry +% 1;
+                            cpu.cpsr.c.write(subtrahend <= op1);
+                            cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                        } else {
+                            // RSC Specific
+                            const subtrahend = @as(u64, op1) -% old_carry +% 1;
+                            cpu.cpsr.c.write(subtrahend <= op2);
+                            cpu.cpsr.v.write(((op2 ^ result) & (~op1 ^ result)) >> 31 & 1 == 1);
+                        }
+
+                        if (rd == 0xF) cpu.setCpsr(cpu.spsr.raw);
+                    }
+                },
+                0x8, 0x9, 0xA, 0xB => {
+                    // Test Operation Flags
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+
+                    if (kind == 0xA) {
+                        // CMP specific
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    } else if (kind == 0xB) {
+                        // CMN specific
+                        cpu.cpsr.c.write(didOverflow);
+                        cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1);
+                    } else {
+                        // TEST, TEQ specific
+                        // Barrel Shifter should always calc CPSR C in TST
+                        if (!S) _ = execute(true, cpu, opcode);
+                    }
                 },
             }
         }
     }.inner;
 }
 
+// pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
+//     return struct {
+//         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
+//             const rd = @truncate(u4, opcode >> 12 & 0xF);
+//             const rn = opcode >> 16 & 0xF;
+//             const old_carry = @boolToInt(cpu.cpsr.c.read());
+
+//             // If certain conditions are met, PC is 12 ahead instead of 8
+//             // TODO: What are these conditions? I can't remember
+//             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4;
+//             const op1 = cpu.r[rn];
+
+//             const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1);
+//             const op2 = if (I) rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount) else execute(S, cpu, opcode);
+
+//             // Undo special condition from above
+//             if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4;
+
+//             switch (instrKind) {
+//                 0x0 => {
+//                     // AND
+//                     const result = op1 & op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0x1 => {
+//                     // EOR
+//                     const result = op1 ^ op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0x2 => {
+//                     // SUB
+//                     cpu.r[rd] = armSub(S, cpu, rd, op1, op2);
+//                 },
+//                 0x3 => {
+//                     // RSB
+//                     cpu.r[rd] = armSub(S, cpu, rd, op2, op1);
+//                 },
+//                 0x4 => {
+//                     // ADD
+//                     cpu.r[rd] = armAdd(S, cpu, rd, op1, op2);
+//                 },
+//                 0x5 => {
+//                     // ADC
+//                     cpu.r[rd] = armAdc(S, cpu, rd, op1, op2, old_carry);
+//                 },
+//                 0x6 => {
+//                     // SBC
+//                     cpu.r[rd] = armSbc(S, cpu, rd, op1, op2, old_carry);
+//                 },
+//                 0x7 => {
+//                     // RSC
+//                     cpu.r[rd] = armSbc(S, cpu, rd, op2, op1, old_carry);
+//                 },
+//                 0x8 => {
+//                     // TST
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     const result = op1 & op2;
+//                     setTestOpFlags(S, cpu, opcode, result);
+//                 },
+//                 0x9 => {
+//                     // TEQ
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     const result = op1 ^ op2;
+//                     setTestOpFlags(S, cpu, opcode, result);
+//                 },
+//                 0xA => {
+//                     // CMP
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     cmp(cpu, op1, op2);
+//                 },
+//                 0xB => {
+//                     // CMN
+//                     if (rd == 0xF)
+//                         return undefinedTestBehaviour(cpu);
+
+//                     cmn(cpu, op1, op2);
+//                 },
+//                 0xC => {
+//                     // ORR
+//                     const result = op1 | op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0xD => {
+//                     // MOV
+//                     cpu.r[rd] = op2;
+//                     setArmLogicOpFlags(S, cpu, rd, op2);
+//                 },
+//                 0xE => {
+//                     // BIC
+//                     const result = op1 & ~op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//                 0xF => {
+//                     // MVN
+//                     const result = ~op2;
+//                     cpu.r[rd] = result;
+//                     setArmLogicOpFlags(S, cpu, rd, result);
+//                 },
+//             }
+
+//             if (rd == 0xF) cpu.pipe.reload(u32, cpu);
+//         }
+//     }.inner;
+// }
+
 fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_carry: u1) u32 {
     var result: u32 = undefined;
     if (S and rd == 0xF) {
@@ -143,6 +295,14 @@ fn armSbc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
     return result;
 }
 
+fn newSbc(left: u32, right: u32, old_carry: u1) u32 {
+    // TODO: Make your own version (thanks peach.bot)
+    const subtrahend = @as(u64, right) -% old_carry +% 1;
+    const ret = @truncate(u32, left -% subtrahend);
+
+    return ret;
+}
+
 pub fn sbc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
     // TODO: Make your own version (thanks peach.bot)
     const subtrahend = @as(u64, right) -% old_carry +% 1;
@@ -195,6 +355,12 @@ fn armAdd(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32) u32 {
     return result;
 }
 
+fn newAdd(didOverflow: *bool, left: u32, right: u32) u32 {
+    var ret: u32 = undefined;
+    didOverflow.* = @addWithOverflow(u32, left, right, &ret);
+    return ret;
+}
+
 pub fn add(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32) u32 {
     var result: u32 = undefined;
     const didOverflow = @addWithOverflow(u32, left, right, &result);
@@ -221,6 +387,15 @@ fn armAdc(comptime S: bool, cpu: *Arm7tdmi, rd: u4, left: u32, right: u32, old_c
     return result;
 }
 
+fn newAdc(didOverflow: *bool, left: u32, right: u32, old_carry: u1) u32 {
+    var ret: u32 = undefined;
+    const did = @addWithOverflow(u32, left, right, &ret);
+    const overflow = @addWithOverflow(u32, ret, old_carry, &ret);
+
+    didOverflow.* = did or overflow;
+    return ret;
+}
+
 pub fn adc(comptime S: bool, cpu: *Arm7tdmi, left: u32, right: u32, old_carry: u1) u32 {
     var result: u32 = undefined;
     const did = @addWithOverflow(u32, left, right, &result);
@@ -280,5 +455,5 @@ fn setTestOpFlags(comptime S: bool, cpu: *Arm7tdmi, opcode: u32, result: u32) vo
 
 fn undefinedTestBehaviour(cpu: *Arm7tdmi) void {
     @setCold(true);
-    cpu.setCpsr(cpu.spsr.raw);
+    cpu.setCpsrNoFlush(cpu.spsr.raw);
 }

src/core/cpu/arm/half_signed_data_transfer.zig

@@ -15,20 +15,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
             const rm = opcode & 0xF;
             const imm_offset_high = opcode >> 8 & 0xF;
 
-            var base: u32 = undefined;
-            if (rn == 0xF) {
-                base = cpu.fakePC();
-                if (!L) base += 4;
-            } else {
-                base = cpu.r[rn];
-            }
-
-            var offset: u32 = undefined;
-            if (I) {
-                offset = imm_offset_high << 4 | rm;
-            } else {
-                offset = cpu.r[rm];
-            }
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
+            const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
 
             const modified_base = if (U) base +% offset else base -% offset;
             var address = if (P) modified_base else base;

src/core/cpu/arm/single_data_transfer.zig

@@ -14,13 +14,8 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
 
-            var base: u32 = undefined;
-            if (rn == 0xF) {
-                base = cpu.fakePC();
-                if (!L) base += 4; // Offset of 12
-            } else {
-                base = cpu.r[rn];
-            }
+            // rn is r15 and L is not set, the PC is 12 ahead
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
 
             const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
 
@@ -40,18 +35,26 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             } else {
                 if (B) {
                     // STRB
-                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
                     bus.write(u8, address, @truncate(u8, value));
                 } else {
                     // STR
-                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);
                     bus.write(u32, address, value);
                 }
             }
 
             address = modified_base;
-            if (W and P or !P) cpu.r[rn] = address;
-            if (L) cpu.r[rd] = result; // This emulates the LDR rd == rn behaviour
+            if (W and P or !P) {
+                cpu.r[rn] = address;
+                if (rn == 0xF) cpu.pipe.reload(u32, cpu);
+            }
+
+            if (L) {
+                // This emulates the LDR rd == rn behaviour
+                cpu.r[rd] = result;
+                if (rd == 0xF) cpu.pipe.reload(u32, cpu);
+            }
         }
     }.inner;
 }

src/core/cpu/arm/software_interrupt.zig

@@ -6,7 +6,7 @@ pub fn armSoftwareInterrupt() InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, _: u32) void {
             // Copy Values from Current Mode
-            const r15 = cpu.r[15];
+            const ret_addr = cpu.r[15] - 4;
             const cpsr = cpu.cpsr.raw;
 
             // Switch Mode
@@ -14,9 +14,10 @@ pub fn armSoftwareInterrupt() InstrFn {
             cpu.cpsr.t.write(false); // Force ARM Mode
             cpu.cpsr.i.write(true); // Disable normal interrupts
 
-            cpu.r[14] = r15; // Resume Execution
+            cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
             cpu.r[15] = 0x0000_0008;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }

src/core/cpu/barrel_shifter.zig

@@ -18,11 +18,9 @@ pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
 
 fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     const rs_idx = opcode >> 8 & 0xF;
+    const rm = cpu.r[opcode & 0xF];
     const rs = @truncate(u8, cpu.r[rs_idx]);
 
-    const rm_idx = opcode & 0xF;
-    const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
-
     return switch (@truncate(u2, opcode >> 5)) {
         0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
         0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
@@ -33,9 +31,7 @@ fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
 
 pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     const amount = @truncate(u8, opcode >> 7 & 0x1F);
-
-    const rm_idx = opcode & 0xF;
-    const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
+    const rm = cpu.r[opcode & 0xF];
 
     var result: u32 = undefined;
     if (amount == 0) {

src/core/cpu/thumb/block_data_transfer.zig

@@ -33,7 +33,8 @@ pub fn fmt14(comptime L: bool, comptime R: bool) InstrFn {
             if (R) {
                 if (L) {
                     const value = bus.read(u32, address);
-                    cpu.r[15] = value & 0xFFFF_FFFE;
+                    cpu.r[15] = value & ~@as(u32, 1);
+                    cpu.pipe.reload(u16, cpu);
                 } else {
                     bus.write(u32, address, cpu.r[14]);
                 }
@@ -52,7 +53,13 @@ pub fn fmt15(comptime L: bool, comptime rb: u3) InstrFn {
             const end_address = cpu.r[rb] + 4 * countRlist(opcode);
 
             if (opcode & 0xFF == 0) {
-                if (L) cpu.r[15] = bus.read(u32, address) else bus.write(u32, address, cpu.r[15] + 4);
+                if (L) {
+                    cpu.r[15] = bus.read(u32, address);
+                    cpu.pipe.reload(u16, cpu);
+                } else {
+                    bus.write(u32, address, cpu.r[15] + 2);
+                }
+
                 cpu.r[rb] += 0x40;
                 return;
             }

src/core/cpu/thumb/branch.zig

@@ -9,16 +9,13 @@ pub fn fmt16(comptime cond: u4) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
             // B
-            const offset = sext(u32, u8, opcode & 0xFF) << 1;
+            if (cond == 0xE or cond == 0xF)
+                cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
 
-            const should_execute = switch (cond) {
-                0xE, 0xF => cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond}),
-                else => checkCond(cpu.cpsr, cond),
-            };
+            if (!checkCond(cpu.cpsr, cond)) return;
 
-            if (should_execute) {
-                cpu.r[15] = (cpu.r[15] + 2) +% offset;
-            }
+            cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
+            cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -27,8 +24,8 @@ pub fn fmt18() InstrFn {
     return struct {
         // B but conditional
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
-            const offset = sext(u32, u11, opcode & 0x7FF) << 1;
-            cpu.r[15] = (cpu.r[15] + 2) +% offset;
+            cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
+            cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -41,13 +38,16 @@ pub fn fmt19(comptime is_low: bool) InstrFn {
 
             if (is_low) {
                 // Instruction 2
-                const old_pc = cpu.r[15];
+                const next_opcode = cpu.r[15] - 2;
 
                 cpu.r[15] = cpu.r[14] +% (offset << 1);
-                cpu.r[14] = old_pc | 1;
+                cpu.r[14] = next_opcode | 1;
+
+                cpu.pipe.reload(u16, cpu);
             } else {
                 // Instruction 1
-                cpu.r[14] = (cpu.r[15] + 2) +% (sext(u32, u11, offset) << 12);
+                const lr_offset = sext(u32, u11, offset) << 12;
+                cpu.r[14] = (cpu.r[15] +% lr_offset) & ~@as(u32, 1);
             }
         }
     }.inner;

src/core/cpu/thumb/data_processing.zig

@@ -10,8 +10,6 @@ const sub = @import("../arm/data_processing.zig").sub;
 const cmp = @import("../arm/data_processing.zig").cmp;
 const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags;
 
-const log = std.log.scoped(.Thumb1);
-
 pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
@@ -58,29 +56,38 @@ pub fn fmt1(comptime op: u2, comptime offset: u5) InstrFn {
 pub fn fmt5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
-            const src_idx = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
-            const dst_idx = @as(u4, h1) << 3 | (opcode & 0x7);
+            const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
+            const rd = @as(u4, h1) << 3 | (opcode & 0x7);
 
-            const src = if (src_idx == 0xF) (cpu.r[src_idx] + 2) & 0xFFFF_FFFE else cpu.r[src_idx];
-            const dst = if (dst_idx == 0xF) (cpu.r[dst_idx] + 2) & 0xFFFF_FFFE else cpu.r[dst_idx];
+            const rs_value = if (rs == 0xF) cpu.r[rs] & ~@as(u32, 1) else cpu.r[rs];
+            const rd_value = if (rd == 0xF) cpu.r[rd] & ~@as(u32, 1) else cpu.r[rd];
 
             switch (op) {
                 0b00 => {
                     // ADD
-                    const sum = add(false, cpu, dst, src);
-                    cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFE else sum;
+                    const sum = add(false, cpu, rd_value, rs_value);
+                    cpu.r[rd] = if (rd == 0xF) sum & ~@as(u32, 1) else sum;
                 },
-                0b01 => cmp(cpu, dst, src), // CMP
+                0b01 => cmp(cpu, rd_value, rs_value), // CMP
                 0b10 => {
                     // MOV
-                    cpu.r[dst_idx] = if (dst_idx == 0xF) src & 0xFFFF_FFFE else src;
+                    cpu.r[rd] = if (rd == 0xF) rs_value & ~@as(u32, 1) else rs_value;
                 },
                 0b11 => {
                     // BX
-                    cpu.cpsr.t.write(src & 1 == 1);
-                    cpu.r[15] = src & 0xFFFF_FFFE;
+                    const thumb = rs_value & 1 == 1;
+                    cpu.r[15] = rs_value & ~@as(u32, 1);
+
+                    cpu.cpsr.t.write(thumb);
+                    if (thumb) cpu.pipe.reload(u16, cpu) else cpu.pipe.reload(u32, cpu);
+
+                    // TODO: We shouldn't need to worry about the if statement
+                    // below, because in BX, rd SBZ (and H1 is guaranteed to be 0)
+                    return;
                 },
             }
+
+            if (rd == 0xF) cpu.pipe.reload(u16, cpu);
         }
     }.inner;
 }
@@ -133,10 +140,9 @@ pub fn fmt12(comptime isSP: bool, comptime rd: u3) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
             // ADD
-            const left = if (isSP) cpu.r[13] else (cpu.r[15] + 2) & 0xFFFF_FFFD;
+            const left = if (isSP) cpu.r[13] else cpu.r[15] & ~@as(u32, 2);
             const right = (opcode & 0xFF) << 2;
-            const result = left + right;
-            cpu.r[rd] = result;
+            cpu.r[rd] = left + right;
         }
     }.inner;
 }

src/core/cpu/thumb/data_transfer.zig

@@ -11,7 +11,9 @@ pub fn fmt6(comptime rd: u3) InstrFn {
         fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
             // LDR
             const offset = (opcode & 0xFF) << 2;
-            cpu.r[rd] = bus.read(u32, (cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
+
+            // Bit 1 of the PC intentionally ignored
+            cpu.r[rd] = bus.read(u32, (cpu.r[15] & ~@as(u32, 2)) + offset);
         }
     }.inner;
 }

src/core/cpu/thumb/software_interrupt.zig

@@ -6,7 +6,7 @@ pub fn fmt17() InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
             // Copy Values from Current Mode
-            const r15 = cpu.r[15];
+            const ret_addr = cpu.r[15] - 2;
             const cpsr = cpu.cpsr.raw;
 
             // Switch Mode
@@ -14,9 +14,10 @@ pub fn fmt17() InstrFn {
             cpu.cpsr.t.write(false); // Force ARM Mode
             cpu.cpsr.i.write(true); // Disable normal interrupts
 
-            cpu.r[14] = r15; // Resume Execution
+            cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
             cpu.r[15] = 0x0000_0008;
+            cpu.pipe.reload(u32, cpu);
         }
     }.inner;
 }

src/core/emu.zig

@@ -18,6 +18,7 @@ const sync_video: RunKind = .LimitedFPS; // Configure Video Sync
 pub const win_scale = 3; // 1x, 2x, 3x, etc. Window Scaling
 pub const cpu_logging = false; // Enable detailed CPU logging
 pub const allow_unhandled_io = true; // Only relevant in Debug Builds
+pub const force_rtc = false;
 
 // 228 Lines which consist of 308 dots (which are 4 cycles long)
 const cycles_per_frame: u64 = 228 * (308 * 4); //280896

src/core/scheduler.zig

@@ -2,6 +2,7 @@ const std = @import("std");
 
 const Bus = @import("Bus.zig");
 const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
+const Clock = @import("bus/GamePak.zig").Clock;
 
 const Order = std.math.Order;
 const PriorityQueue = std.PriorityQueue;
@@ -60,6 +61,13 @@ pub const Scheduler = struct {
                         3 => cpu.bus.apu.ch4.channelTimerOverflow(late),
                     }
                 },
+                .RealTimeClock => {
+                    const device = &cpu.bus.pak.gpio.device;
+                    if (device.kind != .Rtc or device.ptr == null) return;
+
+                    const clock = @ptrCast(*Clock, @alignCast(@alignOf(*Clock), device.ptr.?));
+                    clock.updateTime(late);
+                },
                 .FrameSequencer => cpu.bus.apu.tickFrameSequencer(late),
                 .SampleAudio => cpu.bus.apu.sampleAudio(late),
                 .HBlank => cpu.bus.ppu.handleHBlankEnd(cpu, late), // The end of a HBlank
@@ -118,4 +126,5 @@ pub const EventKind = union(enum) {
     SampleAudio,
     FrameSequencer,
     ApuChannel: u2,
+    RealTimeClock,
 };

src/core/util.zig

@@ -151,6 +151,7 @@ pub const Logger = struct {
 
     pub fn print(self: *Self, comptime format: []const u8, args: anytype) !void {
         try self.buf.writer().print(format, args);
+        try self.buf.flush(); // FIXME: On panics, whatever is in the buffer isn't written to file
     }
 
     pub fn mgbaLog(self: *Self, cpu: *const Arm7tdmi, opcode: u32) void {
@@ -190,7 +191,7 @@ pub const Logger = struct {
             cpu.r[12],
             cpu.r[13],
             cpu.r[14],
-            cpu.r[15],
+            cpu.r[15] - if (cpu.cpsr.t.read()) 2 else @as(u32, 4),
             cpu.cpsr.raw,
             opcode,
         };