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4 changed files with 20 additions and 17 deletions

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@ -203,7 +203,7 @@ pub const Apu = struct {
self.stream = SDL.SDL_NewAudioStream(SDL.AUDIO_F32, 2, @intCast(c_int, self.sampleRate()), SDL.AUDIO_F32, 2, host_sample_rate) orelse unreachable; self.stream = SDL.SDL_NewAudioStream(SDL.AUDIO_F32, 2, @intCast(c_int, self.sampleRate()), SDL.AUDIO_F32, 2, host_sample_rate) orelse unreachable;
} }
// while (SDL.SDL_AudioStreamAvailable(self.stream) > (@sizeOf(f32) * 2 * 0x800)) {} while (SDL.SDL_AudioStreamAvailable(self.stream) > (@sizeOf(f32) * 2 * 0x800)) {}
_ = SDL.SDL_AudioStreamPut(self.stream, &[2]f32{ left, right }, 2 * @sizeOf(f32)); _ = SDL.SDL_AudioStreamPut(self.stream, &[2]f32{ left, right }, 2 * @sizeOf(f32));
self.sched.push(.SampleAudio, self.sched.now() + self.sampleTicks() - late); self.sched.push(.SampleAudio, self.sched.now() + self.sampleTicks() - late);

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@ -1,4 +1,5 @@
const std = @import("std"); const std = @import("std");
const builtin = @import("builtin");
const Bit = @import("bitfield").Bit; const Bit = @import("bitfield").Bit;
const Bitfield = @import("bitfield").Bitfield; const Bitfield = @import("bitfield").Bitfield;
@ -6,8 +7,6 @@ const Bus = @import("../Bus.zig");
const DmaController = @import("dma.zig").DmaController; const DmaController = @import("dma.zig").DmaController;
const Scheduler = @import("../scheduler.zig").Scheduler; const Scheduler = @import("../scheduler.zig").Scheduler;
const panic_on_und_io: bool = false;
const log = std.log.scoped(.@"I/O"); const log = std.log.scoped(.@"I/O");
pub const Io = struct { pub const Io = struct {
@ -61,7 +60,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
// Interrupts // Interrupts
0x0400_0200 => @as(T, bus.io.irq.raw) << 16 | bus.io.ie.raw, 0x0400_0200 => @as(T, bus.io.irq.raw) << 16 | bus.io.ie.raw,
0x0400_0208 => @boolToInt(bus.io.ime), 0x0400_0208 => @boolToInt(bus.io.ime),
else => undRead("Tried to read {} from 0x{X:0>8}", .{ T, address }), else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
}, },
u16 => switch (address) { u16 => switch (address) {
// Display // Display
@ -103,7 +102,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
0x0400_0202 => bus.io.irq.raw, 0x0400_0202 => bus.io.irq.raw,
0x0400_0204 => unimplementedRead("Read halfword from WAITCNT", .{}), 0x0400_0204 => unimplementedRead("Read halfword from WAITCNT", .{}),
0x0400_0208 => @boolToInt(bus.io.ime), 0x0400_0208 => @boolToInt(bus.io.ime),
else => undRead("Tried to read {} from 0x{X:0>8}", .{ T, address }), else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
}, },
u8 => return switch (address) { u8 => return switch (address) {
// Display // Display
@ -127,7 +126,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
// Interrupts // Interrupts
0x0400_0200 => @truncate(T, bus.io.ie.raw), 0x0400_0200 => @truncate(T, bus.io.ie.raw),
0x0400_0300 => @enumToInt(bus.io.postflg), 0x0400_0300 => @enumToInt(bus.io.postflg),
else => undRead("Tried to read byte from 0x{X:0>8}", .{address}), else => undefinedRead("Tried to read {} from 0x{X:0>8}", .{ T, address }),
}, },
else => @compileError("I/O: Unsupported read width"), else => @compileError("I/O: Unsupported read width"),
}; };
@ -185,7 +184,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0200 => bus.io.setIrqs(value), 0x0400_0200 => bus.io.setIrqs(value),
0x0400_0204 => log.debug("Wrote 0x{X:0>8} to WAITCNT", .{value}), 0x0400_0204 => log.debug("Wrote 0x{X:0>8} to WAITCNT", .{value}),
0x0400_0208 => bus.io.ime = value & 1 == 1, 0x0400_0208 => bus.io.ime = value & 1 == 1,
else => undWrite("Tried to write {} 0x{X:0>8} to 0x{X:0>8}", .{ T, value, address }), else => undefinedWrite("Tried to write {} 0x{X:0>8} to 0x{X:0>8}", .{ T, value, address }),
}, },
u16 => switch (address) { u16 => switch (address) {
// Display // Display
@ -317,7 +316,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0204 => log.debug("Wrote 0x{X:0>4} to WAITCNT", .{value}), 0x0400_0204 => log.debug("Wrote 0x{X:0>4} to WAITCNT", .{value}),
0x0400_0208 => bus.io.ime = value & 1 == 1, 0x0400_0208 => bus.io.ime = value & 1 == 1,
0x0400_0206, 0x0400_020A => {}, // Not Used 0x0400_0206, 0x0400_020A => {}, // Not Used
else => undWrite("Tried to write {} 0x{X:0>4} to 0x{X:0>8}", .{ T, value, address }), else => undefinedWrite("Tried to write {} 0x{X:0>4} to 0x{X:0>8}", .{ T, value, address }),
}, },
u8 => switch (address) { u8 => switch (address) {
// Display // Display
@ -362,24 +361,29 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
// Interrupts // Interrupts
0x0400_0208 => bus.io.ime = value & 1 == 1, 0x0400_0208 => bus.io.ime = value & 1 == 1,
0x0400_0301 => bus.io.haltcnt = if (value >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}), 0x0400_0301 => bus.io.haltcnt = if (value >> 7 & 1 == 0) .Halt else std.debug.panic("TODO: Implement STOP", .{}),
else => undWrite("Tried to write 0x{X:0>2} to 0x{X:0>8}", .{ value, address }), else => undefinedWrite("Tried to write {} 0x{X:0>2} to 0x{X:0>8}", .{ T, value, address }),
}, },
else => @compileError("I/O: Unsupported write width"), else => @compileError("I/O: Unsupported write width"),
}; };
} }
fn undRead(comptime format: []const u8, args: anytype) u8 { fn undefinedRead(comptime format: []const u8, args: anytype) u8 {
if (panic_on_und_io) std.debug.panic(format, args) else log.warn(format, args); log.debug(format, args);
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
return 0; return 0;
} }
fn unimplementedRead(comptime format: []const u8, args: anytype) u8 { fn unimplementedRead(comptime format: []const u8, args: anytype) u8 {
log.warn(format, args); log.debug(format, args);
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
return 0; return 0;
} }
fn undWrite(comptime format: []const u8, args: anytype) void { fn undefinedWrite(comptime format: []const u8, args: anytype) void {
if (panic_on_und_io) std.debug.panic(format, args) else log.warn(format, args); log.debug(format, args);
if (builtin.mode == .Debug) std.debug.panic("TODO: Implement I/O Register", .{});
} }
/// Read / Write /// Read / Write

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@ -100,7 +100,7 @@ pub fn main() anyerror!void {
var emu_rate = FpsAverage.init(); var emu_rate = FpsAverage.init();
// Create Emulator Thread // Create Emulator Thread
const emu_thread = try Thread.spawn(.{}, emu.run, .{ .LimitedFPS, &quit, &emu_rate, &scheduler, &cpu }); const emu_thread = try Thread.spawn(.{}, emu.run, .{ .UnlimitedFPS, &quit, &emu_rate, &scheduler, &cpu });
defer emu_thread.join(); defer emu_thread.join();
var title_buf: [0x20]u8 = std.mem.zeroes([0x20]u8); var title_buf: [0x20]u8 = std.mem.zeroes([0x20]u8);
@ -267,5 +267,4 @@ fn initAudio(apu: *Apu) SDL.SDL_AudioDeviceID {
export fn audioCallback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void { export fn audioCallback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void {
const apu = @ptrCast(*Apu, @alignCast(8, userdata)); const apu = @ptrCast(*Apu, @alignCast(8, userdata));
_ = SDL.SDL_AudioStreamGet(apu.stream, stream, len); _ = SDL.SDL_AudioStreamGet(apu.stream, stream, len);
} }