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No commits in common. "3a51707280bcb35f3397c8a6da8441f95629bf07" and "2f74b61f2e898e683faee127e930149095fca509" have entirely different histories.
3a51707280
...
2f74b61f2e
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@ -30,7 +30,6 @@ pub const Io = struct {
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0x0400_0000 => @as(u32, self.dispcnt.raw),
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0x0400_0000 => @as(u32, self.dispcnt.raw),
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0x0400_0004 => @as(u32, self.dispstat.raw),
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0x0400_0004 => @as(u32, self.dispstat.raw),
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0x0400_0006 => @as(u32, self.vcount.raw),
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0x0400_0006 => @as(u32, self.vcount.raw),
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0x0400_0130 => @as(u32, self.keyinput.raw),
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0x0400_0200 => @as(u32, self.ie.raw),
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0x0400_0200 => @as(u32, self.ie.raw),
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0x0400_0208 => @boolToInt(self.ime),
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0x0400_0208 => @boolToInt(self.ime),
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else => std.debug.panic("[I/O:32] tried to read from {X:}", .{addr}),
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else => std.debug.panic("[I/O:32] tried to read from {X:}", .{addr}),
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252
src/cpu.zig
252
src/cpu.zig
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@ -120,7 +120,7 @@ pub const Arm7tdmi = struct {
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}
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}
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pub inline fn hasSPSR(self: *const Self) bool {
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pub inline fn hasSPSR(self: *const Self) bool {
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const mode = getModeChecked(self, self.cpsr.mode.read());
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const mode = getMode(self.cpsr.mode.read()) orelse unreachable;
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return switch (mode) {
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return switch (mode) {
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.System, .User => false,
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.System, .User => false,
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else => true,
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else => true,
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@ -128,7 +128,7 @@ pub const Arm7tdmi = struct {
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}
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}
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pub inline fn isPrivileged(self: *const Self) bool {
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pub inline fn isPrivileged(self: *const Self) bool {
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const mode = getModeChecked(self, self.cpsr.mode.read());
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const mode = getMode(self.cpsr.mode.read()) orelse unreachable;
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return switch (mode) {
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return switch (mode) {
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.User => false,
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.User => false,
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else => true,
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else => true,
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@ -141,11 +141,12 @@ pub const Arm7tdmi = struct {
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}
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}
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fn changeModeFromIdx(self: *Self, next: u5) void {
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fn changeModeFromIdx(self: *Self, next: u5) void {
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self.changeMode(getModeChecked(self, next));
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const mode = getMode(next) orelse unreachable;
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self.changeMode(mode);
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}
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}
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pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
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pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
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const current = getModeChecked(self, self.cpsr.mode.read());
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const current = getMode(self.cpsr.mode.read()) orelse unreachable;
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if (idx < 8) {
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if (idx < 8) {
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self.r[idx] = value;
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self.r[idx] = value;
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@ -165,7 +166,7 @@ pub const Arm7tdmi = struct {
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}
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}
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pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
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pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
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const current = getModeChecked(self, self.cpsr.mode.read());
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const current = getMode(self.cpsr.mode.read()) orelse unreachable;
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var result: u32 = undefined;
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var result: u32 = undefined;
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if (idx < 8) {
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if (idx < 8) {
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@ -188,7 +189,7 @@ pub const Arm7tdmi = struct {
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}
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}
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pub fn changeMode(self: *Self, next: Mode) void {
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pub fn changeMode(self: *Self, next: Mode) void {
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const now = getModeChecked(self, self.cpsr.mode.read());
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const now = getMode(self.cpsr.mode.read()) orelse unreachable;
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// Bank R8 -> r12
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// Bank R8 -> r12
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var r: usize = 8;
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var r: usize = 8;
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@ -303,16 +304,6 @@ pub const Arm7tdmi = struct {
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std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
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std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
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prettyPrintPsr(&self.spsr);
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prettyPrintPsr(&self.spsr);
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if (self.cpsr.t.read()) {
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const opcode = self.bus.read16(self.r[15] - 4);
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const id = thumbIdx(opcode);
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std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
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} else {
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const opcode = self.bus.read32(self.r[15] - 4);
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const id = armIdx(opcode);
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std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
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}
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std.debug.print("tick: {}\n\n", .{self.sched.tick});
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std.debug.print("tick: {}\n\n", .{self.sched.tick});
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std.debug.panic(format, args);
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std.debug.panic(format, args);
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@ -441,97 +432,96 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
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fn thumbPopulate() [0x400]ThumbInstrFn {
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fn thumbPopulate() [0x400]ThumbInstrFn {
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return comptime {
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return comptime {
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@setEvalBranchQuota(5025); // This is exact
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@setEvalBranchQuota(0x5000);
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var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
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var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
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var i: usize = 0;
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var i: usize = 0;
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while (i < lut.len) : (i += 1) {
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while (i < lut.len) : (i += 1) {
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lut[i] = switch (@as(u3, i >> 7 & 0x7)) {
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if (i >> 4 & 0x3F == 0b010000) {
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0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
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const op = i & 0xF;
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const I = i >> 4 & 1 == 1;
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const is_sub = i >> 3 & 1 == 1;
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lut[i] = format4(op);
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const rn = i & 0x7;
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} else if (i >> 4 & 0x3F == 0b010001) {
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break :blk format2(I, is_sub, rn);
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} else blk: {
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const op = i >> 5 & 0x3;
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const offset = i & 0x1F;
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break :blk format1(op, offset);
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},
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0b001 => blk: {
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const op = i >> 5 & 0x3;
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const rd = i >> 2 & 0x7;
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break :blk format3(op, rd);
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},
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0b010 => switch (@as(u2, i >> 5 & 0x3)) {
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0b00 => if (i >> 4 & 1 == 1) blk: {
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const op = i >> 2 & 0x3;
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const op = i >> 2 & 0x3;
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const h1 = i >> 1 & 1;
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const h1 = i >> 1 & 1;
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const h2 = i & 1;
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const h2 = i & 1;
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break :blk format5(op, h1, h2);
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} else blk: {
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lut[i] = format5(op, h1, h2);
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const op = i & 0xF;
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} else if (i >> 5 & 0x1F == 0b00011) {
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break :blk format4(op);
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const I = i >> 4 & 1 == 1;
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},
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const is_sub = i >> 3 & 1 == 1;
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0b01 => blk: {
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const rn = i & 0x7;
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lut[i] = format2(I, is_sub, rn);
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} else if (i >> 5 & 0x1F == 0b01001) {
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const rd = i >> 2 & 0x7;
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const rd = i >> 2 & 0x7;
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break :blk format6(rd);
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},
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lut[i] = format6(rd);
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else => blk: {
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} else if (i >> 6 & 0xF == 0b0101) {
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const op = i >> 4 & 0x3;
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const op = i >> 4 & 0x3;
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const T = i >> 3 & 1 == 1;
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const T = i >> 3 & 1 == 1;
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break :blk format78(op, T);
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},
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lut[i] = format78(op, T);
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},
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} else if (i >> 7 & 0x7 == 0b000) {
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0b011 => blk: {
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const op = i >> 5 & 0x3;
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const offset = i & 0x1F;
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lut[i] = format1(op, offset);
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} else if (i >> 7 & 0x7 == 0b001) {
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const op = i >> 5 & 0x3;
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const rd = i >> 2 & 0x7;
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lut[i] = format3(op, rd);
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} else if (i >> 7 & 0x7 == 0b011) {
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const B = i >> 6 & 1 == 1;
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const B = i >> 6 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const offset = i & 0x1F;
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const offset = i & 0x1F;
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break :blk format9(B, L, offset);
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},
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lut[i] = format9(B, L, offset);
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else => switch (@as(u3, i >> 6 & 0x7)) {
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}
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// MSB is guaranteed to be 1
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0b000 => blk: {
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if (i >> 2 & 0xFF == 0xB0) {
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const S = i >> 1 & 1 == 1;
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lut[i] = format13(S);
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} else if (i >> 2 & 0xFF == 0xDF) {
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lut[i] = thumbSoftwareInterrupt();
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} else if (i >> 6 & 0xF == 0b1000) {
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const L = i >> 5 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const offset = i & 0x1F;
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const offset = i & 0x1F;
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break :blk format10(L, offset);
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},
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lut[i] = format10(L, offset);
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0b001 => blk: {
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} else if (i >> 6 & 0xF == 0b1001) {
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const L = i >> 5 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const rd = i >> 2 & 0x3;
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const rd = i >> 2 & 0x3;
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break :blk format11(L, rd);
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},
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lut[i] = format11(L, rd);
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0b010 => blk: {
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} else if (i >> 6 & 0xF == 0b1010) {
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const isSP = i >> 5 & 1 == 1;
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const isSP = i >> 5 & 1 == 1;
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const rd = i >> 2 & 0x7;
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const rd = i >> 2 & 0x7;
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break :blk format12(isSP, rd);
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},
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lut[i] = format12(isSP, rd);
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0b011 => if (i >> 4 & 1 == 1) blk: {
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} else if (i >> 6 & 0xF == 0b1011 and i >> 3 & 0x3 == 0b10) {
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const L = i >> 5 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const R = i >> 2 & 1 == 1;
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const R = i >> 2 & 1 == 1;
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break :blk format14(L, R);
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} else blk: {
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lut[i] = format14(L, R);
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const S = i >> 1 & 1 == 1;
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} else if (i >> 6 & 0xF == 0b1100) {
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break :blk format13(S);
|
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||||||
},
|
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||||||
0b100 => blk: {
|
|
||||||
const L = i >> 5 & 1 == 1;
|
const L = i >> 5 & 1 == 1;
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const rb = i >> 2 & 0x7;
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const rb = i >> 2 & 0x7;
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||||||
|
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||||||
break :blk format15(L, rb);
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lut[i] = format15(L, rb);
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},
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} else if (i >> 6 & 0xF == 0b1101) {
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0b101 => if (i >> 2 & 0xF == 0b1111) blk: {
|
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break :blk thumbSoftwareInterrupt();
|
|
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} else blk: {
|
|
||||||
const cond = i >> 2 & 0xF;
|
const cond = i >> 2 & 0xF;
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||||||
break :blk format16(cond);
|
|
||||||
},
|
lut[i] = format16(cond);
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||||||
0b110 => format18(),
|
} else if (i >> 5 & 0x1F == 0b11100) {
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||||||
0b111 => blk: {
|
lut[i] = format18();
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||||||
|
} else if (i >> 6 & 0xF == 0b1111) {
|
||||||
const is_low = i >> 5 & 1 == 1;
|
const is_low = i >> 5 & 1 == 1;
|
||||||
break :blk format19(is_low);
|
|
||||||
},
|
lut[i] = format19(is_low);
|
||||||
},
|
}
|
||||||
};
|
|
||||||
}
|
}
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||||||
|
|
||||||
return lut;
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return lut;
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|
@ -545,66 +535,92 @@ fn armPopulate() [0x1000]ArmInstrFn {
|
||||||
|
|
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var i: usize = 0;
|
var i: usize = 0;
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||||||
while (i < lut.len) : (i += 1) {
|
while (i < lut.len) : (i += 1) {
|
||||||
lut[i] = switch (@as(u2, i >> 10)) {
|
// Instructions with Opcode[27] == 0
|
||||||
0b00 => if (i == 0x121) blk: {
|
if (i == 0x121) {
|
||||||
break :blk branchAndExchange;
|
// Bits 27:20 and 7:4
|
||||||
} else if (i & 0xFCF == 0x009) blk: {
|
lut[i] = branchAndExchange;
|
||||||
|
} else if (i >> 6 & 0x3F == 0b000000 and i & 0xF == 0b1001) {
|
||||||
|
// Bits 27:22 and 7:4
|
||||||
const A = i >> 5 & 1 == 1;
|
const A = i >> 5 & 1 == 1;
|
||||||
const S = i >> 4 & 1 == 1;
|
const S = i >> 4 & 1 == 1;
|
||||||
break :blk multiply(A, S);
|
|
||||||
} else if (i & 0xFBF == 0x109) blk: {
|
lut[i] = multiply(A, S);
|
||||||
|
} else if (i >> 7 & 0x1F == 0b00010 and i >> 4 & 0x3 == 0b00 and i & 0xF == 0b1001) {
|
||||||
|
// Bits 27:23, 21:20 and 7:4
|
||||||
const B = i >> 6 & 1 == 1;
|
const B = i >> 6 & 1 == 1;
|
||||||
break :blk singleDataSwap(B);
|
|
||||||
} else if (i & 0xF8F == 0x089) blk: {
|
lut[i] = singleDataSwap(B);
|
||||||
|
} else if (i >> 7 & 0x1F == 0b00001 and i & 0xF == 0b1001) {
|
||||||
|
// Bits 27:23 and bits 7:4
|
||||||
const U = i >> 6 & 1 == 1;
|
const U = i >> 6 & 1 == 1;
|
||||||
const A = i >> 5 & 1 == 1;
|
const A = i >> 5 & 1 == 1;
|
||||||
const S = i >> 4 & 1 == 1;
|
const S = i >> 4 & 1 == 1;
|
||||||
break :blk multiplyLong(U, A, S);
|
|
||||||
} else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: {
|
lut[i] = multiplyLong(U, A, S);
|
||||||
|
} else if (i >> 9 & 0x7 == 0b000 and i >> 3 & 1 == 1 and i & 1 == 1) {
|
||||||
|
// Bits 27:25, 7 and 4
|
||||||
const P = i >> 8 & 1 == 1;
|
const P = i >> 8 & 1 == 1;
|
||||||
const U = i >> 7 & 1 == 1;
|
const U = i >> 7 & 1 == 1;
|
||||||
const I = i >> 6 & 1 == 1;
|
const I = i >> 6 & 1 == 1;
|
||||||
const W = i >> 5 & 1 == 1;
|
const W = i >> 5 & 1 == 1;
|
||||||
const L = i >> 4 & 1 == 1;
|
const L = i >> 4 & 1 == 1;
|
||||||
break :blk halfAndSignedDataTransfer(P, U, I, W, L);
|
|
||||||
} else if (i & 0xD90 == 0x100) blk: {
|
lut[i] = halfAndSignedDataTransfer(P, U, I, W, L);
|
||||||
|
} else if (i >> 9 & 0x7 == 0b011 and i & 1 == 1) {
|
||||||
|
// Bits 27:25 and 4
|
||||||
|
lut[i] = armUndefined;
|
||||||
|
} else if (i >> 10 & 0x3 == 0b00 and i >> 7 & 0x3 == 0b10 and i >> 4 & 1 == 0) {
|
||||||
|
// Bits 27:26, 24:23 and 20
|
||||||
const I = i >> 9 & 1 == 1;
|
const I = i >> 9 & 1 == 1;
|
||||||
const R = i >> 6 & 1 == 1;
|
const R = i >> 6 & 1 == 1;
|
||||||
const kind = i >> 4 & 0x3;
|
const kind = i >> 4 & 0x3;
|
||||||
break :blk psrTransfer(I, R, kind);
|
|
||||||
} else blk: {
|
lut[i] = psrTransfer(I, R, kind);
|
||||||
const I = i >> 9 & 1 == 1;
|
} else if (i >> 10 & 0x3 == 0b01) {
|
||||||
const S = i >> 4 & 1 == 1;
|
// Bits 27:26
|
||||||
const instrKind = i >> 5 & 0xF;
|
|
||||||
break :blk dataProcessing(I, S, instrKind);
|
|
||||||
},
|
|
||||||
0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) armUndefined else blk: {
|
|
||||||
const I = i >> 9 & 1 == 1;
|
const I = i >> 9 & 1 == 1;
|
||||||
const P = i >> 8 & 1 == 1;
|
const P = i >> 8 & 1 == 1;
|
||||||
const U = i >> 7 & 1 == 1;
|
const U = i >> 7 & 1 == 1;
|
||||||
const B = i >> 6 & 1 == 1;
|
const B = i >> 6 & 1 == 1;
|
||||||
const W = i >> 5 & 1 == 1;
|
const W = i >> 5 & 1 == 1;
|
||||||
const L = i >> 4 & 1 == 1;
|
const L = i >> 4 & 1 == 1;
|
||||||
break :blk singleDataTransfer(I, P, U, B, W, L);
|
|
||||||
},
|
lut[i] = singleDataTransfer(I, P, U, B, W, L);
|
||||||
else => switch (@as(u2, i >> 9 & 0x3)) {
|
} else if (i >> 10 & 0x3 == 0b00) {
|
||||||
// MSB is guaranteed to be 1
|
// Bits 27:26
|
||||||
0b00 => blk: {
|
const I = i >> 9 & 1 == 1;
|
||||||
|
const S = i >> 4 & 1 == 1;
|
||||||
|
const instrKind = i >> 5 & 0xF;
|
||||||
|
|
||||||
|
lut[i] = dataProcessing(I, S, instrKind);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Instructions with Opcode[27] == 1
|
||||||
|
if (i >> 8 & 0xF == 0b1110) {
|
||||||
|
// bits 27:24
|
||||||
|
// Coprocessor Data Opertation + Register Transfer
|
||||||
|
lut[i] = armUndefined;
|
||||||
|
} else if (i >> 9 & 0x7 == 0b100) {
|
||||||
|
// Bits 27:25
|
||||||
const P = i >> 8 & 1 == 1;
|
const P = i >> 8 & 1 == 1;
|
||||||
const U = i >> 7 & 1 == 1;
|
const U = i >> 7 & 1 == 1;
|
||||||
const S = i >> 6 & 1 == 1;
|
const S = i >> 6 & 1 == 1;
|
||||||
const W = i >> 5 & 1 == 1;
|
const W = i >> 5 & 1 == 1;
|
||||||
const L = i >> 4 & 1 == 1;
|
const L = i >> 4 & 1 == 1;
|
||||||
break :blk blockDataTransfer(P, U, S, W, L);
|
|
||||||
},
|
lut[i] = blockDataTransfer(P, U, S, W, L);
|
||||||
0b01 => blk: {
|
} else if (i >> 9 & 0x7 == 0b101) {
|
||||||
|
// Bits 27:25
|
||||||
const L = i >> 8 & 1 == 1;
|
const L = i >> 8 & 1 == 1;
|
||||||
break :blk branch(L);
|
lut[i] = branch(L);
|
||||||
},
|
} else if (i >> 9 & 0x7 == 0b110) {
|
||||||
0b10 => armUndefined, // COP Data Transfer
|
// Bits 27:25
|
||||||
0b11 => if (i >> 8 & 1 == 1) armSoftwareInterrupt() else armUndefined, // COP Data Operation + Register Transfer
|
// Coprocessor Data Transfer
|
||||||
},
|
lut[i] = armUndefined;
|
||||||
};
|
} else if (i >> 8 & 0xF == 0b1111) {
|
||||||
|
// Bits 27:24
|
||||||
|
lut[i] = armSoftwareInterrupt();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return lut;
|
return lut;
|
||||||
|
@ -633,14 +649,10 @@ const Mode = enum(u5) {
|
||||||
System = 0b11111,
|
System = 0b11111,
|
||||||
};
|
};
|
||||||
|
|
||||||
fn getMode(bits: u5) ?Mode {
|
pub fn getMode(bits: u5) ?Mode {
|
||||||
return std.meta.intToEnum(Mode, bits) catch null;
|
return std.meta.intToEnum(Mode, bits) catch null;
|
||||||
}
|
}
|
||||||
|
|
||||||
fn getModeChecked(cpu: *const Arm7tdmi, bits: u5) Mode {
|
|
||||||
return getMode(bits) orelse cpu.panic("[CPU|CPSR] 0b{b:0>5} is an invalid CPU mode", .{bits});
|
|
||||||
}
|
|
||||||
|
|
||||||
fn armUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
fn armUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
|
||||||
const id = armIdx(opcode);
|
const id = armIdx(opcode);
|
||||||
cpu.panic("[CPU:ARM] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
|
cpu.panic("[CPU:ARM] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });
|
||||||
|
|
Loading…
Reference in New Issue