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compare: paoda:3a51707280bcb35f3397c8a6da8441f95629bf07
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5 Commits
2f74b61f2e ... 3a51707280

Author SHA1 Message Date
Rekai Nyangadzayi Musuka 3a51707280 fix: allow for 32-bit reads to KEYINPUT 2022-02-05 13:47:05 -04:00
Rekai Nyangadzayi Musuka b4d20fb264 chore: refactor ARMv4 decoding 2022-02-05 13:46:55 -04:00
Rekai Nyangadzayi Musuka 746158043d chore: add more debug information to CPU panic method 2022-02-05 13:46:24 -04:00
Rekai Nyangadzayi Musuka 25300c8a9f chore: give more descriptive panic messages when changing mode fails 2022-02-04 16:54:57 -04:00
Rekai Nyangadzayi Musuka 27d0ba8c7e chore: clean up THUMB instruction decoding 2022-02-04 15:57:46 -04:00
2 changed files with 168 additions and 179 deletions
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1
src/bus/io.zig
View File

@ -30,6 +30,7 @@ pub const Io = struct {
0x0400_0000 => @as(u32, self.dispcnt.raw),
0x0400_0004 => @as(u32, self.dispstat.raw),
0x0400_0006 => @as(u32, self.vcount.raw),
0x0400_0130 => @as(u32, self.keyinput.raw),
0x0400_0200 => @as(u32, self.ie.raw),
0x0400_0208 => @boolToInt(self.ime),
else => std.debug.panic("[I/O:32] tried to read from {X:}", .{addr}),

346
src/cpu.zig
View File

@ -120,7 +120,7 @@ pub const Arm7tdmi = struct {
}
pub inline fn hasSPSR(self: *const Self) bool {
const mode = getMode(self.cpsr.mode.read()) orelse unreachable;
const mode = getModeChecked(self, self.cpsr.mode.read());
return switch (mode) {
.System, .User => false,
else => true,
@ -128,7 +128,7 @@ pub const Arm7tdmi = struct {
}
pub inline fn isPrivileged(self: *const Self) bool {
const mode = getMode(self.cpsr.mode.read()) orelse unreachable;
const mode = getModeChecked(self, self.cpsr.mode.read());
return switch (mode) {
.User => false,
else => true,
@ -141,12 +141,11 @@ pub const Arm7tdmi = struct {
}
fn changeModeFromIdx(self: *Self, next: u5) void {
const mode = getMode(next) orelse unreachable;
self.changeMode(mode);
self.changeMode(getModeChecked(self, next));
}
pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
const current = getMode(self.cpsr.mode.read()) orelse unreachable;
const current = getModeChecked(self, self.cpsr.mode.read());
if (idx < 8) {
self.r[idx] = value;
@ -166,7 +165,7 @@ pub const Arm7tdmi = struct {
}
pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
const current = getMode(self.cpsr.mode.read()) orelse unreachable;
const current = getModeChecked(self, self.cpsr.mode.read());
var result: u32 = undefined;
if (idx < 8) {
@ -189,7 +188,7 @@ pub const Arm7tdmi = struct {
}
pub fn changeMode(self: *Self, next: Mode) void {
const now = getMode(self.cpsr.mode.read()) orelse unreachable;
const now = getModeChecked(self, self.cpsr.mode.read());
// Bank R8 -> r12
var r: usize = 8;
@ -304,6 +303,16 @@ pub const Arm7tdmi = struct {
std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
prettyPrintPsr(&self.spsr);
if (self.cpsr.t.read()) {
const opcode = self.bus.read16(self.r[15] - 4);
const id = thumbIdx(opcode);
std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
} else {
const opcode = self.bus.read32(self.r[15] - 4);
const id = armIdx(opcode);
std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
}
std.debug.print("tick: {}\n\n", .{self.sched.tick});
std.debug.panic(format, args);
@ -432,96 +441,97 @@ pub fn checkCond(cpsr: PSR, cond: u4) bool {
fn thumbPopulate() [0x400]ThumbInstrFn {
return comptime {
@setEvalBranchQuota(0x5000);
@setEvalBranchQuota(5025); // This is exact
var lut = [_]ThumbInstrFn{thumbUndefined} ** 0x400;
var i: usize = 0;
while (i < lut.len) : (i += 1) {
if (i >> 4 & 0x3F == 0b010000) {
const op = i & 0xF;
lut[i] = switch (@as(u3, i >> 7 & 0x7)) {
0b000 => if (i >> 5 & 0x3 == 0b11) blk: {
const I = i >> 4 & 1 == 1;
const is_sub = i >> 3 & 1 == 1;
const rn = i & 0x7;
break :blk format2(I, is_sub, rn);
} else blk: {
const op = i >> 5 & 0x3;
const offset = i & 0x1F;
break :blk format1(op, offset);
},
0b001 => blk: {
const op = i >> 5 & 0x3;
const rd = i >> 2 & 0x7;
break :blk format3(op, rd);
},
0b010 => switch (@as(u2, i >> 5 & 0x3)) {
0b00 => if (i >> 4 & 1 == 1) blk: {
const op = i >> 2 & 0x3;
const h1 = i >> 1 & 1;
const h2 = i & 1;
break :blk format5(op, h1, h2);
} else blk: {
const op = i & 0xF;
break :blk format4(op);
},
0b01 => blk: {
const rd = i >> 2 & 0x7;
break :blk format6(rd);
},
else => blk: {
const op = i >> 4 & 0x3;
const T = i >> 3 & 1 == 1;
break :blk format78(op, T);
},
},
0b011 => blk: {
const B = i >> 6 & 1 == 1;
const L = i >> 5 & 1 == 1;
const offset = i & 0x1F;
break :blk format9(B, L, offset);
},
else => switch (@as(u3, i >> 6 & 0x7)) {
// MSB is guaranteed to be 1
0b000 => blk: {
const L = i >> 5 & 1 == 1;
const offset = i & 0x1F;
break :blk format10(L, offset);
},
0b001 => blk: {
const L = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x3;
break :blk format11(L, rd);
},
0b010 => blk: {
const isSP = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x7;
break :blk format12(isSP, rd);
},
0b011 => if (i >> 4 & 1 == 1) blk: {
const L = i >> 5 & 1 == 1;
const R = i >> 2 & 1 == 1;
break :blk format14(L, R);
} else blk: {
const S = i >> 1 & 1 == 1;
break :blk format13(S);
},
0b100 => blk: {
const L = i >> 5 & 1 == 1;
const rb = i >> 2 & 0x7;
lut[i] = format4(op);
} else if (i >> 4 & 0x3F == 0b010001) {
const op = i >> 2 & 0x3;
const h1 = i >> 1 & 1;
const h2 = i & 1;
lut[i] = format5(op, h1, h2);
} else if (i >> 5 & 0x1F == 0b00011) {
const I = i >> 4 & 1 == 1;
const is_sub = i >> 3 & 1 == 1;
const rn = i & 0x7;
lut[i] = format2(I, is_sub, rn);
} else if (i >> 5 & 0x1F == 0b01001) {
const rd = i >> 2 & 0x7;
lut[i] = format6(rd);
} else if (i >> 6 & 0xF == 0b0101) {
const op = i >> 4 & 0x3;
const T = i >> 3 & 1 == 1;
lut[i] = format78(op, T);
} else if (i >> 7 & 0x7 == 0b000) {
const op = i >> 5 & 0x3;
const offset = i & 0x1F;
lut[i] = format1(op, offset);
} else if (i >> 7 & 0x7 == 0b001) {
const op = i >> 5 & 0x3;
const rd = i >> 2 & 0x7;
lut[i] = format3(op, rd);
} else if (i >> 7 & 0x7 == 0b011) {
const B = i >> 6 & 1 == 1;
const L = i >> 5 & 1 == 1;
const offset = i & 0x1F;
lut[i] = format9(B, L, offset);
}
if (i >> 2 & 0xFF == 0xB0) {
const S = i >> 1 & 1 == 1;
lut[i] = format13(S);
} else if (i >> 2 & 0xFF == 0xDF) {
lut[i] = thumbSoftwareInterrupt();
} else if (i >> 6 & 0xF == 0b1000) {
const L = i >> 5 & 1 == 1;
const offset = i & 0x1F;
lut[i] = format10(L, offset);
} else if (i >> 6 & 0xF == 0b1001) {
const L = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x3;
lut[i] = format11(L, rd);
} else if (i >> 6 & 0xF == 0b1010) {
const isSP = i >> 5 & 1 == 1;
const rd = i >> 2 & 0x7;
lut[i] = format12(isSP, rd);
} else if (i >> 6 & 0xF == 0b1011 and i >> 3 & 0x3 == 0b10) {
const L = i >> 5 & 1 == 1;
const R = i >> 2 & 1 == 1;
lut[i] = format14(L, R);
} else if (i >> 6 & 0xF == 0b1100) {
const L = i >> 5 & 1 == 1;
const rb = i >> 2 & 0x7;
lut[i] = format15(L, rb);
} else if (i >> 6 & 0xF == 0b1101) {
const cond = i >> 2 & 0xF;
lut[i] = format16(cond);
} else if (i >> 5 & 0x1F == 0b11100) {
lut[i] = format18();
} else if (i >> 6 & 0xF == 0b1111) {
const is_low = i >> 5 & 1 == 1;
lut[i] = format19(is_low);
}
break :blk format15(L, rb);
},
0b101 => if (i >> 2 & 0xF == 0b1111) blk: {
break :blk thumbSoftwareInterrupt();
} else blk: {
const cond = i >> 2 & 0xF;
break :blk format16(cond);
},
0b110 => format18(),
0b111 => blk: {
const is_low = i >> 5 & 1 == 1;
break :blk format19(is_low);
},
},
};
}
return lut;
@ -535,92 +545,66 @@ fn armPopulate() [0x1000]ArmInstrFn {
var i: usize = 0;
while (i < lut.len) : (i += 1) {
// Instructions with Opcode[27] == 0
if (i == 0x121) {
// Bits 27:20 and 7:4
lut[i] = branchAndExchange;
} else if (i >> 6 & 0x3F == 0b000000 and i & 0xF == 0b1001) {
// Bits 27:22 and 7:4
const A = i >> 5 & 1 == 1;
const S = i >> 4 & 1 == 1;
lut[i] = multiply(A, S);
} else if (i >> 7 & 0x1F == 0b00010 and i >> 4 & 0x3 == 0b00 and i & 0xF == 0b1001) {
// Bits 27:23, 21:20 and 7:4
const B = i >> 6 & 1 == 1;
lut[i] = singleDataSwap(B);
} else if (i >> 7 & 0x1F == 0b00001 and i & 0xF == 0b1001) {
// Bits 27:23 and bits 7:4
const U = i >> 6 & 1 == 1;
const A = i >> 5 & 1 == 1;
const S = i >> 4 & 1 == 1;
lut[i] = multiplyLong(U, A, S);
} else if (i >> 9 & 0x7 == 0b000 and i >> 3 & 1 == 1 and i & 1 == 1) {
// Bits 27:25, 7 and 4
const P = i >> 8 & 1 == 1;
const U = i >> 7 & 1 == 1;
const I = i >> 6 & 1 == 1;
const W = i >> 5 & 1 == 1;
const L = i >> 4 & 1 == 1;
lut[i] = halfAndSignedDataTransfer(P, U, I, W, L);
} else if (i >> 9 & 0x7 == 0b011 and i & 1 == 1) {
// Bits 27:25 and 4
lut[i] = armUndefined;
} else if (i >> 10 & 0x3 == 0b00 and i >> 7 & 0x3 == 0b10 and i >> 4 & 1 == 0) {
// Bits 27:26, 24:23 and 20
const I = i >> 9 & 1 == 1;
const R = i >> 6 & 1 == 1;
const kind = i >> 4 & 0x3;
lut[i] = psrTransfer(I, R, kind);
} else if (i >> 10 & 0x3 == 0b01) {
// Bits 27:26
const I = i >> 9 & 1 == 1;
const P = i >> 8 & 1 == 1;
const U = i >> 7 & 1 == 1;
const B = i >> 6 & 1 == 1;
const W = i >> 5 & 1 == 1;
const L = i >> 4 & 1 == 1;
lut[i] = singleDataTransfer(I, P, U, B, W, L);
} else if (i >> 10 & 0x3 == 0b00) {
// Bits 27:26
const I = i >> 9 & 1 == 1;
const S = i >> 4 & 1 == 1;
const instrKind = i >> 5 & 0xF;
lut[i] = dataProcessing(I, S, instrKind);
}
// Instructions with Opcode[27] == 1
if (i >> 8 & 0xF == 0b1110) {
// bits 27:24
// Coprocessor Data Opertation + Register Transfer
lut[i] = armUndefined;
} else if (i >> 9 & 0x7 == 0b100) {
// Bits 27:25
const P = i >> 8 & 1 == 1;
const U = i >> 7 & 1 == 1;
const S = i >> 6 & 1 == 1;
const W = i >> 5 & 1 == 1;
const L = i >> 4 & 1 == 1;
lut[i] = blockDataTransfer(P, U, S, W, L);
} else if (i >> 9 & 0x7 == 0b101) {
// Bits 27:25
const L = i >> 8 & 1 == 1;
lut[i] = branch(L);
} else if (i >> 9 & 0x7 == 0b110) {
// Bits 27:25
// Coprocessor Data Transfer
lut[i] = armUndefined;
} else if (i >> 8 & 0xF == 0b1111) {
// Bits 27:24
lut[i] = armSoftwareInterrupt();
}
lut[i] = switch (@as(u2, i >> 10)) {
0b00 => if (i == 0x121) blk: {
break :blk branchAndExchange;
} else if (i & 0xFCF == 0x009) blk: {
const A = i >> 5 & 1 == 1;
const S = i >> 4 & 1 == 1;
break :blk multiply(A, S);
} else if (i & 0xFBF == 0x109) blk: {
const B = i >> 6 & 1 == 1;
break :blk singleDataSwap(B);
} else if (i & 0xF8F == 0x089) blk: {
const U = i >> 6 & 1 == 1;
const A = i >> 5 & 1 == 1;
const S = i >> 4 & 1 == 1;
break :blk multiplyLong(U, A, S);
} else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: {
const P = i >> 8 & 1 == 1;
const U = i >> 7 & 1 == 1;
const I = i >> 6 & 1 == 1;
const W = i >> 5 & 1 == 1;
const L = i >> 4 & 1 == 1;
break :blk halfAndSignedDataTransfer(P, U, I, W, L);
} else if (i & 0xD90 == 0x100) blk: {
const I = i >> 9 & 1 == 1;
const R = i >> 6 & 1 == 1;
const kind = i >> 4 & 0x3;
break :blk psrTransfer(I, R, kind);
} else blk: {
const I = i >> 9 & 1 == 1;
const S = i >> 4 & 1 == 1;
const instrKind = i >> 5 & 0xF;
break :blk dataProcessing(I, S, instrKind);
},
0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) armUndefined else blk: {
const I = i >> 9 & 1 == 1;
const P = i >> 8 & 1 == 1;
const U = i >> 7 & 1 == 1;
const B = i >> 6 & 1 == 1;
const W = i >> 5 & 1 == 1;
const L = i >> 4 & 1 == 1;
break :blk singleDataTransfer(I, P, U, B, W, L);
},
else => switch (@as(u2, i >> 9 & 0x3)) {
// MSB is guaranteed to be 1
0b00 => blk: {
const P = i >> 8 & 1 == 1;
const U = i >> 7 & 1 == 1;
const S = i >> 6 & 1 == 1;
const W = i >> 5 & 1 == 1;
const L = i >> 4 & 1 == 1;
break :blk blockDataTransfer(P, U, S, W, L);
},
0b01 => blk: {
const L = i >> 8 & 1 == 1;
break :blk branch(L);
},
0b10 => armUndefined, // COP Data Transfer
0b11 => if (i >> 8 & 1 == 1) armSoftwareInterrupt() else armUndefined, // COP Data Operation + Register Transfer
},
};
}
return lut;
@ -649,10 +633,14 @@ const Mode = enum(u5) {
System = 0b11111,
};
pub fn getMode(bits: u5) ?Mode {
fn getMode(bits: u5) ?Mode {
return std.meta.intToEnum(Mode, bits) catch null;
}
fn getModeChecked(cpu: *const Arm7tdmi, bits: u5) Mode {
return getMode(bits) orelse cpu.panic("[CPU|CPSR] 0b{b:0>5} is an invalid CPU mode", .{bits});
}
fn armUndefined(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
const id = armIdx(opcode);
cpu.panic("[CPU:ARM] ID: 0x{X:0>3} 0x{X:0>8} is an illegal opcode", .{ id, opcode });