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0ceba17139
...
2e4854c2ff
Author | SHA1 | Date |
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Rekai Nyangadzayi Musuka | 2e4854c2ff | |
Rekai Nyangadzayi Musuka | 85f0b13f4a |
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@ -35,6 +35,11 @@ pub fn DmaController(comptime id: u2) type {
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/// Internal. Word Count
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/// Internal. Word Count
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_word_count: if (id == 3) u16 else u14,
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_word_count: if (id == 3) u16 else u14,
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/// Some DMA Transfers are enabled during Hblank / VBlank and / or
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/// have delays. Thefore bit 15 of DMACNT isn't actually something
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/// we can use to control when we do or do not execute a step in a DMA Transfer
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enabled: bool,
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pub fn init() Self {
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pub fn init() Self {
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return .{
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return .{
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.id = id,
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.id = id,
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@ -47,6 +52,7 @@ pub fn DmaController(comptime id: u2) type {
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._sad = 0,
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._sad = 0,
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._dad = 0,
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._dad = 0,
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._word_count = 0,
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._word_count = 0,
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.enabled = false,
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};
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};
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}
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}
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@ -70,6 +76,9 @@ pub fn DmaController(comptime id: u2) type {
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self._sad = self.sad;
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self._sad = self.sad;
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self._dad = self.dad;
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self._dad = self.dad;
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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// Only a Start Timing of 00 has a DMA Transfer immediately begin
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self.enabled = new.start_timing.read() == 0b00;
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}
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}
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self.cnt.raw = halfword;
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self.cnt.raw = halfword;
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@ -80,7 +89,9 @@ pub fn DmaController(comptime id: u2) type {
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self.writeCntHigh(@truncate(u16, word >> 16));
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self.writeCntHigh(@truncate(u16, word >> 16));
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}
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}
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pub fn step(self: *Self, bus: *Bus) void {
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pub fn step(self: *Self, bus: *Bus) bool {
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if (!self.enabled or !self.cnt.enabled.read()) return false;
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const sad_adj = std.meta.intToEnum(Adjustment, self.cnt.sad_adj.read()) catch unreachable;
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const sad_adj = std.meta.intToEnum(Adjustment, self.cnt.sad_adj.read()) catch unreachable;
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const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
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const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
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@ -96,8 +107,8 @@ pub fn DmaController(comptime id: u2) type {
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}
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}
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switch (sad_adj) {
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switch (sad_adj) {
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.Increment => self._sad += offset,
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.Increment => self._sad +%= offset,
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.Decrement => self._sad -= offset,
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.Decrement => self._sad -%= offset,
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.Fixed => {},
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.Fixed => {},
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// TODO: Figure out correct behaviour on Illegal Source Addr Control Type
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// TODO: Figure out correct behaviour on Illegal Source Addr Control Type
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@ -105,14 +116,16 @@ pub fn DmaController(comptime id: u2) type {
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}
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}
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switch (dad_adj) {
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switch (dad_adj) {
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.Increment, .IncrementReload => self._dad += offset,
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.Increment, .IncrementReload => self._dad +%= offset,
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.Decrement => self._dad -= offset,
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.Decrement => self._dad -%= offset,
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.Fixed => {},
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.Fixed => {},
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}
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}
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self._word_count -= 1;
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self._word_count -= 1;
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if (self._word_count == 0) {
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if (self._word_count == 0) {
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if (!self.cnt.repeat.read()) {
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// If we're not repeating, Fire the IRQs and disable the DMA
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if (self.cnt.irq.read()) {
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if (self.cnt.irq.read()) {
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switch (id) {
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switch (id) {
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0 => bus.io.irq.dma0.set(),
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0 => bus.io.irq.dma0.set(),
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@ -121,16 +134,59 @@ pub fn DmaController(comptime id: u2) type {
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3 => bus.io.irq.dma0.set(),
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3 => bus.io.irq.dma0.set(),
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}
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}
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}
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}
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self.cnt.enabled.unset();
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self.cnt.enabled.unset();
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}
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}
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// We want to disable our internal enabled flag regardless of repeat
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// because we only want to step A DMA that repeats during it's specific
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// timing window
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self.enabled = false;
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}
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return true;
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}
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pub fn isBlocking(self: *const Self) bool {
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// A DMA Transfer is Blocking if it is Immediate
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return self.cnt.start_timing.read() == 0b00;
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}
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pub fn pollBlankingDma(self: *Self, comptime kind: DmaKind) void {
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if (self.enabled) return;
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switch (kind) {
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.HBlank => self.enabled = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b10,
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.VBlank => self.enabled = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
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.Immediate, .Special => {},
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}
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if (self.cnt.repeat.read() and self.enabled) {
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self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
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const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable;
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if (dad_adj == .IncrementReload) self._dad = self.dad;
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}
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}
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}
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};
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};
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}
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}
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pub fn pollBlankingDma(bus: *Bus, comptime kind: DmaKind) void {
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bus.io.dma0.pollBlankingDma(kind);
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bus.io.dma1.pollBlankingDma(kind);
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bus.io.dma2.pollBlankingDma(kind);
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bus.io.dma3.pollBlankingDma(kind);
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}
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const Adjustment = enum(u2) {
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const Adjustment = enum(u2) {
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Increment = 0,
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Increment = 0,
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Decrement = 1,
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Decrement = 1,
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Fixed = 2,
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Fixed = 2,
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IncrementReload = 3,
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IncrementReload = 3,
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};
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};
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const DmaKind = enum(u2) {
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Immediate = 0,
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HBlank,
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VBlank,
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Special,
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};
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28
src/cpu.zig
28
src/cpu.zig
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@ -296,30 +296,10 @@ pub const Arm7tdmi = struct {
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}
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}
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fn handleDMATransfers(self: *Self) bool {
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fn handleDMATransfers(self: *Self) bool {
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const dma0 = &self.bus.io.dma0;
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if (self.bus.io.dma0.step(self.bus)) return self.bus.io.dma0.isBlocking();
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const dma1 = &self.bus.io.dma1;
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if (self.bus.io.dma1.step(self.bus)) return self.bus.io.dma1.isBlocking();
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const dma2 = &self.bus.io.dma2;
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if (self.bus.io.dma2.step(self.bus)) return self.bus.io.dma2.isBlocking();
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const dma3 = &self.bus.io.dma3;
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if (self.bus.io.dma3.step(self.bus)) return self.bus.io.dma3.isBlocking();
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if (dma0.cnt.enabled.read() and dma0.cnt.start_timing.read() == 0) {
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dma0.step(self.bus);
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return true;
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}
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if (dma1.cnt.enabled.read() and dma1.cnt.start_timing.read() == 0) {
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dma1.step(self.bus);
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return true;
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}
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if (dma2.cnt.enabled.read() and dma2.cnt.start_timing.read() == 0) {
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dma2.step(self.bus);
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return true;
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}
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if (dma3.cnt.enabled.read() and dma3.cnt.start_timing.read() == 0) {
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dma3.step(self.bus);
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return true;
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}
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return false;
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return false;
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}
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}
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25
src/ppu.zig
25
src/ppu.zig
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@ -366,3 +366,28 @@ const ScreenEntry = extern union {
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palette_bank: Bitfield(u16, 12, 4),
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palette_bank: Bitfield(u16, 12, 4),
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raw: u16,
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raw: u16,
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};
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};
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const Attr0 = extern union {
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y: Bitfield(u16, 0, 8),
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rot_scaling: Bit(u16, 8), // This SBZ
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disabled: Bit(u16, 9),
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mode: Bitfield(u16, 10, 2),
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mosaic: Bit(u16, 12),
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is_8bpp: Bit(u16, 13),
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shape: Bit(u16, 14, 2),
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raw: u16,
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};
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const Attr1 = extern union {
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x: Bitfield(u16, 0, 9),
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h_flip: Bit(u16, 12),
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v_flip: Bit(u16, 13),
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size: Bitfield(u16, 14, 2),
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raw: u16,
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};
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const Attr2 = extern union {
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tile_id: Bitfield(u16, 0, 10),
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rel_prio: Bitfield(u16, 10, 2),
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pal_id: Bitfield(u16, 12, 3),
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};
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@ -1,5 +1,7 @@
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const std = @import("std");
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const std = @import("std");
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const pollBlankingDma = @import("bus/dma.zig").pollBlankingDma;
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const Bus = @import("Bus.zig");
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const Bus = @import("Bus.zig");
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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const Arm7tdmi = @import("cpu.zig").Arm7tdmi;
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@ -68,6 +70,9 @@ pub const Scheduler = struct {
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irq.vblank.set();
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irq.vblank.set();
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cpu.handleInterrupt();
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cpu.handleInterrupt();
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}
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}
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// See if Vblank DMA is present and not enabled
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pollBlankingDma(bus, .VBlank);
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}
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}
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if (scanline == 227) stat.vblank.unset();
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if (scanline == 227) stat.vblank.unset();
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@ -84,6 +89,9 @@ pub const Scheduler = struct {
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cpu.handleInterrupt();
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cpu.handleInterrupt();
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}
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}
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// See if Hblank DMA is present and not enabled
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pollBlankingDma(bus, .HBlank);
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bus.ppu.dispstat.hblank.set();
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bus.ppu.dispstat.hblank.set();
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self.push(.HBlank, self.tick + (68 * 4));
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self.push(.HBlank, self.tick + (68 * 4));
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},
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},
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@ -96,6 +104,9 @@ pub const Scheduler = struct {
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cpu.handleInterrupt();
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cpu.handleInterrupt();
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}
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}
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// See if Hblank DMA is present and not enabled
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pollBlankingDma(bus, .HBlank);
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bus.ppu.dispstat.hblank.set();
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bus.ppu.dispstat.hblank.set();
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self.push(.HBlank, self.tick + (68 * 4));
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self.push(.HBlank, self.tick + (68 * 4));
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},
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},
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