Rekai Nyangadzayi Musuka
|
99b686b2d7
|
fix(cpu): use barrel shifter in data processing immediates
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2022-10-21 05:11:58 -03:00 |
Rekai Nyangadzayi Musuka
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daad98bbfe
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feat(cpu): implement format 12 thumb instructions
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2022-10-21 05:11:57 -03:00 |
Rekai Nyangadzayi Musuka
|
2fb01577af
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feat(cpu): implement some already decoded format 3 instructions
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2022-10-21 05:11:57 -03:00 |
Rekai Nyangadzayi Musuka
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96d21f27a5
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feat(cpu): implement THUMB format 5 instructions
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2022-10-21 05:11:57 -03:00 |
Rekai Nyangadzayi Musuka
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793110f315
|
chore: mgba log now supports printing THUMB instructions
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2022-10-21 05:11:57 -03:00 |
Rekai Nyangadzayi Musuka
|
5ed5c5d52d
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feat(cpu): implement like 1 THUMB instruction
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2022-10-21 05:11:57 -03:00 |
Rekai Nyangadzayi Musuka
|
01385ee46b
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chore: distinguish between undefined ARM and THUMB instr
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2022-10-21 05:11:57 -03:00 |
Rekai Nyangadzayi Musuka
|
0eba3aca1f
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chore(cpu): lay groundwork for THUMB instruction decoding and execution
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2022-10-21 05:11:57 -03:00 |
Rekai Nyangadzayi Musuka
|
83a5370196
|
chore(cpu): refactor ARM functions to make room for THUMB
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2022-10-21 05:11:56 -03:00 |
Rekai Nyangadzayi Musuka
|
b0b6247f06
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fix(cpu): fix conditions for GT cond
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2022-10-21 05:11:56 -03:00 |
Rekai Nyangadzayi Musuka
|
2a33716166
|
fix(cpu): fix imm value calculation in MSR
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2022-10-21 05:11:56 -03:00 |
Rekai Nyangadzayi Musuka
|
9b26454c72
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fix(cpu): resolve off-by-one error when executing LDM
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2022-10-21 05:11:56 -03:00 |
Rekai Nyangadzayi Musuka
|
97b933d9ea
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feat(cpu): implement branch and exchange
If I want to continue with armwrestler, I'll have to implement
THUMB instructions now
|
2022-10-21 05:11:56 -03:00 |
Rekai Nyangadzayi Musuka
|
ff70aadfdb
|
fix(cpu): make Data Processing instructions r15-aware
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2022-10-21 05:11:55 -03:00 |
Rekai Nyangadzayi Musuka
|
ae53f92d40
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fix(cpu): make LDRH and STRH aware of r15
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2022-10-21 05:11:55 -03:00 |
Rekai Nyangadzayi Musuka
|
f51e1d3154
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fix(cpu): account for r15 in LDR and STR instructions
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2022-10-21 05:11:55 -03:00 |
Rekai Nyangadzayi Musuka
|
a21f94569f
|
fix(cpu): flip two branches in PSR Transfer execution
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2022-10-21 05:11:55 -03:00 |
Rekai Nyangadzayi Musuka
|
b9255bffe7
|
feat(cpu): implement MSR and MRS
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2022-10-21 05:11:55 -03:00 |
Rekai Nyangadzayi Musuka
|
e1f8400343
|
feat(cpu): stub PSR Transfer instructions
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2022-10-21 05:11:55 -03:00 |
Rekai Nyangadzayi Musuka
|
52493831cc
|
chore(io): implement IE and IME
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2022-10-21 05:11:54 -03:00 |
Rekai Nyangadzayi Musuka
|
00ba7afac4
|
chore: remove some magic constants
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2022-10-21 05:11:54 -03:00 |
Rekai Nyangadzayi Musuka
|
c703352ac3
|
Merge branch 'main' of ssh://musuka.dev:2222/paoda/zba
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2022-10-21 05:11:54 -03:00 |
Rekai Nyangadzayi Musuka
|
97e663febf
|
fix(bus): remove accidental recursion
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2022-10-21 05:11:54 -03:00 |
Rekai Nyangadzayi Musuka
|
3891b54f42
|
chore: ignores for building on windows
|
2022-10-21 05:11:54 -03:00 |
Rekai Nyangadzayi Musuka
|
9a5959e46c
|
fix(cpu): write results of ORR to destination register
|
2022-10-21 05:11:54 -03:00 |
Rekai Nyangadzayi Musuka
|
780c717409
|
feat(cpu): implement TEQ
|
2022-10-21 05:11:53 -03:00 |
Rekai Nyangadzayi Musuka
|
34c6df344d
|
feat(cpu): Implement ORR
|
2022-10-21 05:11:53 -03:00 |
Rekai Nyangadzayi Musuka
|
670347d4a0
|
feat(bus): implement IWRAM and EWRAM
|
2022-10-21 05:11:53 -03:00 |
Rekai Nyangadzayi Musuka
|
e0c4b3b407
|
fix(ppu): properly access Mode 4 palette
|
2022-10-21 05:11:53 -03:00 |
Rekai Nyangadzayi Musuka
|
cffffab8ea
|
feat(cpu): refactor LDM/STM
|
2022-10-21 05:11:53 -03:00 |
Rekai Nyangadzayi Musuka
|
527bd2889e
|
feat(cpu): implement LDM/STM
|
2022-10-21 05:11:53 -03:00 |
Rekai Nyangadzayi Musuka
|
15dc4ce03a
|
chore(io): DISPSTAT bits 3 and 4 better match GBATEK documentation
|
2022-10-21 05:11:52 -03:00 |
Rekai Nyangadzayi Musuka
|
4f629227ab
|
fix(cpu): fix off-by-word bug in BL
|
2022-10-21 05:11:52 -03:00 |
Rekai Nyangadzayi Musuka
|
caa799853e
|
feat(bus): have VCOUNT be addressable on the bus
|
2022-10-21 05:11:52 -03:00 |
Rekai Nyangadzayi Musuka
|
3590215d33
|
feat(ppu): implement Mode 4
Implementation is not tested. Pending on LDM and STM so that I can
run beeg.gba
|
2022-10-21 05:11:52 -03:00 |
Rekai Nyangadzayi Musuka
|
d6aafc61bd
|
chore(io): rename some io bitfield fields
|
2022-10-21 05:11:52 -03:00 |
Rekai Nyangadzayi Musuka
|
357211a4cc
|
chore: remove premature inlines
|
2022-10-21 05:11:52 -03:00 |
Rekai Nyangadzayi Musuka
|
c4c4332485
|
chore: add FPS counter
|
2022-10-21 05:11:51 -03:00 |
Rekai Nyangadzayi Musuka
|
2cec8d9f70
|
chore: improve code clarity
|
2022-10-21 05:11:51 -03:00 |
Rekai Nyangadzayi Musuka
|
8348d7c4bc
|
feat(ppu): improve timings + implement BG mode 3 bitmap
|
2022-10-21 05:11:51 -03:00 |
Rekai Nyangadzayi Musuka
|
c33068d831
|
fix: allocate framebuf on heap
|
2022-10-21 05:11:51 -03:00 |
Rekai Nyangadzayi Musuka
|
f28b963f9d
|
chore: add code for heap alloc of white texture
|
2022-10-21 05:11:51 -03:00 |
Rekai Nyangadzayi Musuka
|
7fc77f993f
|
chore(gui): switch from RGBA8888 to BGR5555 to match BG Mode 3
|
2022-10-21 05:11:51 -03:00 |
Rekai Nyangadzayi Musuka
|
0e0b21d8c3
|
feat: draw white texture using SDL2
|
2022-10-21 05:11:50 -03:00 |
Rekai Nyangadzayi Musuka
|
f3ad0eb3aa
|
fix(ppu): deallocate palette RAM on cleanup
|
2022-10-21 05:11:50 -03:00 |
Rekai Nyangadzayi Musuka
|
036b861b05
|
chore: code cleanup
|
2022-10-21 05:11:50 -03:00 |
Rekai Nyangadzayi Musuka
|
880546468c
|
chore(bus): refactor bus.zig
|
2022-10-21 05:11:50 -03:00 |
Rekai Nyangadzayi Musuka
|
1a9c9ba4cb
|
chore: refactor instruction exec code
|
2022-10-21 05:11:50 -03:00 |
Rekai Nyangadzayi Musuka
|
a9e7140a88
|
chore(io): alias @This() to Self in io.zig
|
2022-10-21 05:11:50 -03:00 |
Rekai Nyangadzayi Musuka
|
808633deb7
|
chore: refactor bios.zig and pak.zig
|
2022-10-21 05:11:49 -03:00 |