|  | 47fc96fe00 | feat(cpu): implement BIC | 2022-10-21 05:12:00 -03:00 |  | 
			
				
					|  | 4ac5ad42c6 | feat(cpu): implement EOR | 2022-10-21 05:12:00 -03:00 |  | 
			
				
					|  | c93153672f | feat(cpu): implement ADD | 2022-10-21 05:11:59 -03:00 |  | 
			
				
					|  | a46dd448f4 | feat(cpu): implement fix for ADC and implement SBC | 2022-10-21 05:11:59 -03:00 |  | 
			
				
					|  | 01f75112ce | chore(barrel_shifter): remove panic from ASR | 2022-10-21 05:11:59 -03:00 |  | 
			
				
					|  | 051b98bc02 | fix(barrel_shifter): should not modify cpsr when amount == 0 | 2022-10-21 05:11:59 -03:00 |  | 
			
				
					|  | 5d0bc1b335 | chore(cpu): refactor the barrel shifter once again | 2022-10-21 05:11:59 -03:00 |  | 
			
				
					|  | 43d011538e | feat(cpu): implement ADC ADC interacting w/ the Barrel Shifter is not working though | 2022-10-21 05:11:59 -03:00 |  | 
			
				
					|  | f3ad5e90ff | feat(cpu): implement RRX for Barrel Shifter | 2022-10-21 05:11:58 -03:00 |  | 
			
				
					|  | 9b867c02e0 | feat(cpu): implement SUB in THUMB format 3 | 2022-10-21 05:11:58 -03:00 |  | 
			
				
					|  | 2ba09868ba | feat(cpu): implement ARM SUB in data processing | 2022-10-21 05:11:58 -03:00 |  | 
			
				
					|  | 9394754593 | feat(cpu): implement MVN | 2022-10-21 05:11:58 -03:00 |  | 
			
				
					|  | 41bab3d6ba | chore(cpu): refactor barrel shifter | 2022-10-21 05:11:58 -03:00 |  | 
			
				
					|  | 99b686b2d7 | fix(cpu): use barrel shifter in data processing immediates | 2022-10-21 05:11:58 -03:00 |  | 
			
				
					|  | daad98bbfe | feat(cpu): implement format 12 thumb instructions | 2022-10-21 05:11:57 -03:00 |  | 
			
				
					|  | 2fb01577af | feat(cpu): implement some already decoded format 3 instructions | 2022-10-21 05:11:57 -03:00 |  | 
			
				
					|  | 96d21f27a5 | feat(cpu): implement THUMB format 5 instructions | 2022-10-21 05:11:57 -03:00 |  | 
			
				
					|  | 793110f315 | chore: mgba log now supports printing THUMB instructions | 2022-10-21 05:11:57 -03:00 |  | 
			
				
					|  | 5ed5c5d52d | feat(cpu): implement like 1 THUMB instruction | 2022-10-21 05:11:57 -03:00 |  | 
			
				
					|  | 01385ee46b | chore: distinguish between undefined ARM and THUMB instr | 2022-10-21 05:11:57 -03:00 |  | 
			
				
					|  | 0eba3aca1f | chore(cpu): lay groundwork for THUMB instruction decoding and execution | 2022-10-21 05:11:57 -03:00 |  | 
			
				
					|  | 83a5370196 | chore(cpu): refactor ARM functions to make room for THUMB | 2022-10-21 05:11:56 -03:00 |  | 
			
				
					|  | b0b6247f06 | fix(cpu): fix conditions for GT cond | 2022-10-21 05:11:56 -03:00 |  | 
			
				
					|  | 2a33716166 | fix(cpu): fix imm value calculation in MSR | 2022-10-21 05:11:56 -03:00 |  | 
			
				
					|  | 9b26454c72 | fix(cpu): resolve off-by-one error when executing LDM | 2022-10-21 05:11:56 -03:00 |  | 
			
				
					|  | 97b933d9ea | feat(cpu): implement branch and exchange If I want to continue with armwrestler, I'll have to implement
THUMB instructions now | 2022-10-21 05:11:56 -03:00 |  | 
			
				
					|  | ff70aadfdb | fix(cpu): make Data Processing instructions r15-aware | 2022-10-21 05:11:55 -03:00 |  | 
			
				
					|  | ae53f92d40 | fix(cpu): make LDRH and STRH aware of r15 | 2022-10-21 05:11:55 -03:00 |  | 
			
				
					|  | f51e1d3154 | fix(cpu): account for r15 in LDR and STR instructions | 2022-10-21 05:11:55 -03:00 |  | 
			
				
					|  | a21f94569f | fix(cpu): flip two branches in PSR Transfer execution | 2022-10-21 05:11:55 -03:00 |  | 
			
				
					|  | b9255bffe7 | feat(cpu): implement MSR and MRS | 2022-10-21 05:11:55 -03:00 |  | 
			
				
					|  | e1f8400343 | feat(cpu): stub PSR Transfer instructions | 2022-10-21 05:11:55 -03:00 |  | 
			
				
					|  | 52493831cc | chore(io): implement IE and IME | 2022-10-21 05:11:54 -03:00 |  | 
			
				
					|  | 00ba7afac4 | chore: remove some magic constants | 2022-10-21 05:11:54 -03:00 |  | 
			
				
					|  | c703352ac3 | Merge branch 'main' of ssh://musuka.dev:2222/paoda/zba | 2022-10-21 05:11:54 -03:00 |  | 
			
				
					|  | 97e663febf | fix(bus): remove accidental recursion | 2022-10-21 05:11:54 -03:00 |  | 
			
				
					|  | 3891b54f42 | chore: ignores for building on windows | 2022-10-21 05:11:54 -03:00 |  | 
			
				
					|  | 9a5959e46c | fix(cpu): write results of ORR to destination register | 2022-10-21 05:11:54 -03:00 |  | 
			
				
					|  | 780c717409 | feat(cpu): implement TEQ | 2022-10-21 05:11:53 -03:00 |  | 
			
				
					|  | 34c6df344d | feat(cpu): Implement ORR | 2022-10-21 05:11:53 -03:00 |  | 
			
				
					|  | 670347d4a0 | feat(bus): implement IWRAM and EWRAM | 2022-10-21 05:11:53 -03:00 |  | 
			
				
					|  | e0c4b3b407 | fix(ppu): properly access Mode 4 palette | 2022-10-21 05:11:53 -03:00 |  | 
			
				
					|  | cffffab8ea | feat(cpu): refactor LDM/STM | 2022-10-21 05:11:53 -03:00 |  | 
			
				
					|  | 527bd2889e | feat(cpu): implement LDM/STM | 2022-10-21 05:11:53 -03:00 |  | 
			
				
					|  | 15dc4ce03a | chore(io): DISPSTAT bits 3 and 4 better match GBATEK documentation | 2022-10-21 05:11:52 -03:00 |  | 
			
				
					|  | 4f629227ab | fix(cpu): fix off-by-word bug in BL | 2022-10-21 05:11:52 -03:00 |  | 
			
				
					|  | caa799853e | feat(bus): have VCOUNT be addressable on the bus | 2022-10-21 05:11:52 -03:00 |  | 
			
				
					|  | 3590215d33 | feat(ppu): implement Mode 4 Implementation is not tested. Pending on LDM and STM so that I can
run beeg.gba | 2022-10-21 05:11:52 -03:00 |  | 
			
				
					|  | d6aafc61bd | chore(io): rename some io bitfield fields | 2022-10-21 05:11:52 -03:00 |  | 
			
				
					|  | 357211a4cc | chore: remove premature inlines | 2022-10-21 05:11:52 -03:00 |  |