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738 Commits

Author SHA1 Message Date
Rekai Nyangadzayi Musuka f0dca29836 fix(dma): apply proper masks to dma i/o 2022-10-29 04:53:21 -03:00
Rekai Nyangadzayi Musuka c75682dbd4 fix(apu): some invalid i/o registers should read 0x0000 2022-10-29 04:29:44 -03:00
Rekai Nyangadzayi Musuka 36832ba1fb feat(apu): impelement all apu i/o reads 2022-10-29 04:24:06 -03:00
Rekai Nyangadzayi Musuka 647bd83224 chore(io): rewrite certain error messages 
We can do this now that we know that it won't be because of any
unimplemented feature in some circumstances
 2022-10-29 02:37:54 -03:00
Rekai Nyangadzayi Musuka c831f67d1a feat(timer): implemeant all timer i/o reads 2022-10-29 01:37:28 -03:00
Rekai Nyangadzayi Musuka 268961262d feat(dma): implement all dma i/o reads 2022-10-29 01:30:12 -03:00
Rekai Nyangadzayi Musuka 3e62feacba feat(ppu): implement all ppu i/o reads 2022-10-29 01:29:27 -03:00
Rekai Nyangadzayi Musuka d859cee365 style: get rid of unnecessary type coersion 2022-10-29 00:06:08 -03:00
Rekai Nyangadzayi Musuka 371cf4cc12 style(i/o, ppu): refactor ppu i/o 2022-10-28 23:45:54 -03:00
Rekai Nyangadzayi Musuka 10aec67ee0 emu: implement thread sleep in granular steps 2022-10-28 21:58:55 -03:00
Rekai Nyangadzayi Musuka 4eb715a138 doc(emu): properly document + simply constants 2022-10-28 21:57:30 -03:00
Rekai Nyangadzayi Musuka 14b24787ab style: remove unnecessary imports 2022-10-28 21:56:55 -03:00
Rekai Nyangadzayi Musuka eb7ffa29f4 fix(apu): pause device on mute instead of writing silence 2022-10-27 09:11:08 -03:00
Rekai Nyangadzayi Musuka 4b8ed3cebb fix(io): resolve embarrasingly simple regression 
introduced in 21eddac31e
 2022-10-23 04:39:31 -03:00
Rekai Nyangadzayi Musuka 928ce674d9 fix(cpu): fix obscure LDRSH behaviour 2022-10-22 22:12:41 -03:00
Rekai Nyangadzayi Musuka 945dbec013 fix(open-bus): don't rotate result 
Rotating misaligned reads is the responsibility of the CPU
 2022-10-22 21:32:36 -03:00
Rekai Nyangadzayi Musuka dd98066a34 Merge pull request 'feat(dma): Implement DMA Latch' (#5) from dma-latch into main 
Reviewed-on: #5
 2022-10-22 23:53:21 +00:00
Rekai Nyangadzayi Musuka a2868dfe9e feat(dma): Implement DMA Latch 2022-10-22 20:52:02 -03:00
Rekai Nyangadzayi Musuka 22979d9450 fix(bios): fix regression 
was reading addr_latch + 8, which is a remnant from when I was faking
the pipeline
 2022-10-22 15:33:36 -03:00
Rekai Nyangadzayi Musuka 712c58391d chore(config): change defaults in config.toml 2022-10-21 06:01:22 -03:00
Rekai Nyangadzayi Musuka 407774d798 chore(gitignore): update .gitignore 2022-10-21 04:40:55 -03:00
Rekai Nyangadzayi Musuka 16f8f4c953 feat: write default config.toml if it doesn't exist 
also resolves panic on missing /zba or /zba/save directory by ensuring
those directories exist as soon as we know the data directory
 2022-10-21 04:39:16 -03:00
Rekai Nyangadzayi Musuka 143ffd95f7 chore: update README 2022-10-21 02:59:43 -03:00
Rekai Nyangadzayi Musuka 250ff25ed7 Merge pull request 'Configure SDL2 to use OpenGL' (#4) from opengl into main 
Reviewed-on: #4
 2022-10-20 01:41:50 +00:00
Rekai Nyangadzayi Musuka eff52ac1bb fix(opengl): properly control whether vsync is enabled 2022-10-17 20:31:42 -03:00
Rekai Nyangadzayi Musuka e60b556f72 chore(ppu): remove BGR555 -> RGBA888 LUT 
LUT probably couldn't fit in CPU cache anyways.

TODO: Consider whether LUTs for separate channels (size 32 * 3 * 3
instead of std.math.maxInt(u15))
 2022-10-17 20:31:42 -03:00
Rekai Nyangadzayi Musuka 3a3e6acc6a chore: replace OpenGL 4.5 bindings with OpenGL 3.3 2022-10-17 20:31:42 -03:00
Rekai Nyangadzayi Musuka 4b4bc7f894 chore: remove unnecessary ptr cast 2022-10-17 20:31:42 -03:00
Rekai Nyangadzayi Musuka 325208d460 feat: implement better Colour Emulation 2022-10-17 20:31:42 -03:00
Rekai Nyangadzayi Musuka f44a1a49fd fix: lower required OpenGL version + resolve offset bug 2022-10-17 20:31:42 -03:00
Rekai Nyangadzayi Musuka 1575f517a9 feat: use opengl 
TODO:
- Texture isn't scaling properly
- I need to reverse the colours in the frag shader
 2022-10-17 20:31:42 -03:00
Rekai Nyangadzayi Musuka 26dba16789 chore(gpio): add missing errdefer 2022-10-17 20:01:50 -03:00
Rekai Nyangadzayi Musuka b133880064 chore(main): report errors slightly better 2022-10-17 18:30:40 -03:00
Rekai Nyangadzayi Musuka 2474daa3ae chore(config): add log message 2022-10-17 17:39:02 -03:00
Rekai Nyangadzayi Musuka fc53a40b3c feat(config): add option to skip BIOS 2022-10-17 17:31:07 -03:00
Rekai Nyangadzayi Musuka 7097e21361 feat(cli): Add option to skip BIOS 2022-10-17 17:25:04 -03:00
Rekai Nyangadzayi Musuka a9fe24b1b4 chore: Update README.md 2022-10-17 17:00:54 -03:00
Rekai Nyangadzayi Musuka f38c840d32 Merge pull request 'Draft: Implement Instruction Pipeline' (#3) from pipeline into main 
Reviewed-on: #3
 2022-10-17 19:42:42 +00:00
Rekai Nyangadzayi Musuka 19e70c39d1 feat(config): add config option to mute ZBA 2022-10-13 00:54:15 -03:00
Rekai Nyangadzayi Musuka 5a72a8e7f3 chore(config): add example config file 2022-10-13 00:46:18 -03:00
Rekai Nyangadzayi Musuka 7b146ad7ca fix(bios): set addr_latch even if bios is skipped 2022-10-13 00:35:22 -03:00
Rekai Nyangadzayi Musuka 822eed1f3a fix(bus): make open bus impl aware of CPU pipeline 2022-10-13 00:35:22 -03:00
Rekai Nyangadzayi Musuka b37a14900c style(bus): cpu ptr doesn't need to be optional 2022-10-13 00:35:22 -03:00
Rekai Nyangadzayi Musuka f5bd20bc2a style: code cleanup 2022-10-13 00:35:22 -03:00
Rekai Nyangadzayi Musuka d3514b14f3 fix: resolve timing regressions 
make sure to use fetch timings when fetching instructions
 2022-10-13 00:35:20 -03:00
Rekai Nyangadzayi Musuka 06c60dad74 fix: rename Pipline to Pipeline 2022-10-13 00:34:18 -03:00
Rekai Nyangadzayi Musuka 870e991862 feat: working pipeline implementation 2022-10-13 00:34:18 -03:00
Rekai Nyangadzayi Musuka 5bb5bdf389 chore: refactor ARM/THUMB data processing instructions 2022-10-13 00:34:18 -03:00
Rekai Nyangadzayi Musuka a3996cbc58 fix: don't flush pipeline when reloading CPSR in ARM Data Processing 2022-10-13 00:34:18 -03:00
Rekai Nyangadzayi Musuka a948c6f900 chore: don't write to CPSR + swap with SPSR at the same time 2022-10-13 00:34:18 -03:00