chore: don't init bus in Arm7tdmi init
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aa19ef5f71
commit
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@ -7,7 +7,6 @@ const Bitfield = @import("bitfield").Bitfield;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const Scheduler = @import("scheduler.zig").Scheduler;
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const FilePaths = @import("util.zig").FilePaths;
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const FilePaths = @import("util.zig").FilePaths;
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const Allocator = std.mem.Allocator;
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const File = std.fs.File;
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const File = std.fs.File;
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// ARM Instructions
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// ARM Instructions
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@ -234,7 +233,7 @@ pub const Arm7tdmi = struct {
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r: [16]u32,
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r: [16]u32,
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sched: *Scheduler,
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sched: *Scheduler,
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bus: Bus,
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bus: *Bus,
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cpsr: PSR,
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cpsr: PSR,
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spsr: PSR,
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spsr: PSR,
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@ -252,11 +251,11 @@ pub const Arm7tdmi = struct {
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log_buf: [0x100]u8,
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log_buf: [0x100]u8,
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binary_log: bool,
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binary_log: bool,
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pub fn init(alloc: Allocator, sched: *Scheduler, paths: FilePaths) !Self {
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pub fn init(sched: *Scheduler, bus: *Bus) Self {
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return Self{
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return Self{
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.r = [_]u32{0x00} ** 16,
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.r = [_]u32{0x00} ** 16,
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.sched = sched,
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.sched = sched,
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.bus = try Bus.init(alloc, sched, paths),
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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.spsr = .{ .raw = 0x0000_0000 },
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.banked_fiq = [_]u32{0x00} ** 10,
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.banked_fiq = [_]u32{0x00} ** 10,
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@ -268,10 +267,6 @@ pub const Arm7tdmi = struct {
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};
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};
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}
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}
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pub fn deinit(self: Self) void {
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self.bus.deinit();
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}
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pub fn useLogger(self: *Self, file: *const File, is_binary: bool) void {
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pub fn useLogger(self: *Self, file: *const File, is_binary: bool) void {
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self.log_file = file;
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self.log_file = file;
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self.binary_log = is_binary;
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self.binary_log = is_binary;
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@ -433,13 +428,13 @@ pub const Arm7tdmi = struct {
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const opcode = self.fetch(u16);
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const opcode = self.fetch(u16);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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thumb.lut[thumbIdx(opcode)](self, &self.bus, opcode);
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thumb.lut[thumbIdx(opcode)](self, self.bus, opcode);
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} else {
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} else {
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const opcode = self.fetch(u32);
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const opcode = self.fetch(u32);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode);
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if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
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if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) {
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arm.lut[armIdx(opcode)](self, &self.bus, opcode);
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arm.lut[armIdx(opcode)](self, self.bus, opcode);
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}
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}
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}
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}
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}
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}
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@ -573,7 +573,7 @@ pub const Ppu = struct {
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// See if HBlank DMA is present and not enabled
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// See if HBlank DMA is present and not enabled
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if (!self.dispstat.vblank.read())
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if (!self.dispstat.vblank.read())
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pollBlankingDma(&cpu.bus, .HBlank);
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pollBlankingDma(cpu.bus, .HBlank);
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self.dispstat.hblank.set();
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self.dispstat.hblank.set();
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self.sched.push(.HBlank, 68 * 4 -| late);
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self.sched.push(.HBlank, 68 * 4 -| late);
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@ -615,7 +615,7 @@ pub const Ppu = struct {
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self.aff_bg[1].latchRefPoints();
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self.aff_bg[1].latchRefPoints();
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// See if Vblank DMA is present and not enabled
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// See if Vblank DMA is present and not enabled
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pollBlankingDma(&cpu.bus, .VBlank);
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pollBlankingDma(cpu.bus, .VBlank);
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}
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}
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if (scanline == 227) self.dispstat.vblank.unset();
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if (scanline == 227) self.dispstat.vblank.unset();
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16
src/main.zig
16
src/main.zig
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@ -5,6 +5,7 @@ const known_folders = @import("known_folders");
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const clap = @import("clap");
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const clap = @import("clap");
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const Gui = @import("Gui.zig");
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const Gui = @import("Gui.zig");
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const Bus = @import("core/Bus.zig");
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const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
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const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi;
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const Scheduler = @import("core/scheduler.zig").Scheduler;
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const Scheduler = @import("core/scheduler.zig").Scheduler;
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const FilePaths = @import("core/util.zig").FilePaths;
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const FilePaths = @import("core/util.zig").FilePaths;
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@ -42,13 +43,16 @@ pub fn main() anyerror!void {
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var scheduler = Scheduler.init(allocator);
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var scheduler = Scheduler.init(allocator);
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defer scheduler.deinit();
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defer scheduler.deinit();
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var arm7tdmi = try Arm7tdmi.init(allocator, &scheduler, paths);
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var bus = try Bus.init(allocator, &scheduler, paths);
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arm7tdmi.bus.attach(&arm7tdmi);
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defer bus.deinit();
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if (paths.bios == null) arm7tdmi.fastBoot();
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defer arm7tdmi.deinit();
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var gui = Gui.init(arm7tdmi.bus.pak.title, width, height);
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var arm7tdmi = Arm7tdmi.init(&scheduler, &bus);
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gui.initAudio(&arm7tdmi.bus.apu);
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bus.attach(&arm7tdmi); // TODO: Shrink Surface (only CPSR and r15?)
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if (paths.bios == null) arm7tdmi.fastBoot();
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var gui = Gui.init(bus.pak.title, width, height);
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gui.initAudio(&bus.apu);
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defer gui.deinit();
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defer gui.deinit();
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try gui.run(&arm7tdmi, &scheduler);
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try gui.run(&arm7tdmi, &scheduler);
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